Abstract
Through Silicon Via (TSV) technology with micro joint has been identified as the 3D package technology to overcome the limitations of I/O density and enhances the system performance compared to that of the conventional flip chip packages. One of the challenges of the reliable 3D TSV packages is stacking and joining of thin wafers or dies. The conventional micro joining methods, such as use of solder bumps, cause many reliability problems, such as intermetallic compound (IMC) formation, electromigration, delamination, creep, and fatigue problems. As an alternative, copper-to-copper direct bonding (CuDB) has been proposed. CuDB enables reduction in fabrication process steps, can obtain higher interconnect density and enhanced thermal conductivity. However, the CuDB interface has potential reliability risk since the bonding is typically performed by compression at high temperature. Several prior studies have reported formation of small voids between the bonding interfaces of the CuDB that can lead to crack initiation, propagation and thereby delamination of the entire interface. The defect can result in failure of the entire package during its fabrication process or operation.This study is risk assessment of possibility of crack propagation at the CuDB interface using fracture mechanics approach. Finite element (FE) analysis and design of experiments (DOE) are used. A crack is assigned at the interface of the CuDB to mimic a small void. Initial crack location and dimensional variables (Initial crack length, Cu pad diameter and pitch, and TSV diameter and pitch) are varied to quantify the risk. The strain energy release rate (SERR) around the crack tip is calculated and compared with the critical SERR, obtained by experiments, to judge the possibility of crack propagation. Sensitivity analysis of design parameters is conducted. As a result, this study provides design recommendations that can minimize interfacial failure of the CuDB. In addition, this study explores various numerical modeling methodologies that can be implemented for efficient failure prediction of the interfaces.
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