Through Glass Via Research Articles

General Analytical Method for Investigating Parasitic Characteristics of Through Glass Vias (TGVs) in 3-D Integration

General Analytical Method for Investigating Parasitic Characteristics of Through Glass Vias (TGVs) in 3-D Integration

Research of Vertical via Based on Silicon, Ceramic and Glass.

With the increasing demand for high-density integration, low power consumption and high bandwidth, creating more sophisticated interconnection technologies is becoming increasingly crucial. Three-dimensional (3D) integration technology is known as the fourth-generation packaging technology beyond Moore's Law because of its advantages of low energy consumption, lightweight and high performance. Through-silicon via (TSV) is considered to be at the core of 3D integration because of its excellent electrical performance, lower power consumption, wider bandwidth, higher density, smaller overall size and lighter weight. Therefore, the particular emphasis of this review is the process flow of TSV technology. Among them, the research status of TSV hole etching, deep hole electroplating filling and chemical mechanical planarization (CMP) in TSV preparation process are introduced in detail. There are a multitude of inevitable defects in the process of TSV processing; thus, the stress problems and electrical characteristics that affect the reliability of TSV are summarized in this review. In addition, the process flow and process optimization status of through ceramic via (TCV) and through glass via (TGV) are discussed.

A Low-Loss Bandpass Filter With Stacked Double-Layer Structure Using Glass-Based Integrated Passive Device Technology

In this letter, a third-order low Insertion loss bandpass filter (BPF) is proposed by using a stacked double-layer structure through the technologies of the glass-based integrated passive device (IPD) and the through glass vias (TGVs). First, a stacked multi-layer structure was introduced to create a 3D-inductor of large inductance with a high Q factor. Then, an air cavity Metal-Insulator-Metal (MIM) structure was used to upgrade the Q factor of the capacitor. Therefore, a third-order low-loss small-sized bandpass filter can be generated by utilizing these LC elements of high Q factors. Experimental results show that the proposed BPF’s size and insertion loss is 0.018λ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0</sub> × 0.013λ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0</sub> and 0.81 dB, respectively. In comparison with the existing design, the proposed BPF shows the superior advantages of smaller size and lower insertion loss.

MMIC-to-Dielectric Waveguide Transitions for Glass Packages Above 150 GHz

In this work, novel concepts of an electromagnetically coupled transition and a galvanically coupled transition in glass technology are presented. This enables efficient coupling of signals above 150 GHz into a dielectric waveguide (DWG). Laser-induced deep etching (LIDE) technology provides fabrication of glass holes, cavities, and cutouts with a precision suitable for use in highly integrated mm-wave modules. Based on the package concept presented by Galler et al. (2022), this article introduces an ultracompact galvanically isolated transition from monolithic microwave integrated circuit (MMIC) to a mechanically flexible DWG, offering a minimum insertion loss of 2.95 dB. The simple fabrication provides a cost-effective variant for modern system-in-package solutions. In addition, a galvanic through-plating of the glass cover with through-glass vias (TGVs) and a ring slot structure for the excitation of a DWG are presented. Thereby, the integration density and performance can be further increased. A minimum insertion loss of 2.62 dB within a large 1-dB bandwidth of 18 GHz around the operating frequency of 166 GHz is verified by measurement. Both the transitions cover a high integration density, hermetic sealing, and modular use suitable for requirements of today’s modern radar and communication packages.

Fabrication of a transparent array of penetrating 3D microelectrodes with two different heights for both neural stimulation and recording

Microelectrode array (MEA) is one of the representative platforms for recording and stimulating neurons to explore their populational electrophysiological activities. Due to the layered structures of the nervous system, various three-dimensional (3D) MEAs have been used to reach specific target depths of neuronal tissues. But it is still difficult to monolithically fabricate various heights of microelectrodes, particularly with optical transparency. Here, we present a 3D MEA with different heights fabricated by multi-step silicon deep reactive ion etching. The microelectrodes were embedded in reflowed glass for high transparency which enables both neural tissue observation and optical stimulation. The heights of microelectrodes were well controlled by our fabrication processes and electrical connections were made with through glass vias (TGVs) to the bottom side for individual addressing. To confine electric stimulation in a small area, we used microelectrodes neighboring a stimulation electrode as local returns. The feasibility of the fabricated MEA was demonstrated by stimulating the mouse retina and successfully recording spikes of ganglion cells located near the stimulation site. Consistent with our COMSOL simulation, the ex vivo experimental results showed the stimulation current confinement was effective. Our study provides a new tool for 3D nervous systems and its fabrication method.

High Inductance Density Glass Embedded Inductors for 3-D Integration

Compared with silicon-based inductors, the inductors with through glass via (TGV) technology have significantly improved in quality ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$Q)$</tex-math> </inline-formula> factor. On the basis of TGV technology, a new type of 3-D embedded inductor is designed for the application scenarios with high inductance density. Through this research, a new preparation process is proposed to reduce the diameter of glass porous. On the basis of fully metallizing the glass porous, larger inductance density is achieved. The fabrication procedure requires grooving inside the glass substrate. In order to ensure the normal metal wiring on the surface, the cavity is filled with organic matter. Finally, the high-density, small-porous inductor array achieves an inductance density of 67.9 nH/mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{2}$</tex-math> </inline-formula> , which is three times higher than the previous glass inductance density. At the same time, the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$Q$</tex-math> </inline-formula> factor is 49 and the self-resonance frequency (SRF) is 5.6 GHz.

Electrochemical discharge machining of a high-precision micro-holes array in a glass wafer using a damping and confinement technique

Due to the unstable gas film, it is still a big challenge to achieve high repeatability and quality in electrochemical discharge machining (ECDM) of micro-hole arrays in glass. Based on our previous research on ECDM in micro channels, the present work uses a non-Newtonian fluid electrolyte (non-NTF electrolyte) in ECDM to further achieve a high uniform precision and quality micro-holes array in glass through the damping and confinement effect. The results revealed that an average entrance diameter of 343.8 ± 3.47 μm (mean ± standard deviation) and average heat-affected zone (HAZ) width of 18.01 ± 1.52 μm were successfully fabricated in a 300-μm-thick glass wafer. As compared to the conventional KOH electrolyte, the entrance overcut and the HAZ width of micro-holes were reduced by 43.84 %, and 64.81 %, respectively, while the repeatability improved by 67.92 %. The non-NTF electrolyte concentration and the tool rotation speed were also found to play a significant role in the damping and confinement effect, significantly affecting the geometrical properties of the micro-holes. Furthermore, the micro-holes array was filled with copper to form through glass vias (TGVs), and a standard deviation of the Kelvin resistance of TGVs was only 5.35 mΩ, further demonstrating an excellent repeatability and localization of ECDM micro-holes using a non-NTF electrolyte. The results illustrate that employing a non-NTF electrolyte is a simple way to increase the stability of the gas film and to improve the repeatability and localization of ECDM micro-holes.

Die-embedded packaging using Corning® multi-layered glass

Die-embedded (DE) packaging technologies in recent years have ventured into advanced packaging structures, such as fan-out wafer level packages (FOWLPs) or package-on-packages (PoPs). They offer higher density at lower costs, despite many challenges, such as the die-shift and warpage problems often observed during the molding process, caused by the high shrinkage and high coefficients of thermal expansion (CTEs) of the molding materials. This in turn makes it difficult to accurately mount the high-density fine-pitch bumps and adversely affects the overall yield, especially in processes using large-size substrates. Glass, known for its superior dimensional and thermal stability and its low or tunable CTEs, can be advantageous in reducing die-shift and warpages as opposed to other alternative material solutions for the molding process. In this paper, we propose a packaging solution based on a glass substrate incorporating a plurality of precisely dimensioned cavities, with a chip positioned in each cavity to prevent them from shifting during processing. Corning® Adaptive Formed Glass (AFG), a laminate glass with a unique clad/core/clad structure, allows for effectively forming cavities with high dimensional precision and positional accuracies as well as surface flatness through a wet etch process. Using a 0.5mm thick laminate Corning® AFG glass, we successfully designed and fabricated three types of DE packages with lab scale tools at Korea Electronics Technology Institute (KETI): single- and double-sided DE packages, and package-on-packages (POPs). High etching selectivity over 20:1, which was achieved by carefully designing the core and clad glass compositions, enabled a wet-etch cavity forming process with accurate cavity depths and flat bottom surfaces (&lt; ± 2.5μm) with relative ease. A double-sided DE package with a total thickness of 600μm was fabricated with two 125μm-thick IC chips, one embedded on each side of the substrate, and connected by metallized through glass vias (TGVs). A POP measured at 5.1×5.1×1.27 mm3 was also successfully demonstrated by using two built-in double-sided DE packages joined by flip-chip bonding, equivalent to stacking four layers of conventional single-sided DE packages. The double-sided DE packages and POPs presented in this paper are believed to be the world’s first demonstration on glass. The work also manifests the immense potential of Corning® AFG glass in enabling higher density IC packaging and large-size panel-level (or wafer-level) packaging.

Fabrication of Panel-Level Glass Substrates with Complete Design Freedom using LIDE

In this work, we present examples of highly reproducible, accurate and extremely cost-effective wafer- and panel-level fabrication of glass interposers, free of any process-dependent design limitations where any distribution and density of Through-Glass Vias (TGV) with any cross-section geometries and aspect-ratios, is possible. Glass has recently garnered significant interest for its many applications in the semiconductor packaging industry, particularly as a core substrate material for interposer applications. Glass has a unique set of material properties with great relevance for this industry, such as very high electrical resistivity, low loss tangent and low dielectric constant. Glass also exhibits low warpage due to its relatively low Young‘s Modulus while still being compatible with Silicon in terms of CTE and, when processed using a technology that doesn’t induce the generation of any defects such as microcracks or thermally-induced stress, it is highly reliable during processing and operation. Laser Induced Deep Etching (LIDE®) technology is a 2.5D glass processing technology with complete design freedom purposedly developed for cost-effective, high-volume fabrication of defect-free glass components. Despite its many advantages as an interposer material in relation to Si, its application has been hindered by the lack of reliable, precise, and cost-effective processing technologies. LIDE® consists of a two-step process: i) a very fast maskless and direct-write laser process induces subtle and very localized modification in the glass substrate, requiring a single laser pulse to modify the whole glass thickness; and ii) a wet-etching process done in batch, where the whole glass substrate is subjected to the action of an etchant and where the removal of glass occurs at an accelerated rate in the laser-modified regions. This process flow allows LIDE to fabricate several thousands of TGV per second, completely free of any defects, with a sub-micron point-to-point accuracy and ± 5 µm accuracy (cumulative) across a 510 mm x 515 mm glass panel (Cp &gt; 1.33), in any glass type, with aspect-ratios from 1:10 to 1:50 (diameter:depth).

Extracting and Analyzing the S-Parameters of Vertical Interconnection Structures in 3D Glass Packaging

In order to effectively employ through-glass vias (TGVs) for high-frequency software package design, it is crucial to accurately characterize the S-parameters of vertical interconnection structures in 3D glass packaging. A methodology is proposed for the extraction of precise S-parameters using the transmission matrix (T-matrix) to analyze and evaluate the insertion loss (IL) and reliability of TGV interconnections. The method presented herein enables the handling of a diverse range of vertical interconnections, encompassing micro-bumps, bond-wires, and a variety of pads. Additionally, a test structure for coplanar waveguide (CPW) TGVs is constructed, accompanied by a comprehensive description of the equations and measurement procedure employed. The outcomes of the investigation demonstrate a favorable concurrence between the simulated and measured results, with analyses and measurements conducted up to 40 GHz.

A Fully Integrated Solid-State Charge Detector with through Fused Silica Glass via Process

A charge detector is a vital component in neutrino and dark matter detection. The integration of a charge collector in the form of flat pads and readout modules has been proposed as an optimization method as it can reduce noise and installation complexity. As a substrate, fused silica glass has attracted considerable attention due to its low radioactive background properties. In this research, based on the application requirements of a high charge collection rate and low noise, the structure of the charge detector was designed using calculation and simulation methods. The entire manufacturing process is described. In addition, a novel through glass via (TGV) structure composed of a conformal metal layer and a photosensitive material that is easy to fabricate and has high morphological compatibility with via filling is proposed. The curing property of the new material was characterized. A fully integrated solid-state charge detector with 32 groups of TGVs was realized. Additionally, the electrical properties of key structures were tested and analyzed.

Fabrication of Substrate-Integrated Waveguide Using Micromachining of Photoetchable Glass Substrate for 5G Millimeter-Wave Applications

A millimeter-wave substrate-integrated waveguide (SIW) was firstly demonstrated using the micromachining of photoetchable glass (PEG) for 5G applications. A PEG substrate was used as a dielectric material of the SIW, and its photoetchable properties were used to fabricate through glass via (TGV) holes. Instead of the conventional metallic through glass via (TGV) array structures that are typically used for the SIW, two continuous empty TGV holes with metallized sidewalls connecting the top metal layer to the bottom ground plane were used as waveguide walls. The proposed TGV walls were fabricated by using optical exposure, heat development and anisotropic HF (hydrofluoric acid) etching of the PEG substrate, followed by a metal sputtering technique. The SIW was fed by microstrip lines connected to the waveguide through tapered microstrip-to-waveguide transitions. The top metal layer, including these feedlines and transitions, was fabricated by selective metal sputtering through a silicon shadow mask, which was prefabricated by a silicon deep-reactive ion-etching (DRIE) technique. The developed PEG-based process provides a relatively simple, wafer-level manufacturing method to fabricate the SIW in a low-cost glass dielectric substrate, without the formation of individual of TGV holes, complex time-consuming TGV filling processes and repeated photolithographic steps. The fabricated SIW had a dimension of 6 × 10 × 0.42 mm3 and showed an average insertion loss of 2.53 ± 0.55 dB in the Ka-band frequency range from 26.5 GHz to 40 GHz, with a return loss better than 13.86 dB. The proposed process could be used not only for SIW-based devices, but also for various millimeter-wave applications where a glass substrate with TGV structures is required.

Wideband Analysis and Prolongation of Surrounding TGVs Shielding Structure in 3-D ICs

Through glass vias (TGVs) with low substrate loss are subjected to signal distortion issues. This letter proposes a wideband scalable model for assessing signal reliability and rationalizing 3-D integrated design in glass interposers. The established equivalent circuit model is derived for extracting the parasitic parameters of the signal transmission unit, and the relevant variables stem from the geometric dimension parameters. The result of comparative analysis uncovers that the simulation results are in excellent accordance with the analytical model. Furthermore, seven crosstalk shielding topologies are proposed, and their noise suppression ability is analyzed. Such the shielding structures can not only reach the insertion loss (IL) performance below 0.15 dB but also achieve the crosstalk suppression capability exceeding 60 dB even at 40 GHz. Feasible strategies are proposed to trade off IL, noise isolation (NI), and occupied area in order to match suitable application scenarios, which can provide a reference for layout design.

Evaluation of the helium hermeticity reliability of copper through-glass vias

This work aims to understand and assess the helium hermeticity reliability of metallized copper (Cu) through-glass vias (TGVs) made in Corning® HPFS® Fused Silica glass substrate. To assess this, the Cu TGV wafers were subjected to numerous stringent environmental reliability tests that includes high temperature storage (HTS) at 125 °C, highly accelerated stress testing (HAST), 130 °C/85 % RH and thermal shock (−40 °C/125 °C). Using a helium leak rate of >1.0 × 10−8 atm·cm3/s as the failure criteria, it was found that all the Cu TGV wafers used in this study significantly outperformed specification requirements, irrespective of the harsh environmental conditions that they were subjected to. This finding clearly attests to the robustness and suitability of Cu TGV wafers used in this study for stringent helium hermeticity requirement applications. At the completion of the tests, no failures were found for all samples subjected to thermal shock and HTS even after 9000 cycles and 4600 h respectively. For HAST samples that failed after exposure times of 400 h and 1500 h, it was found that the root cause for their failure was due to the erosion of Cu at the titanium (Ti)–Cu interface, caused by the formation of CuO and/or Cu2O. This led to sidewall debonding of the Ti–Cu interface, resulting in helium leak rates > 1.0 × 10−8 atm·cm3/s. Additionally, higher HAST exposure time was found to lead to increased degradation of the Ti–Cu interface.

Formation of high aspect ratio through-glass vias by the combination of Ultrasonic micromachining and copper electroplating

Fabrication of high aspect ratio (>5) multiple copper-filled through-holes in non-conductive materials like glass and single-crystal‑silicon is reported by using a faster (>8 μm/s) ultrasonic micromachining (USM). A customized stainless tool having multiple tips arranged in a 6 × 6 area-array manner was used with ~1 μm-size Silicon carbide (SiC) abrasive particles. Numerical simulations were performed to find a suitable horn to reduce the losses during the transmission of ultrasonic wave propagation. A tapered horn profile was chosen to transmit the vibrations uniformly from the ultrasonic head to the multiple tips. A novel technique was proposed to measure the vibration amplitude at different ultrasonic power ratings. >250 experiments were carried out to investigate the effect of ultrasonic power ratings and tool feed rate on the geometric characteristic of microholes. Average etch rates as high as 8 μm/s and 6 μm/s were obtained for glass and silicon, respectively. These average etch rates are higher than those obtained with plasma etching and electrochemical discharge machining. Through-holes were created in a 1.1 mm thick glass substrate in <3 min. The importance of post-USM cleaning by ultrasonic agitation was highlighted, which helped in removing the abrasive particles stuck inside the through-holes. Copper was deposited inside these through-holes using a bottom-up electroplating approach. These copper-filled through-holes can be used as 3-dimensional (3D) interconnects required in various microsystems packaging-related applications.

Defect-Free Metallization of through-Glass Vias (TGV) with Engineered Geometry

Metallized through-glass vias (TGVs) have attracted interest in recent years due to their promise in enabling 2.5D and 3D electronic architectures and high-density MEMS devices. However, unlike metallization of PCB, metallization of TGV is challenging, and the electroplating processes are not well-established. This is mostly due to the form factor associated with TGVs - high length (L) and small diameter (Φ). During electrolytic process, for example electroplating of Copper inside the TGVs, such form factor often leads to severe transport limitation and subsequent formation of defects such as seams or voids in the samples. This has led to intense research in the past decade to develop special additives and processes to achieve defect-free filling of TGVs. It has been accepted that defect-free filling of TGVs is not possible without specialized additives in the solution. We will first demonstrate through simplified theoretical analysis and numerical modeling why that is the case when the geometry of the TGV has uniform cross-section. Even when the electroplating is carried out in in fully kinetic-controlled regime (Thiele modulus, μ ≤ 1), it will be clear from the analysis that a complete defect-free metallization is not achievable as long as the TGV cross-section is uniform. Next, we will report a novel metallization technique using an engineered via with an X-shape in the middle and operating in the kinetic-limited regime without the requirement of any specialized additives. This leads to Cu bridging of the vias at the waist, after which continued conformal plating ensures void-free filling. It would be emphasized that by combining these two effects – novel shape of TGV and kinetic controlled electroplating – void-free filling is achievable even in the absence of any additives. While additive-based bath is required and will continue to be used to optimize between plating speed, low stress and roughness of plated copper, the objective of this talk is to demonstrate the advantage of engineered vias in which even an additive-free bath could provide defect-free metallization. At very low current densities, an anomalous increase in thickness in the middle compared to the top of the via was observed. This cannot be explained by a simple 1D model and is an interesting next step in understanding additive-free electroplating.

Proposal and analysis of carbon nanotube based differential multibit through glass vias

The paper proposes glass as a potential material to advanced interposers for high-density three-dimensional (3-D) integration. On the basis of multi-bit through glass via (TGV) which comprises of TGVs filled with multi-walled carbon nanotubes (MWCNTs)/single-walled CNTs (SWCNTs) and separate conducting pads, the design of novel differential multibit-CNT TGVs (DM-TGCVs) is proposed and studied. The effective complex conductivity is formulated for accurate characterization of the high frequency behaviour of DM-TGCVs. A distributed π-type transmission line model for the modeling of DM-TGCVs is established and the frequency dependent impedance is extracted through partial element equivalent circuit (PEEC) technique. The influence of CNT filling ratio, probability of metallic fraction of CNTs, and CNTs as filler material on the resistance and inductance is also studied. Through the proposed analytical model, signal insertion loss of DM-TGCVs in the differential- and common-mode configurations is exhaustively investigated. Due to ultra-high electrical resistivity of glass (1012 − 1016 Ω-cm), signal loss in DM-TGCVs is determined by the conductor loss, which results in an improved electrical performance under differential-mode signaling than common-mode signaling approach. This phenomenon is unique to TGVs and totally different from the conventional through silicon vias, where signal loss is dominated by the dielectric loss at high frequencies. The magnitude of insertion loss (S21) for the proposed DM-TGCVs under differential-mode configuration w.r.t. differential TSVs (D-TSVs) and differential multibit CNT TSVs (DMC-TSVs) improves up to ∼ 44% and ∼22%, respectively for varying via radius. The DM-TGCVs also exhibit superior crosstalk inhibition capability and provide up to ∼89% and ∼24% improvements in crosstalk than D-TSVs and DMC-TSVs at f = 20 GHz. More importantly, DM-TGCVs provide one-third saving of the chip area compared to D-TSVs.

Nonlinear multiphoton modification of glass substrates for fabrication of high aspect ratio through-glass vias

To meet the demands of high-frequency wireless communications and Internet of Things (IoT) applications, modern integrated circuit (IC) packages should support operating frequencies in the GHz range and be implemented on fine substrate structures. Glass has many advantages as an interposer material for three-dimensional IC (3D-IC) designs, including tunable electrical and mechanical properties, amenability to large-scale processing, and high optical transparency in the visible range. Moreover, glass is easily processed to produce the through-glass vias (TGVs) required to realize high-frequency circuit designs and microelectromechanical systems devices. The present study proposes a method for patterning TGVs on glass substrates via a nonlinear multiphoton-assisted modification process performed using single-pulse irradiation by a 1030-nm picosecond laser. A theoretical model is additionally proposed to describe the glass substrate modification mechanism induced by the nonlinear multiphoton excitation effect. The feasibility of the proposed method is demonstrated by patterning a TGV array with a high aspect ratio of 1:10 and a taper angle of ∼2° on a Corning SGW3 glass substrate.

Etch the borosilicate glass to form a straight through-glass-via based on the FLACE technology

Interposers will become in demand for advanced electronic systems and through the substrate, vias are essential for 3D integration. A straight via is necessary because a tapered hole is accompanied by large signal loss. This article reports a straight through-glass-via (TGV) fabricated by femtosecond laser-assisted chemical etching (FLACE). The femtosecond laser was used to modify the glass substrates, and the modified glass samples were etched with hydrofluoric acid (HF) solution to form TGV. The effects of key processing parameters, including laser pulse energy, the number of burst pulses, and the HF solution concentration, on the TGV taper profile, were systematically investigated. It was found that The TGV taper sidewall angle decreases with increasing laser pulse energy and increases with increasing HF solution concentration. The number of bursts should be optimized because more than 10 bursts would prevent TGV formation. The study shows via etched in 3 wt% HF after irradiation with 3 bursts of 60 μJ can become approximately vertical. Among the three processing parameters, HF concentration was found to be the most crucial parameter. This work can serve as a critical reference for applications of TGV in high-performance 3D integrated circuits.

Development of 3D Wafer Level Hermetic Packaging with Through Glass Vias (TGVs) and Transient Liquid Phase Bonding Technology for RF Filter.

The development of 5G mobile communication created the need for high-frequency communication systems, which require vast quantities of radio frequency (RF) filters with a high-quality factor (Q) and low inband losses. In this study, the packaging of an RF filter with a through-glass via (TGV) interposer was designed and fabricated using a three-dimensional wafer-level package (3D WLP). TGV fabrication is a high-yielding process, which can produce high precision vias without masking and lithography and reduce the manufacturing cost compared with the through silicon via (TSV) solution. The glass interposer capping wafer contains Cu-filled TGV, a metal redistribution layer (RDL), and the bonding layer. The RF filter substrate with Au bump is bonded to the capping wafer based on Au-Sn transient liquid phase (TLP) bonding at 280 °C with a 40 kN (approximately 6.5 MPa) bonding force. Experimental results show that shear strengths of approx. 54.5 MPa can be obtained, higher than the standard requirement (~6 MPa). In addition, a comparison of the electrical performance of the RF filter package after the pre-conditional level three (Pre-Con L3) and unbiased highly accelerated stress (uHAST) tests showed no difference in insertion attenuation across the passband (<0.2 dB, standard value: <1 dB). The final packages passed the reliability tests in the field of consumer electronics. The proposed RF filter WLP achieves high performance, low cost, and superior reliability.