Temperature Coefficient Of Threshold Voltage Research Articles

Variation of Threshold Voltage With Temperature in Impact Ionization-Induced Steep Switching Si and Ge Junctionless MOSFETs

In this paper, we report on the anomalous behavior of threshold voltage ( ${V} _{\sf th})$ with temperature in junctionless (JL) transistors. It is shown that both positive and negative values of temperature coefficient of threshold voltage ( dV $_{\sf th}$ / dT ) in nMOS Si and Ge JL devices can occur at higher drain biases. At lower temperatures, ${V} _{\sf th}$ reduces with a decrease in temperature due to the dominance of bipolar effects over thermal generation of carriers, whereas at higher temperatures, thermal generation results in essentially unipolar characteristics, and ${V} _{\sf th}$ reduces with increase in temperature. It is also shown that zero temperature coefficient condition shall be nonexistent under dominant bipolar conduction over unipolar operation. Results show new viewpoints to understand the two contrasting physical mechanisms leading to positive and negative dV $_{\sf th}$ / dT values in JL devices.

The investigation of the zero temperature coefficient point of power MOSFET

The paper investigates the zero temperature coefficient (ZTC) point of power MOSFET, based on the output characteristic of power MOSFET, the temperature coefficient of threshold voltage and the carrier mobility. It is found that the gate voltage has a big effect on the ZTC point. The result indicates that there are three types of temperature coefficient under different gate voltage. When the gate voltage is near the threshold voltage, both the linear region and saturation region shows a large positive temperature coefficient. With the increase of gate voltage, the temperature coefficient of the linear region changes from positive to negative, when the saturation region still remains positive, giving rise to the ZTC point. When the gate voltage is high enough, the negative temperature coefficient is present on both the linear and saturation region, resulting in no ZTC point. According to the experimental result, the change of ZTC point as a function of temperature is larger when the gate voltage is higher. The carrier mobility is also discussed, displaying a positive temperature coefficient at low gate voltage due to the free charge screen effect.

A sub 1V CMOS bandgap reference with two diodes

A small size, sub 1V CMOS bandgap voltage reference with the temperature coefficient (TC) of 12ppm/°C from 0°C to 100°C is presented in this paper. The proposed circuit offers several performance advantages over previous bandgap voltage reference circuits. Compared to a conventional structure, it achieves a smaller area by using only two diodes. Also, it can fulfil sub 1V reference voltage by using temperature coefficient of threshold voltage to generate a current proportional to absolute temperature. This is because TC of this current on proposed circuit is bigger than that of conventional structure. Detailed analysis of the proposed bandgap reference is provided, which is simulated using 0.35μm CMOS process. The proposed bandgap reference occupies an active area of 0.0067mm2. The simulation results are the voltage reference output voltage of 0.843V and an accuracy of ±0.08%.

Temperature Sensor Front End in SOI CMOS Operating up to 250 <inline-formula> <tex-math notation="TeX">$^{\circ}\hbox{C}$</tex-math></inline-formula>

This brief presents a complementary-to-absolute-temperature voltage and a voltage reference based on the threshold voltage Vth extraction principle. The proposed Vth extraction circuit eliminates the nonlinear temperature-dependent mobility and mobility ratio terms, and it achieves a wide operating temperature range from -25 °C to 250 °C. The threshold-voltage temperature coefficient (TC) mismatch between nMOS and pMOS is compensated by selecting different channel lengths. Fabricated in the 1-μm partially depleted silicon-on-insulator CMOS process, the voltage reference achieves a box model TC of 27 parts per million (ppm) (mean) for an operating temperature range of -25 °C-250 °C and 18.7 ppm (mean) for a range of 25 °C-150 °C. Furthermore, the ratiometric output achieves mean temperature inaccuracy within ±1.8% over a temperature of 275 °C.

Temperature Coefficient of Threshold Voltage in High-k Metal Gate Transistors with Various TiN and Capping Layer Thicknesses

The temperature coefficient of Vth (=dVth/dT), which is commonly utilized for circuit design, was systematically obtained against various TiN and capping layer thicknesses in high-k/metal gate field-effect transistors (FETs). It is known that the magnitude of |dVth/dT| for such FETs is larger than that of polycrystalline silicon (poly-Si) gate FETs. The origins of the dVth/dT difference among high-k/metal gate FETs were attributed to differences in the temperature coefficient of flat band voltage (=dVFB/dT) and the equivalent gate oxide thickness (EOT). Thicker TiN layers reduced dVFB/dT, which enlarged the magnitude of |dVth/dT|. The EOT increased as the TiN metal layer or Al2O3 capping layer increased in thickness. The large EOT led to an increase in |dVth/dT|, since dVth/dT is a function of the inverse of gate capacitance. In contrast, La2O3 capping hardly affected dVth/dT. This is because La2O3 capping did not affect EOT differently from Al2O3 capping. The relationship between dVth/dT and EOT implies that EOT scaling relieves the issue of large |dVth/dT| for high-k/metal gate FETs.

Understanding Linear-Mode Robustness in Low-Voltage Trench Power MOSFETs

The high-temperature electrothermal stability and linear-mode robustness of low-voltage discrete power trench MOSFETs are assessed. The linear-mode robustness is shown to be dependent on the positive temperature coefficient of the subthreshold diffusion current and the MOSFET gain factor. The datasheet threshold voltage temperature coefficient ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GSTX</sub> TC) of a power MOSFET is important because it correlates with the linear-mode robustness and the zero-temperature-coefficient (ZTC) point of the device. The impact of the MOSFET active area and the cell pitch on the <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GSTX</sub> TC is experimentally assessed on fabricated devices. It is shown that the magnitude of the <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GSTX</sub> TC increases as the MOSFET active area increases, whereas it reduces as the cell pitch increases. The drain voltage at the onset of thermal runaway is shown to increase as the <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GSTX</sub> TC reduces for the same active area, thereby making the <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GSTX</sub> TC an indicator of linear-mode robustness. Although the gate voltage at the ZTC point and the magnitude of the <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GSTX</sub> TC increase with the MOSFET active area, the reduced thermal resistance improves the linear-mode robustness. The implication is that improved device performance in terms of lower specific on-state resistance ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SPEC</sub> in ohm-square millimeter) is at the expense of linear-mode robustness of the power MOSFET since lower <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SPEC</sub> devices have higher gain factors and higher currents are delivered at weaker inversion levels (and therefore contain higher proportions of subthreshold diffusion currents). In designing power MOSFETs, these parameters must be taken into consideration so as to minimize high-temperature instability and improve linear-mode robustness.

Normally-off trench JFET technology in 4H silicon carbide

A double gate normally-off silicon carbide (SiC) trench junction field effect transistors (JFET) design is considered. Innovative migration enhanced embedded epitaxial (ME 3) growth process was developed to replace the implantation process and realize high device performance. Strong anisotropic behavior in electrical characteristics of the pn junction fabricated on (1 1 −2 0) and (1 −1 0 0) trench a-planes was observed, although quality of the pn diodes was found to be independent of trench plane orientations. Fabricated normally-off trench 4H-SiC JFET demonstrates the potential for lower specific on-resistance ( R onS) in the range of 5–10 mΩ cm 2 (1200 V class). A relative high T −2.6 dependence of R onS is observed. A breakdown voltage of 400 V in the avalanche mode was confirmed at zero gate bias conditions for cell design without edge termination. It was demonstrated that the normally-off JFETs are suitable for high temperature applications. Average temperature coefficient of threshold voltage ( V th) was calculated as −1.8 mV/°C, which is close to the MOS based Si power devices.

Achieving accuracy in modeling the temperature coefficient of threshold voltage in MOS transistors with uniform and horizontally nonuniform channel doping

A thorough investigation on the threshold voltage temperature coefficient (TVTC) in MOS transistors is carried out. The TVTC behavior is analyzed in both conventional MOSFETs with uniformly-doped channel (UDC) and double-diffused devices (DMOS). First, a survey of analytical TVTC models proposed in literature for UDC MOSFETs is presented. Due to the need of simple TVTC expressions also for power devices, the listed UDC models are extended to the DMOS case via the straightforward “maximum doping” approach, which is commonly believed to correctly describe the turn-on mechanism in nonuniformly doped channels (NUDC). The accuracy degree of all TVTC expressions and the adequacy of the above method are—for the first time—deeply analyzed through ATLAS 2-D simulations of both DMOS and ideal UDC structures. As a main result, the “maximum doping” approach is demonstrated too coarse for suitably modeling the underlying DMOS physics. Nevertheless, it is shown that the TVTC in DMOSTs characterized by proper technological parameters is described with reasonable agreement by the Klaassen–Hes UDC model. Conversely, more compact formulations are proved to suffer from an unacceptable inaccuracy regardless of the MOS typology.

Analysis of the threshold voltage and its temperature dependence in electrolyte-insulator-semiconductor field-effect transistors (EISFET's)

A first-order theoretical model is developed that allows the temperature dependence of the threshold voltage of an electrolyte-insulator-semiconductor field-effect transistor (EISFET) to be determined. Specifically, a detailed analysis is presented for a representative cell consisting of a Ag/AgCI reference electrode, a simple 1:1 electrolyte, and an ISFET. In addition, an insulator is assumed for which the site-binding model is applicable. All temperature-dependent parameters are identified and quantitatively described. Results are computed for SiO 2 and Al 2 O 3 insulators over a pH range from 1 to 12, and a temperature range from 20 to 80°C. Graphs of the surface-site occupancies versus the pH are shown to provide useful physical insight in interpreting the results. The threshold-voltage temperature coefficient is shown to be highly dependent on the pH; however, for Al 2 O 3 , over a 20-80°C range, the variation is roughly linear.

On the temperature coefficient of the MOSFET threshold voltage

The temperature coefficient of the threshold voltage of the most common types of MOSFET devices has been measured and analyzed in terms of the underlying device physics. Owing to differences in gate contact potential and anomalies of the substrate backbias effect, the above coefficient has a typical value for each type. In particular for a compensated device, such as a CMOS p-channel MOSFET, the value of the temperature coefficient is relatively large (up to 3 mV/degree).

Improved Temperature Coefficient of Threshold Voltage in Twisted Nematic Liquid Crystals

Abstract This work is concerned with reducing temperature dependence of the threshold voltage of the TN nematic liquid crystals which consist of majority of n-type base mixtures and minority of p-type additives. The temperature coefficient of threshold voltage is closely related to the effective component of permanent dipole moment per molecules of p-type additives and becomes smaller with increasing it. The temperature coefficient is independent of the concentration of p-type additives. The mixture, whose temperature coefficient is 0.16%/ ° C or -3mV/° C, is developed for seven to-one multiplexing scheme over the temperature range 0 ∼ 40° C without any temperature compensation circuit.

A survey equipment using low-voltage halogen-quenched Geiger-Müller counters

The paper describes a small portable equipment for use by the private prospector in the location and approximate assay of radioactive ores. Its features are cheapness in cost and maintenance, simplicity of operation, long battery-life (2000 hours), robustness, lightness of weight (6 lb) and smallness of size (8⅞ in × 8 in × 3½ in). A pair of headphones and a meter are supplied as indicators; one quarter of full-scale deflection of the meter denotes the presence of bed rock containing 0.03% uranium oxide, U3O8 (0.003r/h for γ-rays from radium), and full-scale deflection denotes that of 1% uranium oxide, U3O8 (0.018r/h).Cold-cathode valves are used in the instrument, one acting as a constant-amplitude oscillator feeding a miniature Cockroft-Walton voltage-quadrupler producing a stabilized voltage output. The moulded plastic container is completely weatherproof.The Geiger-Muller counter tubes use bromine as the quenching agent, have thresholds of about 300–330 volts, and have very long lives. The range of temperature over which they will operate is from −50° C to +40° C, the temperature coefficient of threshold voltage being less than 0.2 volt/°C. Plateaux are 100 volts in length, with slopes from 0.03–0.1 %/volt. The counters may be operated at ±800 volts without damage. Their efficiency is not appreciably different from that of standard tubes.