Threshold Voltage Sensitivity Research Articles

Investigation of Backgate-Bias Dependence of Threshold-Voltage Sensitivity to Process and Temperature Variations for Ultra-Thin-Body Hetero-Channel MOSFETs

This paper investigates the impact of backgate bias (Vbg) on the sensitivity of threshold voltage (Vth) to process and temperature variations for ultra-thin-body (UTB) GeOI and InGaAs-OI MOSFETs. Our study indicates that the quantum-confinement effect significantly suppresses the Vbg dependence of the Vth sensitivity to process and temperature variations. Since Si, Ge, and InGaAs channels exhibit different degrees of quantum confinement, the impact of quantum confinement has to be considered when one-to-one comparisons among hetero-channel UTB devices regarding variability are made. Our study is crucial to the robustness of multi- Vth designs with advanced UTB technologies.

Comparative Simulation Analysis of Process-Induced Variability in Nanoscale SOI and Bulk Trigate FinFETs

This paper presents a comprehensive simulation study of the process and statistical variability in 16-nm technology node bulk and silicon-on-insulator (SOI) fin field effect transistors (FinFETs). The devices are carefully designed to offer good manufacturability while meeting the performance requirements of the 16-nm technology. First, the sensitivity of the two types of FinFETs to process- induced channel length, fin-width, and fin-height variability is carefully investigated and compared based on the threshold voltage, OFF-current, and overdrive current sensitivity. Possible improvement of the SOI substrate design for reduction of the SOI FinFET sensitivity to fin-width variation is also discussed. The individual and combined impact of the relevant statistical variability sources including random discrete dopants (RDDs), fin-line edge roughness, gate-line edge roughness, and metal gate granularity are studied and compared for the nominal 25-nm gate length FinFET designs.

Green's function approach for modeling of electrostatic effects in nanoscale fully depleted double-gate silicon-on-insulator metal-oxide-semiconductor field-effect transistors

Exact solution of two-dimensional (2D) Poisson's equation for fully depleted double-gate silicon-on-insulator metal-oxide-semiconductor field-effect transistor is derived using three-zone Green's function solution technique. Framework consists of consideration of source–drain junction curvature. 2D potential profile obtained forms the basis for estimation of threshold voltage. Temperature dependence of front surface potential distribution, back surface potential distribution and front-gate threshold voltage are modeled using temperature sensitive parameters. Applying newly developed model, surface potential and threshold voltage sensitivities to gate oxide thickness have been comprehensively investigated. Device simulation is performed using ATLAS 2D (SILVACO, 4701 Patrick Henry Drive, Bldg. Santa Clara, CA 95054 USA) device simulator, and the results obtained are compared with the proposed 2D model. The model results are found to be in good agreement with the simulated data. Copyright © 2013 John Wiley & Sons, Ltd.

Sensitivity of on-resistance and threshold voltage to buffer-related deep level defects in AlGaN/GaN high electron mobility transistors

The influence of deep levels defects located in highly resistive GaN:C buffers on the on-resistance (RON) and threshold voltage (Vth) of AlGaN/GaN high electron mobility transistors (HEMTs) power devices was studied by a combined photocapacitance deep level optical spectroscopy (C-DLOS) and photoconductance deep level optical spectroscopy (G-DLOS) methodology as a function of electrical stress. Two carbon-related deep levels at 1.8 and 2.85 eV below the conduction band energy minimum were identified from C-DLOS measurements under the gate electrode. It was found that buffer-related defects under the gate shifted Vth positively by approximately 10%, corresponding to a net areal density of occupied defects of 8 × 1012 cm−2. The effect of on-state drain stress and off-state gate stress on buffer deep level occupancy and RON was also investigated via G-DLOS. It was found that the same carbon-related deep levels observed under the gate were also active in the access region. Off-state gate stress produced significantly more trapping and degradation of RON (∼140%) compared to on-state drain stress (∼75%). Greater sensitivity of RON to gate stress was explained by a more sharply peaked lateral distribution of occupied deep levels between the gate and drain compared to drain stress. The overall greater sensitivity of RON compared to Vth to buffer defects suggests that electron trapping is significantly greater in the access region compared to under the gate, likely due to the larger electric fields in the latter region.

Threshold Voltage Sensitivity to Metal Gate Work-Function Based Performance Evaluation of Double-Gate n-FinFET Structures for LSTP Technology

This paper investigates the threshold voltage sensitivity to metal gate work-function for n-channel double gate fin field-effect transistor (FinFET) structures and evaluates the short channel performance of the device using threshold voltage dependence on metal gate work-function analysis. We carried out the study for a double gate n-channel fin field-effect transistor (n-FinFET) with parameters as per the projection report of International Technology Roadmap for Semiconductors, ITRS-2011 for low standby power (LSTP) 20 nm gate length technology node. In the present study device simulation have been carried out using PADRE simulator from MuGFET, which is based on the drift-diffusion theory. Our results show the accuracy and validity of classical drift-diffusion simulation results for transistor structures with lateral dimensions 10nm and above. The subthreshold behavior of device improves with increased metal gate work-function. The results also show that a higher gate work-function (≥5 eV) can fulfill the tolerable off-current as projected in ITRS 2011 report. The SCE in FinFET can reasonably be controlled and improved by proper adjustment of the metal gate work-function. DIBL is reduced with the increase in gate work function.

Sensitivity of Threshold Voltage to Nanowire Width Variation in Junctionless Transistors

We experimentally investigate the sensitivity of threshold voltage (T) to the variation of silicon nanowire (SiNW) width (Wsi) in gate-all-around junctionless transistors by comparison with inversion-mode transistors with the same geometric parameters. Due to the nature of junctionless transistors with a heavily doped SiNW channel, the VT fluctuation caused by the Wsi variation of junctionless transistors is significantly larger than that of inversion-mode transistors with a nearly intrinsic channel. This is because, in junctionless transistors, the channel doping concentration cannot be reduced in order to keep their inherent advantages. Therefore, our findings indicate that careful optimization or methods to mitigate the VT fluctuation related to the Wsi variation should be considered in junctionless transistors.

An analytical study of undoped symmetric double gate MOSFET (SDG)

AbstractIn the present paper, compact analytical models for the threshold voltage, threshold voltage roll‐off and subthreshold swing of undoped symmetrical double‐gate MOSFET have been developed based on analytical solution of two‐dimensional Poisson's equation for potential distribution. The developed models include drain‐induced barrier lowering (DIBL) through the Vds‐dependent parameter. The calculated threshold voltage value, obtained from the proposed model, shows a good agreement with the experimental and published results. The simulation results for potential show that the conduction is highly confined to the surfaces. The threshold voltage sensitivity to the thickness is found to be approximately 0.2%. Model prediction indicates that subthreshold slope is not linearly related to DIBL parameter for thick silicon film. The proposed analytical models not only provide useful insight into behavior of symmetrical DG MOSFETs but also serve as the basis for compact modeling. Copyright © 2010 John Wiley & Sons, Ltd.

Experimental determination of wave function spread in Si inversion layers

We have experimentally determined the extent of wave function spread TQM in Si inversion layers on (100)-oriented surface in metal-oxide-semiconductor field-effect transistors (MOSFETs) using the back gate bias sensitivity of front gate threshold voltage of planar fully depleted silicon-on-insulator (SOI) MOSFETs. We show that the sum of TQM for large positive and negative F is an electrically determined value of the SOI thickness TSI. We find that the electric field dependence of TQM for electrons and holes is given by TQM∼F−0.4 and F−0.6, respectively, at high electric fields with TQM being larger for holes at a given F. Larger TQM for holes can be explained by the fact that holes have a smaller effective mass along the confinement direction than electrons in (100) Si. The field dependences of TQM are, however, not consistent with the results of variational calculations that assume single-subband occupancy and predict TQM∼F−1/3. The discrepancy likely indicates that the effects of multiple-subband occup...

Leakage–Delay Tradeoff in FinFET Logic Circuits: A Comparative Analysis With Bulk Technology

In this paper, we study the advantages offered by multi-gate fin FETs (FinFETs) over traditional bulk MOSFETs when low standby power circuit techniques are implemented. More precisely, we simulated various vehicle circuits, ranging from ring oscillators to mirror full adders, to investigate the effectiveness of back biasing and transistor-stacking in both FinFETs and bulk MOSFETs. The opportunity to separate the gates of FinFETs and to operate them independently has been systematically analyzed; mixed connected- and independent-gate circuits have also been evaluated. The study spans over the device, the layout, and the circuit level of abstraction and appropriate figures of merit are introduced to quantify the potential advantage of different schemes. Our results show that, thanks to a larger threshold voltage sensitivity to back biasing, the FinFET technology is able to offer a more favorable compromise between standby power consumption and dynamic performance and is well suited for implementing fast and energy-efficient adaptive back-biasing strategies.

Device-Optimization Technique for Robust and Low-Power FinFET SRAM Design in NanoScale Era

In this paper, we propose a methodology to model and optimize FinFET devices for robust and low-power SRAMs. We propose to optimize the gate sidewall offset spacer thickness to simultaneously minimize leakage current and drain capacitance to on-current ratio in FinFET. With the source/drain extension doping controlled at the outer edges of the spacer, the thickness of the spacer determines the channel length. Optimization reduces the sensitivity of the device threshold voltage to the fluctuations in silicon thickness (by 32%) and gate length (by 73%). Our analysis shows that optimization of spacer thickness results in 65% reduction in SRAM cell leakage and improves cell read-failure probability (by 200 X) compared to conventional FinFET SRAM. Access time of an SRAM cell designed with optimized devices is comparable to conventional SRAM. We also compared the optimized-spacer-thickness SRAM cell with one designed using longer gate length and minimum-spacer-thickness transistors. The long-channel-device-based SRAM cell is marginally robust than optimized SRAM; however, increased gate-edge direct-tunneling leakage and parasitic capacitances degrade the power consumption and access time.

Analytical Model of the Threshold Voltage and Subthreshold Swing of Undoped Cylindrical Gate-All-Around-Based MOSFETs

Analytical physically based models for the threshold voltage, subthreshold swing, and drain-induced barrier lowering (DIBL) of undoped cylindrical gate-all-around MOSFETs have been derived based on an analytical solution of 2-D Poisson's equation (in cylindrical coordinates) in which the mobile charge term has been included. Using the new model, threshold voltage, DIBL and subthreshold swing sensitivities to channel length, and channel thickness have been investigated. The models for DIBL, subthreshold swing, and threshold voltage rolloff parameters have been verified by comparison with 3-D numerical simulations; close agreement with the numerical simulations has been observed

Simulation Study of High-Performance Modified Saddle MOSFET for Sub-50-nm DRAM Cell Transistors

A novel modified saddle MOSFET to be applied to sub-50-nm DRAM technology with high performance and easy scalability is proposed, and its characteristics at a given recess open width of 40 nm is studied by device simulation. The proposed device has ~ 21% lower gate capacitance and lower Ioff by two orders of magnitude than a conventional saddle device under nearly the same Ion. In addition, the proposed device showed less threshold voltage sensitivity to the corner shape and lower gate delay time (CV/I) by ~ 30% than the conventional recess channel device while keeping nearly the same Ioff

High-temperature and self-heating effects in fully depleted SOI MOSFETs

In this paper, the high-temperature and self-heating effects in the fully depleted enhancement lightly doped SOI n-MOSFETs are investigated over a wide range of temperatures from 300 to 600°K by using the SILVACO11All product names are trademarks of SILVACO International, 4701 Patrick Henry Drive, Santa Clara, CA, USA. TCAD tools. In particular, we have studied their current–voltage characteristics (ID–VGS and ID–VDS), threshold voltages and propagation delays. Simulation results show that there exists a biasing point where the drain current and the transconductance are temperature independent. Such a point is known as the zero temperature coefficient (ZTC) bias point. The drain current ZTC bias points are identified in both the linear and saturation regions whereas the transconductance ZTC bias point exists only in the saturation region. We have observed that decreasing the film thickness could reduce the threshold voltage sensitivity of the SOI MOSFET with temperature and that the drain current decreases with increasing temperature. We have also noted that due to the self-heating effects, the drain current decreases with increasing drain bias exhibiting a negative conductance and that the self-heating effects reduced at a higher operating temperature. Self-heating effects are more pronounced for higher gate biases and thinner silicon films whereas the bulk device shows negligible self-heating effects.

Threshold voltage sensitivity to doping density in extremely scaled MOSFETs

The dependence of the threshold voltage (VT) on channel doping for extremely scaled devices is investigated. This work is focused on the fundamental VT issue and its physical insight into the impact of the doping density on device characteristics. We find that the threshold voltage is, in fact, insensitive to doping over a wide range of doping density and such insensitivity is further extended by bandgap narrowing in nanoscale MOSFETs via analytical analyses and two-dimensional numerical device simulations (2003 Taurus-MEDICI User Guide (Mountain View, CA: Synopsis Inc.)). This result particularly suggests the scalability and feasibility of nanoscale double-gate MOSFETs.

Calibration of a pH sensitive buried channel silicon-on-insulator MOSFET for sensor applications

The threshold voltage characteristics of a buried channel silicon-on-insulator MOSFET is examined in solutions of varying acidity. Experiments utilizing an integrated micro-fluidic channel exhibit a variation in threshold voltage that appears approximately linear with pH in the range from pH 4 to pH 7, with a sensitivity of ∼1 V per pH unit. Charge configuration changes in the vicinity of the MOSFET inversion layer due to protonation/deprotonation of the device surface is proposed as an explanation for the observed shifts in threshold voltage. When the pH range is expanded we observe a non-linear relationship bet- ween pH and the threshold voltage of the device, this behavior is explained in terms of deprotonation of the different species of the native oxide surface, Numerical simulations of the MOSFET demonstrate that the threshold voltage sensitivity corresponds to an additional surface positive fixed charge density of ∼ 1 × 1010 cm–2 for each pH unit. (© 2004 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

Quantum mechanical effects on random oxide thickness and random doping induced fluctuations in ultrasmall semiconductor devices

Quantum mechanical effects on fluctuations in ultrasmall semiconductor devices are studied. Quantum mechanical effects are included in the analysis by using the density gradient model, for which the main parameters (effective masses) are identified through the two-dimensional Schrödinger equation. A very fast technique for the computation of threshold voltage fluctuations induced by random oxide thickness and doping variations is proposed. This technique is based on linearization of the transport equations with respect to the fluctuating quantities. This technique is computationally very efficient because it avoids numerous simulations for various doping and oxide realizations (as in the case of Monte Carlo techniques). At the same time, it provides information about the sensitivity of threshold voltage to the fluctuations of oxide thicknesses and doping at different locations. Sample simulation results are reported and compared with those previously published and good agreement is observed.

Sensitivity of double-gate and finfet devices to process variations

We investigate the manufacturability of 20-nm double-gate and FinFET devices in integrated circuits by projecting process tolerances. Two important factors affecting the sensitivity of device electrical parameters to physical variations were quantitatively considered. The quantum effect was computed using the density gradient method and the sensitivity of threshold voltage to random dopant fluctuation was studied by Monte Carlo simulation. Our results show the 3/spl sigma/ value of V/sub T/ variation caused by discrete impurity fluctuation can be greater than 100%. Thus, engineering the work function of gate materials and maintaining a nearly intrinsic channel is more desirable. Based on a design with an intrinsic channel and ideal gate work function, we analyzed the sensitivity of device electrical parameters to several important physical fluctuations such as the variations in gate length, body thickness, and gate dielectric thickness. We found that quantum effects have great impact on the performance of devices. As a result, the device electrical behavior is sensitive to small variations of body thickness. The effect dominates over the effects produced by other physical fluctuations. To achieve a relative variation of electrical parameters comparable to present practice in industry, we face a challenge of fin width control (less than /spl sim/1 nm 3/spl sigma/ value of variation) for the 20-nm FinFET devices. The constraint of the gate length variation is about 10/spl sim/15%. We estimate a tolerance of 1/spl sim/2 /spl Aring/ 3/spl sigma/ value of oxide thickness variation and up to 30% front-back oxide thickness mismatch.

A physical short-channel threshold voltage model for undoped symmetric double-gate MOSFETs

A compact, physical, short-channel threshold voltage model for undoped symmetric double-gate MOSFETs has been derived based on an analytical solution of the two-dimensional (2-D) Poisson equation with the mobile charge term included. The new model is verified by published numerical simulations with close agreement. Applying the newly developed model, threshold voltage sensitivities to channel length, channel thickness, and gate oxide thickness have been comprehensively investigated. For practical device designs the channel length causes 30-50% more threshold voltage variation than does the channel thickness for the same process tolerance, while the gate oxide thickness causes the least, relatively insignificant threshold voltage variation. Model predictions indicate that individual DG MOSFETs with good turn-off behavior are feasible at 10 nm scale; however, practical exploitation of these devices toward gigascale integrated systems requires development of novel technologies for significant improvement in process control.

Back gate effects on threshold voltage sensitivity to SOI thickness in fully-depleted SOI MOSFETs

The dependence of threshold voltage on silicon-on-insulator (SOI) thickness is studied on fully-depleted SOI MOSFETs, and, for this purpose, back-gate oxide thickness and back gate voltage are varied. When the back gate oxide is thinner than the critical thickness dependent on the back gate voltage, the threshold voltage has a minimum in cases where the SOI film thickness is decreased, because of capacitive coupling between the SOI layer and the back gate. This fact suggests that threshold voltage fluctuations due to SOI thickness variations are reduced by controlling the back gate voltage and thinning the back gate oxide.

An ultra-thin midgap gate FDSOI MOSFET

This work describes an ultra-thin fully depleted silicon-on-insulator (FDSOI) MOS transistor design, which uses a midgap workfunction metal gate and lightly doped channel to set the threshold voltages ( V th) of both nMOSFETs and pMOSFETs symmetrically at 0.3 V for ultra-low voltage applications. In contrast to conventional FDSOI devices, the threshold voltage sensitivity for this FDSOI device displays excellent immunity to variations in SOI film thickness and channel doping density. We find a 1% variation for a 25% variation in SOI film thickness centered at 10 nm or a 50% channel doping variation centered at 1×10 15 cm −3. Such a device is very suitable for ultra-low voltage applications.