Threshold Voltage Of nMOSFETs Research Articles

Influence of electron beam irradiation induced charging-effect on nanoprobing localization of a crystal defect in MOSFET

The paper demonstrates that the electron beam (e-beam) irradiation induced charging-effect has remarkable impact on nanoprobing localization of a crystal defect hidden in metal-oxide-semiconductor field-effect transistor (MOSFET). We present a practical example showing that device characterization at the contact layer (CT) is susceptible to the charging-effect since scanning electron microscopy (SEM) based nanoprobe system running is inevitablely acompanied by e-beam irradiation towards device under test (DUT). The mechanisms is seldomly reported in the past. In our case, the p-n junction at a nMOSFET drain end showed the ohmic current-voltage (I-V) characteristic at the beginning. However, by utilizing the atomic force microscopy (AFM) based nanoprobe system without e-beam, the measurement found previous resistive characteristic of the p-n junctions disappeared. Instead, it exhibited good rectifying characteristic. I-V characteristic discrepancy coming from two analytical methods was attributed to the charging-effect influence. It was experimentally proven that the charging-effect impact at MOSFET gate CT had strong dependance on the e-beam irradiation magnitude corresponding to the SEM scan speed. Charging effect produced distinct consequences at distinct scan speeds. The positive charging-effect occurred under the fast scan while the negative charging-effect occurred under the slow scan. The former mechanism made the potential at gate CT high enough to turn on nMOSFET. Therefore, the nMOSFET channel current merged with the p-n junction current in a closed-loop. In contrast, the slow scan induced negative charging-effect made the gate potential lower than the nMOSFET threshold voltage (VT), so that the nMOSFET stayed off-state. Consequently, the p-n junction resumed its intrinsic rectifying I-V characteristic. Different from the nMOSFET, the charging-effect affected the pMOSFET in the opposite manner. As a result, the initial conclusion of the MOSFET junction leakage was not valid. Next, we ran a optimal flow to narrow down a fault by eliminating the charging-effect impact. Eventually, a crystal defect (pipeline) was isolated in a suspcted nMOSFET relying on nanoprobe and TEM analysis. The article explains the evident influence of charging-effect on the nanoprobe analysis and puts forward an effective way to minimize the side effect of the e-beam irradiation. The work may draw more attention to the analytical methodologies regarding MOSFET reliability improvement.

Back gate impact on SEU characterization of a Double SOI 4k-bit SRAM

In this paper, heavy-ion single-event effects studies are investigated on a 0.2 μm Double silicon-on-insulator (DSOI) 4k bit Static Random Access Memory (SRAM). The back gate bias is used to adjust the single event upset (SEU) rate of the SRAM circuit. Experimental results show that applying a -5 V bias to the back gate of nMOSFETs can reduce the SEU cross section by 31 % ~ 62 %, and the SEU rate by 61 %. While applying to the back gate of both nMOSFETs and pMOSFETs a 5 V bias can increase the SEU cross section by 43 % ~ 298 %, and the SEU rate by 3 orders of magnitude. The SEU rate is calculated using OMERE software under the GEO orbit with a 3 mm aluminum shielding condition. To further analyze the cause of this phenomenon, TCAD simulation and DSOI MOSFETs test were introduced in this paper. Results show that applying a negative bias to the back gate of nMOSFETs will reduce the single particle transient (SET) and increase the threshold voltage of nMOSFETs, which makes the SRAM cell more tolerant to SEU; while applying a positive bias to the back gate of pMOSFETs will decrease the drive current of pMOSFETs, which makes the SRAM cell more sensitive to SEU.

Interfacial Properties of nMOSFETs With Different Al2O3 Capping Layer Thickness and TiN Gate Stacks

In this article, the interfacial properties of nMOSFETs with different thickness high- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\kappa $ </tex-math></inline-formula> Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> capping layer on an 8-nm SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> and TiN gate stacks have been investigated using electrical measurement and low-frequency noise at room temperature. It is shown that the predominant 1/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${f}$ </tex-math></inline-formula> noise is governed by the number fluctuations mechanism. It is indicated that: 1) presence of an Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> capping layer increases the noise power spectral density and, hence, the oxide trap density has an influence on the low-field mobility further and 2) effective work-function and the threshold voltage of nMOSFET should be modulated using the high- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\kappa $ </tex-math></inline-formula> Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> capping layers.

Impact of Quantum Confinement on Stress-Induced nMOSFET Threshold Voltage Shift

In this paper, we propose a comprehensive model to express nMOSFET threshold voltage shift induced by stress, ranging from a high tensile one to a high compressive one. Using this model, the quantum confinement effect, combined with large out-of-plane stress, is shown to play an important role to cause the threshold voltage shift as large as about 80 mV induced by high-film-stress contact etch-stop layer.

Threshold voltage model of strained Si channel nMOSFET

The model of nMOSFET threshold voltage was established based on study of voltage distribution in strained Si film,which was grown on relaxed SiGe virtual substrate.The model was analyzed with reasonable parameters, and the dependence of threshold voltage on Ge fraction and channel doping was revealed. The dependence of threshold voltage shift on Ge fraction was also obtained. The relationship between threshold voltage and strained Si layer thickness and doping was studied. The results indicates, the threshold voltage increases with increasing doping concentrations of relaxed SiGe layer, decreases with increasing Ge fraction of relaxed SiGe layer, and increases with increasing strained Si layer thickness. This threshold voltage model provides valuable reference to the strained-Si device design.

Development of A 4H-SiC CMOS Inverter

AbstractIn this paper we report the first 4H-SiC CMOS inverter, which was designed to be integrated in the process flow of a 4H-SiC power DMOSFET. The channels of both of the n channel and p-channel MOSFETs of the inverter were 50 um wide by 3 um long. NMOSFET threshold voltage (VTH) ranged from 4.4 V at 25°C to 2.2 V at 250°C and PMOSFET VTH ranged from -4.75 V at 25°C to just under -4 V at 300°C. The transfer threshold voltage (Vm) of the 4H-SiC CMOS inverter was in a very tight range of 2.8 V to 2.9 V over the entire temperature range of 25°C to 300°C when using a drive voltage (VDD) of 10 V.

Electrical reliability of highly reliable 256M-bit mobile DRAM with top-edge round STI and dual gate oxide

A novel CMOS fabrication process with a dual gate oxide (NDGO, thin oxide 5.0 nm, thick oxide 7.8 nm) and a shallow trench isolation (STI) top-edge rounded by a pad oxide undercut was developed for a 256M-bit mobile dynamic random access memory (DRAM) with V D=1.8 V. We present a comprehensive study on the I– V characteristics and the long-term reliability of CMOSFET fabricated by NDGO process, and compared these characteristics with those of conventional single gate oxide transistors with a gate oxide thickness 5.0–7.5 nm. While thin oxide nMOSFET have a threshold voltage of nMOSFET ( V thn) of between 0.70 and 0.72 V and a saturation current ( I DSAT) of between 280 and 300 μA/μm, thick oxide nMOSFET have a V thn of between 0.85 and 0.90 V and an I DSAT of between 160 and 200 μA/μm in NDGO process due to a difference in the gate oxide thickness at similar boron doses. A 10 year lifetime of thick oxide cell transistors is projected for a V g=8.9 V due to an electrical stress release at the STI top-edge round improved by the pad oxide undercut. The hot carrier lifetime and hot electron induced punchthrough also showed good characteristics. Consequently, this NDGO process is able to provide a reliable transistor performance for a 256M-bit mobile DRAM operating at low power.

The temperature-dependence of threshold voltage of N-MOSFETs with nonuniform substrate doping

In this work, the temperature effect on threshold voltage of a MOSFET with nonuniformly doped substrate is discussed. The concept of threshold surface potential is adopted so as to take the freeze out effect into consideration and to calculate the threshold voltage as a function of temperature. A new method of extracting the threshold voltage from experimental data, based on the definition of threshold surface potential, is also proposed. The extracted values fit well with the calculated threshold voltages in the temperature range of 80 to 300 K.

Preventing boron penetration through 25-/spl Aring/ gate oxides with nitrogen implant in the Si substrates

For gate oxides thinner than 40 /spl Aring/, conventional schemes of incorporating N in the oxides might become insufficient in stopping B penetration. By implanting N into the Si substrates with a sacrificial oxide layer; we have grown 25 /spl Aring/ gate oxide and prevented B penetration in the presence of F after 90 min of 850/spl deg/C and 10 s of 1050/spl deg/C anneals. SIMS analyses surprisingly reveal a N peak formed within the thin oxide layer, while no N is left in the Si substrate beyond the oxide layer. In addition, no B is seen in the substrate, either. As a consequence, threshold voltage of pMOSFETs is shifted to a more negative value which agrees with calculations assuming no B penetration. Meanwhile, threshold voltage of nMOSFETs is not affected by the N implant, which confirms that B penetration is the only explanation for the pMOSFET data. Prevention of B penetration also improves the short-channel effects for 0.25-/spl mu/m pMOSFETs, while no difference is seen in nMOSFETs with and without N implant.

Effects of Compositional Segregation and Short Channel on Threshold Voltage of nMOSFET

ABSTRACTThis study calculates the threshold voltage (VT) roll-off behavior caused by short channel effect (SCE) as a result of scaling and the reverse short-channel effect (RSCE) due to B segregation around source and drain junctions by using the 2D device simulator - SILVACO™-ATLAS. The simulation results are comparable with the experimental data. It suggests that the drift diffusion physics can predict SCE and RSCE very well to sub-0.25μ Si n-MOSFET devices. The modeling results indicate the VT roll off at shorter channel length for devices with higher substrate doping concentration. VT increases if the local p-dopant segregation exists around the source and drain junction. It is observed that RSCE is more significant for devices with lower substrate doping concentration and shorter channel length.

Supply voltage design tradeoffs between speed and NMOSFET reliability of half-micrometer BiCMOS gates

Voltage supply scaling for a BiCMOS gate was investigated experimentally and analytically. For half-micrometer technology, the supply voltage design tradeoffs between propagation delay and NMOSFET reliability were studied. It was found that the minimum BiCMOS operating voltage ranges from 2.5 to 3.0 V. This minimum can be explained by the sum of twice the base-emitter potential and the NMOSFET threshold voltage, due to the emitter grounded Bi-MOS structure of the BiCMOS gate. As a result, 3.3-V operation is inherently marginal for BiCMOS gates. On the other hand, NMOS reliability in the BiCMOS gate is drastically improved because effective drain voltage is reduced by the base-emitter potential. Thus, NMOSFETs with a channel length shorter by more than 0.2 mu m can be used, and this ensures reliable operation of BiCMOS gates at 5 V. In terms of the tradeoffs between gate speed and NMOS reliability, it is verified that BiCMOS gates offer the highest speed in half-micrometer design. >

Propagation Delay Measurements from a Timing Sampler Intended for Use in Space

This paper describes a 3-μm CMOS timing sampler which is a test circuit designied inito the JPL CRRES chip to be flown on the Coombined Release and Radiation Effects Satellite (CRRES). The timing sampler consists of 64 inverter-pair stages with sampling latches anid decoder circuitry. The sampler is used to measure inverter-pair propagation delays, which are nominally 2.5 nanoseconds, with a resolutioni of 100 picoseconds. A simple model was developed to explain the radiation-induced inverter-pair delay shifts in terms of radiation-induced MOSFET-threshold voltage shifts and effective nodal capacitances. The magnitude of the shift in pair delay with radiation was estimated at the point where the n-MOSFET threshold voltage became zero. For a 0.7-volt threshold shift, the pairdelay increased from its preradiation value by 360 picoseconds for a rising step iniput and decreased by 190 picoseconds for a falling step input.