Threshold Voltage Of Device Research Articles

2-GHz 2×VDD 28-nm CMOS Digital Output Buffer with Slew Rate Auto-Adjustment Against Process and Voltage Variations

A 2[Formula: see text]VDD CMOS output buffer with process, voltage and leakage (PVL) detection mechanism is proposed such that slew rate is auto-adjusted to reduce the variations at different corners. To boost the driving current, low threshold voltage transistors are used instead of devices with typical threshold voltage in the driving transistor of output stage. More importantly, to prevent large leakage of those large low threshold voltage devices, leakage detection resistors are added at the gates of the always-on low threshold voltage transistors to clamp the leakage. The static power consumption is reduced when it is not activated. Another feature of the proposed design is that the gate-oxide leakage is also reduced by lengthening the driving transistors. Besides, all biases in the proposed design are generated from bandgap circuits such that not only is the variation caused by temperature drifting reduced, the area overhead and power dissipation are also minimized. The proposed design is carried out by using 28-nm CMOS process. The data rate proved by physical measurement is proved to be 2.0[Formula: see text]GHz given 1.8/1.05[Formula: see text]V supply voltage, namely, VDD or 2[Formula: see text]VDD, when the proposed PVL detection as well as the compensation circuitry are activated.

Realizing a Planar 4H-SiC Junctionless FET for Sub-10-nm Regime Using P+ Pocket

In this paper, using calibrated device simulations, we propose the use of a P± pocket at channel-drain and channel-source interfaces in 4H-SiC junctionless FET (4H-SiC p-JLFET) to achieve efficient volume depletion in the sub-10-nm regime; thus relaxing the need of channel thickness scaling or the use of complex device architectures. The P± pocket improves the OFF-state current (IOFF) by ~ 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">9</sup> , while slightly degrading the ON-state current (ION) and subthreshold slope (SS) for a 7-nm channel length device. This large gain in IOFF presents the possibility of realizing multiple threshold voltage (VTH) devices by tuning the metal-gate work function, which helps in creating optimized designs in terms of area, power, leakage, and performance, which is not possible in Si JLFETs, due to their need of high metal-gate work functions to achieve volume depletion even at larger channel lengths. The 4H-SiC p-JLFET gives ~1pA/μm IOFF even at an elevated temperature of 600 K. We also discuss the scaling of the SiC p-JLFETs for 7-and 5-nm channel length.

Stress-Induced Performance Shifts in 3D DRAMs

3D-stacked DRAMs can significantly increase cell density and bandwidth while also lowering power consumption. However, 3D structures experience significant thermomechanical stress due to the differential rate of contraction of the constituent materials, which have different coefficients of thermal expansion. This impacts circuit performance. This article develops a procedure that performs a performance analysis of 3D DRAMs, capturing the impact of both layout-aware stress and layout-independent stress on parameters such as latency, leakage power, refresh power, area, and bus delay. The approach first proposes a semianalytical stress analysis method for the entire 3D DRAM structure, capturing the stress induced by through-silicon-vias (TSVs), micro bumps, package bumps, and warpage. Next, this stress is translated to variations in device mobility and threshold voltage, after which analytical models for latency, leakage power, and refresh power are derived. Finally, a complete analysis of performance variations is performed for various 3D DRAM layout configurations to assess the impact of layout-dependent stress. We explore the use of alternative flexible package substrate options to mitigate the performance impact of stress. Specifically, we explore the use of an alternative bendable package substrate made of polyimide to reduce warpage-induced stress, and show that it reduces stress-induced variations and improves the performance metrics for stacked 3D DRAMs.

Small dose effect in RADFET with thick gate oxide

In order to track “small dose effect” leading to stabilization of RADFETs with 1 μm thick oxide fabricated at Tyndall National Institute, Cork, Ireland irradiation was performed with gamma-rays in the radiation dose interval from 1 to 5 cGy, followed with room temperature annealing for the time of 28 days. Gate bias during irradiation was 0, 2.5 and 5 V. Threshold voltage shift ΔVT determined from transfer characteristics in saturation were followed during irradiation and annealing. It was shown that there is significant increase in ΔVT for 1 cGy radiation dose and those are 36.3, 43.3 mV and 45.7 mV for gate bias 0, 2.5 V and 5 V, respectively. For higher radiation doses ΔVT also increases, however, such increase is much lower. RADFETs fading at room temperature lead to permanent decrease in ΔVT and after 28 days the threshold voltage for devices is returned to virgin device value. Small dose effect is confirmed and radiation dose of at least 5 cGy is necessary for RADFET stabilization before their use in dosimetric application. After RADFETs stabilization they were irradiated in dose interval from 10 to 50 cGy with gate bias of 0, 2.5 and 5 V. It was shown that there is a linear dependence between ΔVT and absorbed radiation dose D, for gate bias during irradiation 0, 2.5 and 5 V. Defects responsible for threshold voltage shift, formed during irradiation as well as their neutralization/compensation during annealing, are also discussed.

Stress-Induced Variability Studies in Tri-Gate FinFETs with Source/Drain Stressor at 7 nm Technology Nodes

The epitaxially grown SiGe source/drain stressor (e-SiGe) technique has emerged to be a consistent performance booster for advanced devices below the 14 nm technology node. At nanoscale, the omnipresent residual stress is now becoming an important source of variability in advanced VLSI technologies that influence the circuit performance. Also, in deeply-scaled technologies, process and environment variations become other sources of variabilities. In this paper, we study the stress-induced variability in aggressively scaled (at 7 N) Si-channel FinFETs with epitaxially grown SiGe stressors in the source and drain regions. The stress distribution analysis is performed with the help of Technology CAD mechanical stress simulations. At first, we calibrate our simulation results with available experimental data. We generate the stress maps in FinFETs with various scaled dimensions of fin length, height and width. The effects of residual strain/stress on variability due to metal gate granularity (MGG) and random discrete dopant (RDD) in strain-engineered FinFETs (with 50 configurations) have been investigated. Furthermore, the device threshold voltage variation due to RDD and MGG are critically examined. Finally, we calculate the mean and standard deviation of these parameters (QQ plots) to quantify the variability.

On-Chip Threshold Voltage Variability Estimation Using Reconfigurable Ring Oscillator

Process variability is one of the major concerns in semiconductor manufacturing in advanced technology nodes. This paper explains an all-digital technique to estimate the impact of threshold voltage ( ${V}_{\text{th}}$ ) of NMOS device under test (NDUT) using a reconfigurable ring oscillator (RRO) which consists of a chain of threshold voltage measurement cell (TVMC). The difference of periods of RRO due to two voltage levels, i.e., ${V}_{\text {dd}}$ and ( ${V}_{\text {dd}}-{V}_{\text {th}}$ ) at the intermediate node provides information about the impact of threshold voltage of an NDUT. A lognormal model is developed to extract the threshold voltage information from the RRO period difference. The maximum difference in predicting the threshold voltage from the proposed model and through SPICE simulation is found to be less than 1.5%. Measured results from 26 test chips in 130-nm process show the feasibility of estimating the $ {V}_{\text {th}}$ variability from the proposed RRO test structure. The proposed test circuit with 300 samples of NDUT occupies a silicon area of ${280} \,\, {\times }\,\, {64}\,\, {\mu } \text {m}^{{2}}$ .

Floating Bulk Cascode Class-E Power Amplifier

In this brief, the switching behavior of the cascode topology is improved through the floating bulk (FB) technique. Although the cascode structure has the advantage of reducing voltage stress on transistors, its parasitic elements increase power loss. The FB technique has been proposed to alleviate the power loss in the cascode class-E PA topology which results in enhancement of power added efficiency (PAE). In this method, the bulk of the common-gate (CG) transistor is connected to the ground through a resistor. As a result, the parasitic capacitances between the drain and source of the CG transistor create a new path of current that accelerates charging of parasitic capacitance at the drain of the common-source (CS) transistor. This new current path speeds up on-to-off transition of the CG transistor. In addition, the threshold voltage of the CG device is increased during on and off transitions which lowers the drain-source voltage of the CS device. Concurrently, these two phenomena minimize the power loss in both CS and CG transistors. To demonstrate the functionality of the FB technique, a cascode class-E PA is implemented in a 0.18- $\boldsymbol {\mu }\text{m}$ CMOS TSMC process at 1.8 GHz with 52% PAE and 27 dBm maximum output power.

Encapsulated Nano-Sized Liquid Crystal Droplet Display with a Single Substrate

We present a single-substrate display device characterized by nano-sized liquid crystal droplets that can be applied to various optical devices. The nano-emulsified liquid crystal droplets can be encapsulated, and their size can be controlled through the number of dispersions. We demonstrate the electro-optical characteristics of a single-substrate display device with capsulated liquid crystal droplets with a diameter of approximately 200–300 nm fabricated using the nano-emulsification process for display applications. The contrast ratio, threshold voltage, and response time of a single-substrate display device using nano-sized liquid crystal droplets are approximately 25:1, 12 V, and 46.26 ms, respectively.

Advances in La-Based High-k Dielectrics for MOS Applications

This paper reviews the studies on La-based high-k dielectrics for metal-oxide-semiconductor (MOS) applications in recent years. According to the analyses of the physical and chemical characteristics of La2O3, its hygroscopicity and defects (oxygen vacancies, oxygen interstitials, interface states, and grain boundary states) are the main problems for high-performance devices. Reports show that post-deposition treatments (high temperature, laser), nitrogen incorporation and doping by other high-k material are capable of solving these problems. On the other hand, doping La into other high-k oxides can effectively passivate their oxygen vacancies and improve the threshold voltages of relevant MOS devices, thus improving the device performance. Investigations on MOS devices including non-volatile memory, MOS field-effect transistor, thin-film transistor, and novel devices (FinFET and nanowire-based transistor) suggest that La-based high-k dielectrics have high potential to fulfill the high-performance requirements in future MOS applications.

Continuous Monitoring of pH and Blood Gases Using Ion-Sensitive and Gas-Sensitive Field Effect Transistors Operating in the Amperometric Mode in Presence of Drift.

Accurate and cost-effective integrated sensor systems for continuous monitoring of pH and blood gases continue to be in high demand. The capacity of ion-selective and Gas-sensitive field effect transistors (FETs) to serve as low-power sensors for accurate continuous monitoring of pH and blood gases is evaluated in the amperometric or current mode of operation. A stand-alone current-mode topology is employed in which a constant bias is applied to the gate with the drain current serving as the measuring signal. Compared with voltage-mode operation (e.g., in the feedback mode in ion-selective FETs), current-mode topologies offer the advantages of small size and low power consumption. However, the ion-selective FET (ISFET) and the Gas-sensitive FET (GasFET) exhibit a similar drift behavior, imposing a serious limitation on the accuracy of these sensors for continuous monitoring applications irrespective of the mode of operation. Given the slow temporal variation associated with the drift characteristics in both devices, a common post-processing technique that involves monitoring the variation of the drain current over short intervals of time can potentially allow extraction of the measuring signal in presence of drift in both sensor types. Furthermore, in the amperometric mode the static sensitivity of a FET-based sensor, given by the product of the FET transconductance and the sensitivity of the device threshold voltage to the measurand concentration, can be increased by adjusting the device design parameters. Increasing the sensitivity, while of interest in its own right, also enhances the accuracy of the proposed method. Rigorous analytical validation of the method is presented for GasFET operation in the amperometric mode. Moreover, the correction algorithm is verified experimentally using a Si3N4-gate ISFET operating in the amperometric mode to monitor pH variations ranging from 3.5 to 10.

Difference in Device Temperature Determination Using p-n-Junction Forward Voltage and Gate Threshold Voltage

Determination of chip temperature is a key element in the lifetime estimation of power devices. There are several temperature sensitive electrical parameters for this purpose, which allow accurate measuring of the chip temperature on fully packaged devices. Among all these parameters, the forward voltage of a p-n junction is probably the most widely used parameter for temperature determination of a power semiconductor device. In metal-oxide-semiconductor (MOS) gated power semiconductor devices, gate threshold voltage is an alternative parameter with high temperature resolution. In this paper, the p-n-junction forward voltage and the gate threshold voltage of MOS-gated power devices were investigated. The difference between temperature measurements via the two methods was analyzed.

Bonding of Large Substrates by Silver Sintering and Characterization of the Interface Thermal Resistance

Low-temperature silver sintering technology, which has been proven to be a promising die-attach solution, was extended to bonding large substrates. Strong bonding strengths for substrates with a dimension of greater than 25 mm × 50 mm were achieved by sintering a nanosilver paste at temperatures below 270 °C under a pressure of less than 5 MPa. To characterize the thermal performance of the substrate-attach interface, we applied a transient thermal technique with cumulative structure function analysis. Using self-heating and the temperature-sensitive threshold voltage of a power device, we measured the transient thermal responses of the device placed at various locations on the bonded structures. Each transient thermal response was used to determine the cumulative structure function, which represents the relationship between cumulative thermal capacitance and cumulative thermal resistance from the device junction to the ambient environment. Two-dimensional maps corresponding to interface thermal resistance were obtained from structure function plots. We found that for well-bonded substrates, the average specific thermal resistance contributed by the sintered silver interface was between 5.20 and 5.78 mm2K/W with a variation of 4.7%–6.0%.

Thermal response for intermodulation distortion components of GaN HEMT for low and high frequency applications

Thermal effect on intermodulation distortion (IMD) behavior of GaN based high-electron mobility transistor (HEMT) have been researched over input power and frequency using a two-tone technique. A significant modification was observed in terms of magnitude on the linear component and the magnitude as well as the position and appearance of the nulls/notches of the nonlinear components was changed conspicuously. The parasitic resistances and as well as the output current were affected when applied input power increases. As a result, an increase in the output IMDs found and the device threshold voltage VT moves towards more negative of Vgs trace which in turn shifts the notch points of the nonlinear IMDs towards lower values of applied bias Vgs. The values of the output IMDs degrades with the increment of temperature and frequency. The output IMD products also reduced following the transconductances response to temperature. On the other hand, the notch/null's position of the nonlinear IMDs also moves following the thermal response of threshold voltage. This authentic and exhaustive study is crucial to figure out the minimum distortion, maximum gain bias option for active devices.

A threshold voltage definition for modeling asymmetric dual-gate amorphous InGaZnO thin-film transistors with parameter extraction technique

A physical definition of threshold voltage has been proposed for asymmetric dual-gate amorphous InGaZnO (a-IGZO) thin-film transistors. Based on the definition, a compact model for drain current has been derived with complete parameter extraction methods. According to the distribution characteristics of density of states (DOS) in the a-IGZO bandgap, the threshold voltage of bottom-gate (BG)-driven devices is defined by the ratio of the trapped-carrier density to the free-carrier density at the bottom surface of the channel layer. This definition has proven to give appropriate values of threshold voltage for devices with DOS parameters varying in a wide range. The trapped-charge density in the above-threshold region can be expressed based on the defined threshold voltage, with the form related to the BG voltage, the top-gate voltage, and the potential along the channel. The free-charge density and analytical drain current can thus be obtained in the above-threshold region. Finally, the continuous drain current expression is developed covering all operation regions. In the modeling process, the determination and extraction strategies for parameters are also presented.

Effect of HCl cleaning on InSb–Al2O3 MOS capacitors

In this work, the role of HCl treatments on InSb surfaces and InSb–Al2O3 dielectric interfaces is characterised. X-ray photoelectron spectroscopy measurements indicate that HCl diluted in and rinsed with isopropanol (IPA) results in a surface layer of InCl3 which is not present for similar HCl-water processes. Furthermore, this InCl3 layer desorbs from the surface between 200 °C and 250 °C. Metal–oxide–semiconductor capacitors were fabricated using atomic layer deposition of Al2O3 at 200 °C and 250 °C and the presence of InCl3 was associated with a +0.79 V flatband voltage shift. The desorption of the InCl3 layer at 250 °C reversed this shift but the increased process temperature resulted in increased interface-trapped charge (D it) and hysteresis voltage (V H ). This shift in flatband voltage, which does not affect other figures of merit, offers a promising route to manipulate the threshold voltage of MOS transistors, allowing enhancement-mode and depletion-mode devices to be fabricated in parallel.

Seamless Fabrication and Threshold Engineering in Monolayer MoS2 Dual‐Gated Transistors via Hydrogen Silsesquioxane

AbstractFrom its inception, extensive work on the characterization of field effect transistors (FETs) based on 2D‐layered semiconductors has relied on a back‐gated transistor architecture. This is useful for initial assessment but lacks ultimate compatibility with integrated circuit (IC) design since the threshold voltage of individual devices cannot be controlled independently in order to achieve specific ON‐state and OFF‐state performance. Note that threshold engineering via gate electrostatics is inevitable for 2D semiconductors owing to the absence of comprehensive, reliable, and universal doping schemes. In recent years, several strategies are adopted for the gating of individual 2D‐FETs such as atomic layer deposition (ALD) of high‐k dielectrics, drop casting of ionic liquids, and deterministic transfer of insulating 2D hexagonal boron nitride. These techniques have their respective strengths and weaknesses. A facile, low‐temperature, scalable, and universally applicable fabrication scheme for dual‐gated monolayer 2D‐FETs is reported here, which is compatible with the back‐end‐of‐the‐line (BEOL) process flow of complementary metal oxide semiconductor (CMOS) technology, using hydrogen silsesquioxane (HSQ). HSQ is a negative tone resist that possesses dielectric properties similar to SiO2 when exposed to high electron beam irradiation and thermal curing and can produce features as small as 10 nm.

A low power RFID based energy harvesting temperature resilient CMOS-only reference voltage

In this work a low power consumption reference voltage in commercial 40 nm technology is proposed. It adopts a new approach to produce a temperature invariant reference voltage for outdoor RFID applications. To do so, the positive temperature coefficient (TC) of the produced output voltage of a Dickson charge pump is used to cancel out the negative temperature coefficient of the threshold voltage (Vth) of CMOS devices. The result is, according to the post-layout Cadence simulation, a 1.224 V reference voltage with a TC of 60 ppm°C−1 in the temperature range of −10 °C to 125 °C. The circuit consumes 7 nW with an active area of 0.00033 mm2.

Optimization of short channel effect and external resistance on small size FinFET for different threshold voltage flavors and supply voltages

In this paper, ideal Technology Computer Aided Design (TCAD) simulation is carried out for small size FinFET transistors. The definition of device critical dimensions is close to the 4th generation FinFET. The source/drain (s/d) extension doping is defined with certain gradient from epitaxy grown s/d, which is found to have dominant effect on the transistor electrostatic as well as the external resistance (Rext) between channel and s/d contact. The simulation is carried out for different threshold voltage (Vth) devices, which are, ultra-low Vth (ULVT), low Vth (LVT) and standard Vth (SVT), as well as different transistor supply voltages (Vdd). The extension doping gradient (sipgrdnt) is varied with the Rext and the sub-threshold swing (SSsat) with high drain voltage (Vd) monitored, which is a key indicator of gate electrostatic control on channel. All the comparison is performed at a given leakage current pre-defined for three Vth type devices by adjusting the metal gate work-function (WF). It is found that the Rext and SSsat are two competing factors for effective drive current (Ieff). Also, the SSsat for peak Ieff decreases with higher Vth flavor and lower operation Vdd and could be viewed as a guideline for FinFET optimization at this scaling regime.

Strong interfacial coupling effects of ferroelectric polarization with two-dimensional electron gas in BaTiO3/MgO/AlGaN/GaN/Si heterostructures

Strong interfacial coupling between ferroelectric polarization and 2DEG is demonstrated in BTO/MgO/AlGaN/GaN/Si with a large threshold voltage for E-mode HEMT devices.

Circuit Performance Shifts Due to Layout-Dependent Stress in Planar and 3D-ICs

This paper presents an approach for analyzing stress in 2-D and 3-D integrated circuits (ICs) due to postmanufacturing thermal mismatch. For both 2D-ICs and 3D-ICs, shallow trench isolation (STI) induces thermal residual stress in active silicon. For 3D-ICs, through-silicon vias (TSVs) act as an additional source of stress. Together, the sources of stress cause changes in the delay and power of the circuit. We develop an analytical model based on inclusion theory in micromechanics to accurately estimate the stresses and strains induced in the active region by surrounding STI in a layout. The TSV-induced stress depends on the location of the transistor with respect to the TSVs. Therefore, these stresses result in placement-dependent variations in the transistor mobilities and threshold voltages of the active devices, and we propagate these effects to circuit-level performance. At the transistor level, the stress state is translated into mobility and threshold voltage variations using piezoresistivity and band deformation potential models, respectively. At the gate level, the computed changes in transistor electrical parameters are used to predict gate-level delay and leakage power changes for single-fingered and multifingered layout styles, which are subsequently used to predict circuit-level delay and leakage power for a given placement.