Measured Threshold Voltage Research Articles

As-grown-Generation Model for Positive Bias Temperature Instability

Positive bias temperature instability (PBTI) is poised to cause significant degradation to nFETs with deep scaling into nanometers. It is commonly modeled by a power law fitted with measured threshold voltage shift. For the first time, this paper shows that such models do not warrant PBTI prediction outside the stress conditions used for the fitting. The underlying cause for this failure is the errors in the extracted power exponent. Based on the understanding of different types of defects, we develop a robust as-grown-generation model and demonstrate its capability for accurate prediction of PBTI under both dc and ac conditions. The generation-induced degradation is found to play a key role. Analysis reveals that although PBTI is usually smaller than negative BTI (NBTI) within the typical test time window, it can exceed NBTI by the end of device lifetime.

Interfacial dynamic surface traps of lead sulfide (PbS) nanocrystals: test-platform for interfacial charge carrier traps at the organic/inorganic functional interface

Nanocrystal (NC) size and ligand dependent dynamic trap formation of lead sulfide (PbS) NCs in contact with an organic semiconductor were investigated using a pentacene/PbS field effect transistor (FET). We used a bilayer pentacene/PbS FET to extract information of the surface traps of PbS NCs at the pentacene/PbS interface through the field effect-induced charge carrier density measurement in the threshold and subthreshold regions. PbS size and ligand dependent trap properties were elucidated by the time domain and threshold voltage measurements in which threshold voltage shift occurs by carrier charging and discharging in the trap states of PbS NCs. The observed threshold voltage shift is interpreted in context of electron trapping through dynamic trap formation associated with PbS NCs. To the best of our knowledge, this is the first demonstration of the presence of interfacial dynamic trap density of PbS NC in contact with an organic semiconductor (pentacene). We found that the dynamic trap density of the PbS NC is size dependent and the carrier residence time in the specific trap sites is more sensitive to NC size variation than to NC ligand exchange. The probing method presented in the study offers a means to investigate the interfacial surface traps at the organic-inorganic hetero-junction, otherwise understanding of the buried surface traps at the functional interface would be elusive.

A Fast $V_{th}$ Measurement (FVM) Technique for NBTI Behavior Characterization

In this letter, a novel fast threshold voltage ( ${V}_{th}$ ) measurement (FVM) technique is proposed and demonstrated, which could perform ${I}$ – ${V}$ characterization of MOSFETs within 1 ns. With the advanced FVM technique, down to 1-ns negative biased temperature instability (NBTI) characterization was successfully carried out for Si pFinFETs at 14-nm technology node. It is experimentally confirmed that the nano-second-level fast recoverable traps, which are generated during NBTI stress, could lead to the underestimation of ${V}_{th}$ degradation under micro-second-level measurement speed. Furthermore, it is found that even when the ${V}_{th}$ measurement is performed within 1 ns after the stress removal, it is still not fast enough to be the real recovery-free measurement. Yet, with the proposed FVM technique, NBTI characteristics could be characterized more accurately and closer to its intrinsic behaviors.

Stable organic thin-film transistors.

Organic thin-film transistors (OTFTs) can be fabricated at moderate temperatures and through cost-effective solution-based processes on a wide range of low-cost flexible and deformable substrates. Although the charge mobility of state-of-the-art OTFTs is superior to that of amorphous silicon and approaches that of amorphous oxide thin-film transistors (TFTs), their operational stability generally remains inferior and a point of concern for their commercial deployment. We report on an exhaustive characterization of OTFTs with an ultrathin bilayer gate dielectric comprising the amorphous fluoropolymer CYTOP and an Al2O3:HfO2 nanolaminate. Threshold voltage shifts measured at room temperature over time periods up to 5.9 × 105 s do not vary monotonically and remain below 0.2 V in microcrystalline OTFTs (μc-OTFTs) with field-effect carrier mobility values up to 1.6 cm2 V-1 s-1. Modeling of these shifts as a function of time with a double stretched-exponential (DSE) function suggests that two compensating aging mechanisms are at play and responsible for this high stability. The measured threshold voltage shifts at temperatures up to 75°C represent at least a one-order-of-magnitude improvement in the operational stability over previous reports, bringing OTFT technologies to a performance level comparable to that reported in the scientific literature for other commercial TFTs technologies.

The formation of a functional pentacene/CH3NH3PbI3−xClx perovskite interface: optical gating and field-induced charge retention

We fabricated a functional pentacene/CH3NH3PbI3-xClx perovskite interface where optical gating and field assisted charge retention occur. Using a pentacene/perovskite field effect transistor (FET) test platform, we investigated the interfacial charge transfer associated with optical gating through threshold voltage measurements under illumination. Importantly, bistable electrical conduction in pentacene/perovskite FET devices was achieved as a result of field-induced charge retention at the interface and the origin is discussed to be associated with interfacial charging at the pentacene/perovskite interface. Interfacial contact modification associated with ion migration and other possible effects in the perovskite layer plays a crucial role in forming a functional interface involving organic semiconducting materials.

Effect of trapped charge in AlGaN/GaN and AlGaN/InGaN/GaN heterostructure by temperature dependent threshold voltage analysis

The effect of trap energy states in AlGaN/InGaN/GaN heterostructure is investigated by temperature dependent threshold voltage measurement from 298 K to 373 K. It is found that the threshold voltage of AlGaN/InGaN/GaN structure decreases from - 6.52 V to - 6.90 V with temperature increase from 298 K to 348 K. But for the temperature higher than 348 K, the threshold voltage starts to increase and reaches to - 6.75 V at 373 K. However, the threshold voltage for AlGaN/GaN structure decreases consistently from −5.32 V to −6.4 V for entire range of temperature. The decrease of threshold voltage is attributed to the surface donor trap charges for both the heterostructures. Furthermore, the acceptor trap charges might have contributed for temperature above 348 K, and hence the increase of threshold voltage is observed in AlGaN/InGaN/GaN heterostructure. Higher crystal defects, resulted from lower growth temperature, might be responsible for the formation of these acceptor trap levels in InGaN layer.

Work Function Extraction of Indium Tin Oxide Used as Transparent Gate Electrode for MOSFET

Recent commercialization has increased the research interest in transparent conducting oxides like Indium Tin Oxide (ITO) being implemented in display technologies and sensors. RF sputtered ITO is used as a transparent gate electrode to fabricate n-MOSFET. For the fabrication of the MOSFET, a four-level mask is used. Electrical characterization is performed on these MOSFETs. Work function (Wf) of ITO is extracted from the threshold voltage measurements of the MOSFET devices. A new method of extracting work function of ITO from n-MOSFET device is introduced in this study.

Analysis of photoluminescence, UV absorbance, optical band gap and threshold voltage of TiO2 nanoparticles dispersed in high birefringence nematic liquid crystal towards its application in display and photovoltaic devices

In the present work anatase TiO2 nanoparticles (NPs) have been dispersed into the pure nematic liquid crystal (NLC) 2020 which is consisted of fluorinated 4'-alkylphenyl-4-isothiocyanatotolanes, in different concentration. The dispersion of TiO2 NPs in NLC induces photoluminescence what is an important finding of this study. It has also been found that the dispersion of TiO2 NPs reduces the UV absorbance of pure NLC. Optical band gap has been calculated and found to be decreased for the dispersed system as compared to pure NLC. The presence of TiO2 NPs affects the molecular dynamics of the NLC molecules, which has been proved by the Fourier transformed infrared spectroscopy (FTIR). Relative electric permittivity and dielectric anisotropy have been found to be decreased for the dispersed system as compared to the pure NLC. The trapping capability of TiO2 NPs is also confirmed by the independent measurement of threshold voltage. The value of threshold voltage has decreased after dispersion of NPs in the pure NLC. This decrement is due to the property of TiO2 NPs to reduce the ionic contribution, thereby, increasing the net field of the system. The induction of photoluminescence in a non photoluminescent material with the help of TiO2 nanoparticle along with reduced band gap are the main findings of the present work. It is suggested that the output of the present work may be very useful in various display and photonic applications as well as in photovoltaic devices.

Carrier scattering in high-κ/metal gate stacks

A significant degradation of the mobility has been repeatedly observed at low inversion density in high-κ/metal gate metal-oxide-semiconductor field-effect transistors. However, the scattering mechanisms responsible for this degradation are still debated. It is often assumed that the mobility is limited by remote charges (RCS) at the interface between SiO2 and HfO2. However, the amount of charges needed to reproduce the experimental mobilities is usually very high (a few 1013 cm−2), and does not seem to be consistent with the measured threshold voltages. Scattering by localized dipoles hardly solves these discrepancies. Here, we investigate the contribution from three alternative mechanisms in a non-equilibrium Green's functions framework: (i) scattering by band offset fluctuations at the SiO2/HfO2 interface, (ii) scattering by dielectric constant fluctuations in SiO2 and HfO2, and (iii) scattering by workfunction fluctuations in a granular metal gate. None of these mechanisms significantly shifts the threshold voltage. We show that mechanisms (i) and (iii) efficiently scatter the carriers at low inversion densities. This reduces the amount of RCS charges needed to reproduce the experimental data. RCS and these mechanisms show different dependences on the thickness of the HfO2 layer, which might help to identify the dominant contributions.

Role of deposition and annealing of the top gate dielectric in a-IGZO TFT-based dual-gate ion-sensitive field-effect transistors

The deposition of the top gate dielectric in thin film transistor (TFT)-based dual-gate ion-sensitive field-effect transistors (DG ISFETs) is critical, and expected not to affect the bottom gate TFT characteristics, while providing a higher pH sensitive surface and efficient capacitive coupling between the gates. Amorphous Ta2O5, in addition to having good sensing properties, possesses a high dielectric constant of ∼25 making it well suited as the top gate dielectric in a DG ISFET by providing higher capacitive coupling (ratio of Ctop/Cbottom) leading to higher amplification. To avoid damage of the a-IGZO channel reported to be caused by plasma exposure, deposition of Ta2O5 by e-beam evaporation followed by annealing was investigated in this work to obtain sensitivity over the Nernst limit. The deteriorated bottom gate TFT characteristics, indicated by an increase in the channel conductance, confirmed that plasma exposure is not the sole contributor to the changes. Oxygen vacancies at the Ta2O5/a-IGZO interface, which emerged during processing, increased the channel conductivity, became filled by optimum annealing in oxygen at 400 °C for 1 h, which was confirmed by an x-ray photoelectron spectroscopy depth profiling analysis. The obtained pH sensitivity of the TFT-based DG ISFET was 402 mV pH−1, which is about 6.8 times the Nernst limit (59 mV pH−1). The concept of capacitive coupling was also demonstrated by simulating an a-IGZO-based DG TFT structure. Here, the exposure of the top gate dielectric to the electrolyte without applying any top gate bias led to changes in the measured threshold voltage of the bottom gate TFT, and this obviated the requirement of a reference electrode needed in conventional ISFETs and other reported DG ISFETs. These devices, with high sensitivities and requiring low volumes (∼2 μl) of analyte solution, could be potential candidates for utilization as chemical sensors and biosensors.

Junction temperature measurement of alternating current light-emitting-diode by threshold voltage method

Junction temperature of alternating current light-emitting-diode (AC-LED) has a significant effect on its stable light output and lifetime. The threshold voltage measurement is employed to characterize the junction temperature of AC-LED, due to its excellent merits in high efficiency and accuracy. The threshold voltage is measured when the driving current of an AC-LED rises to a reference on-set value from the zero-crossing node. Based on multiple measurements of threshold voltage at different temperatures, a linear relationship was uncovered between the threshold voltage and the junction temperature of AC-LED with the correlating factor of temperature sensitive parameter (TSP). Thereby, we can calculate the junction temperature with the TSP and threshold voltage once the AC-LED stays at thermal equilibrium state. The accuracy of the proposed junction temperature measurement technique was found to be ±3.2°C for the reference current of 1 mA. It is concluded that the method of threshold voltage is accurate and simple to implement, making it highly suitable for measuring the junction temperature of AC-LED in industry.

(Invited) Reliability Study of RF Power Amplifiers with GaN-on-SiC HEMTs

In total 50 RF amplifier demonstrators consisting each of a PCB board containing one GaN-on-SiC, HEMT, CHZ015A-QEG, from UMS in SMD quad-flat no-leads package (QFN) were assembled for the study. Two types of solders, one of which is lead-free, (Sn63Pb36Ag2 and SAC305) and two types of TIM materials (NanoTIM and TgonTM805) for PCB attachment to liquid cold plate were tested for thermo-mechanical reliability. Out of the total number of the demonstrators 24 were subjected to thermal stress by 2300 thermal cycles (TC) between -20°C and 80°C and remaining 26 were subjected to the electrical stress by power cycling (PC) with drain current of 100 mA at drain voltage of 45 V and cycle time of 2 min. HF characterization of all the boards was done before subjecting them to the thermal and electrical stresses. All the devices were also subjected to static electrical characterization by measuring threshold voltage and output and voltage blocking characteristics. The static electrical and HF characterization was performed again after 2300 cycles of TC stress and after 1100, 4700 and 14500 cycles of PC stress. In addition failure analysis was performed on the TC and PC stressed demonstrators by using optical microscopy and 2D X-ray microscopy. The results of electrical and HF characterization show clearly changes and degradation in device performance as a function of the number of the PC cycles and accumulated current stress time. No significant differences between the boards equipped with different solder or TIM materials are observed which means that the observed changes in performance are due to the degradation of the HEMT devices. A reduction in value of saturation current (VDS=10 V, VGS=0.8 V) of about 5, 12 and 16 % is observed after 1100, 4700 and 14500 cycles of PC stress, respectively. There is a clear tendency of the threshold voltage shift (measured at 10 mA) towards more negative values showed by devices from different groups. The shift is by -0.1 to -0.15 V from typical value of about -2.25 V. The leakage current is less well behaved. There are devices with no significant change in leakage current but also devices which show an increase in leakage current by a factor larger than 2, as a result of the PC stress. Results of HF measurements show a decrease in S11 and S21 parameters from -10.91±0.23 to -10.0±0.21 and from 16.04±0.24 to 15.51±0.28 after PC stress (measurement conditions VDS=45 V, IDS=100 mA, power level 5 dBm, 1.3 GHz). The support of Sweden´s innovation agency, Vinnova, and Sweden Energy Authority is acknowledged. Figure 1

Investigation on the Charge Loss Mechanisms of Nanoscale Charge Trap Non-Volatile Memory by Using Stretched Exponential Function.

Charge loss mechanisms of nanoscale charge trap non-volatile memory devices are carefully examined and studied. Fowler-Nordheim tunnelling mechanism is used to perform rapid program/erase cycling. Based on the good fit of post cycled and baked threshold voltage data to Stretched Exponential function, the lowest point and the peak of Vt distribution were found to evolve in a similar manner that resulted to similar derived Ea. The saturation behaviour of the threshold voltage decay can be predicted and validated through cells' threshold voltage measurements that fit well to Stretched Exponential function. The power law relationship of program/erase cycle count and the saturation behaviour was found to be similar on the device under study and NROM devices that utilizes significant different charge injection mechanisms for program/erase operation. The experimental results also demonstrated that charge injection mechanism is one of the dominant factors in determining the underlying charge loss mechanism. Moreover, the determination of charge loss mechanism depends on the total charges injected through the tunnel oxide layer of ONO stack in NB-CTNVM cell. Physical interpretation of the experimental findings of the dominant charge loss mechanism is deliberated in detail.

Monolayer field effect transistor as a probe of electronic defects in organic semiconducting layers at organic/inorganic hetero-junction interface

The origin of a large negative threshold voltage observed in monolayer (ML) field effect transistors (FETs) is explored using in-situ electrical measurements through confining the thickness of an active layer to the accumulation layer thickness. Using ML pentacene FETs combined with gated multiple-terminal devices and atomic force microscopy, the effect of electronic and structural evolution of a ML pentacene film on the threshold voltage in an FET, proportional to the density of deep traps, was probed, revealing that a large negative threshold voltage found in ML FETs results from the pentacene/SiO2 and pentacene/metal interfaces. More importantly, the origin of the threshold voltage difference between ML and thick FETs is addressed through a model in which the effective charge transport layer is transitioned from the pentacene layer interfacing with the SiO2 gate dielectric to the upper layers with pentacene thickness increasing evidenced by pentacene coverage dependent threshold voltage measurements.

A Study of Super Junction Trench Gate IGBT with Fully Self-Aligned Fabrication Technology

ABSTRACTThe main targets of this paper are decrease the on-resistance (power dissipation) and increase breakdown voltage of the super junction trench gate insulated gate bipolar transistor (SJ-TGIGBT) by designing new device structure combined with control and optimising the key fabrication technology parameters. We proposed a new trench gate IGBT with super junction structure in its n drift region, which exhibits a strongly improved relationship of device’s on-resistance with its blocking voltage. The on-resistance of SJ-TGIGBT is 1.25 power related to the thickness of its n drift region and linearly related to its breakdown voltage, which eliminated the 2.5 power of breakdown voltage relationship of on-resistance for conventional IGBT. An accurate control of impurity concentration of n drift region in the trench sidewall is important to achieve the performance of proposed SJ-TGIGBT, and tilted angle ion implantation is considered to be the most suitable method for the doped impurity fine controllability, so we optimized the trench sidewall doping by adjusting the ion implantation dosage and its implanted tilted angles. The proposed SJ-IGBTs are fabricated with designed silicides fully self-aligned technology using only four masks. The fabricated chips are measured with correct output I–V characteristics, the measured threshold voltage is 3.05–5.57 V, blocking voltage is 1130–1280 V. The measured results also confirmed that the reduction in on-resistance is about 12% compared with the conventional non-SJ IGBT, and more than 34% compared with the silicon limit of non-SJ metal-oxide-semiconductor (MOS) devices with a 1200 V voltage rating.

Design, Fabrication and Characterization of Low-Noise and High-Reliability Amorphous Silicon Gate Driver Circuit for Advanced FPD Applications

We report a novel design of amorphous silicon gate (ASG) driver circuit with not only low output noises but also improved reliability. The ASG circuits are made of thin-film transistors (TFTs) and integrated in the substrate glass. Unlike the most traditional ASG circuits, the proposed pull-down signals are complementary with lower frequency to discharge the critical nodes in the proposed circuit. The new pull-down signals are created to discharge each two adjacent stage circuits. By inputting two controlled pulse signals, the prospective pull-down signals can be created eventually in the circuit. To simulate the real driving conditions, a string of a resistance (1.24 ${\hbox{k}}\Omega$ ) and a capacitance (85.5 pF) are connected to each output as loading. By probing the output pads of the real circuit sample, the output characteristics can practicably be measured. In particular, the output ripples can be suppressed to 0.28 V. Moreover, the measured threshold voltage $({\rm V}_{\rm th})$ shift with two stressing signals at different frequencies reveals the significant difference. The measured ${\rm V}_{\rm th}$ shift after 12 h of the clock stressing with lower frequency (167 Hz) is about 12% slower speed than that of the stressing clock with higher frequency (16.7 kHz) under the high temperature (60 $^{\circ}\hbox{C}$ ).

Simulating the Influence of Mobile Ionic Oxide Charge on SiC MOS Bias-Temperature Instability Measurements

We report here on results obtained using a time-dependent drift-diffusion model to simulate ion transport in the gate oxide of a SiC MOS device during bias-temperature instability measurements to assess the impact on threshold voltage under typical testing conditions. Measured threshold voltage is found to depend strongly on the temperature and mobile ion species, which in combination with the measurement parameters determine how the ions react to the stress and measurement sequence. Simulations show that, based on their mobilities, both potassium-like and copper-like ions may be responsible for experimental observations of a negative trend in threshold instability above 100 °C for SiC MOS devices.

Modelling and characterization of NAND flash memory channels

The threshold voltage distribution after ideal programming in NAND flash memory cells is usually distorted by a combination of the random telegraph noise (RTN), cell-to-cell interference (CCI), and the retention process. To decide the original bits more accurately in this scenario, a precise channel model shall be utilized on the basis of the measured threshold voltages. This paper aims to characterize these various distortions occurring in multi-level cell (MLC) flash memories. A mathematical description of the overall distribution for the total flash channel distortion is presented. The final threshold voltage distribution for each symbol of MLC flash is also characterized, which is important for calculating the exact soft decisions of cell bits and the application of advanced flash error correction. The results of the theoretical analysis have been validated through Monte Carlo simulations of the flash channel.

Negative bias temperature instability threshold voltage shift turnaround in SiGe channel MOSFETs

Negative bias temperature instability (NBTI) has been measured at various temperatures in high-k gate insulator MOSFETs with buried Si0.65Ge0.35 channels and with regular Si surface channels. Previous studies on both surface channel Si devices and Si1−xGex buried channel devices provide evidence for net positive charge trapping as a function of electrical stressing time albeit reduced for the case of Si1−xGex compared to the Si case. In our case, for buried Si0.65Ge0.35, the authors find initial negative charge trapping followed by positive charge trapping at longer times, typically >10−1 s. The effect is accentuated at higher temperatures and yields a turnaround in the measured threshold voltage shift as a function of stress time. Closer examination of NBTI in high-k gate, Si surface devices stressed at room temperature and 90 °C suggests both electron and hole trapping may be present there although the majority effect is hole trapping.

In situ preparation, electrical and surface analytical characterization of pentacene thin film transistors.

The fabrication of organic thin film transistors with highly reproducible characteristics presents a very challenging task. We have prepared and analyzed model pentacene thin film transistors under ultra-high vacuum conditions, employing surface analytical tools and methods. Intentionally contaminating the gold contacts and SiO2 channel area with carbon through repeated adsorption, dissociation, and desorption of pentacene proved to be very advantageous in the creation of devices with stable and reproducible parameters. We mainly focused on the device properties, such as mobility and threshold voltage, as a function of film morphology and preparation temperature. At 300 K, pentacene displays Stranski-Krastanov growth, whereas at 200 K fine-grained, layer-like film growth takes place, which predominantly influences the threshold voltage. Temperature dependent mobility measurements demonstrate good agreement with the established multiple trapping and release model, which in turn indicates a predominant concentration of shallow traps in the crystal grains and at the oxide-semiconductor interface. Mobility and threshold voltage measurements as a function of coverage reveal that up to four full monolayers contribute to the overall charge transport. A significant influence on the effective mobility also stems from the access resistance at the gold contact-semiconductor interface, which is again strongly influenced by the temperature dependent, characteristic film growth mode.