Threshold Voltage Instability Research Articles

Characterization of Oxide Trapping in SiC MOSFETs Under Positive Gate Bias

SiC MOSFETs devices with double-trench dominate the market due to their low on-resistance. However, studies on its temperature-dependent properties are not comprehensive. This work uses fast I-V and static I-V techniques to explore the location of electrons trapped in the device under moderate gate stress. Threshold voltage instability (VTH hysteresis and ΔVTH) and on-resistance degradation (ΔRON) are used to characterize oxide trapping. Although the observation method is different, it can be found that the VTH instability and RON degradation increase linearly with logarithmic time over a wide time range from 100 μs to 104 s, suggesting that the direct tunneling mechanism dominates the electrons trapping in the oxide near the SiO2/SiC interface. The interface trap density is 3.8× 1012 cm.2EeV-1. In addition, a negative temperature dependence is shown in the test, and the fitting parameter γ from 0.16 to 0.18 indicated that these traps are concentrated in the oxide layer. These traps’ energy level at 0.68 eV below the conduction band was obtained in the recovery phase through the Arrhenius plot.

Hf-Based and Zr-Based Charge Trapping Layer Engineering for E-Mode GaN MIS-HEMT Using Ferroelectric Charge Trap Gate Stack

E-mode hybrid ferroelectric charge storage gate (FEG) GaN HEMTs have shown promising performances for future power GaN device applications. The FEG-HEMT demonstrates a combination of ferroelectric polarization and charge trapping process in the ferro-charge-storage gate stack, leading to a positive threshold voltage shift for E-mode operations. In this work, FEG-HEMTs with various Hf-based and Zr-based charge trapping layers are systematically studied. FEG-HEMT which employed nitrogen incorporated HfO2 (HfON) as the charge trapping layer shows an E-mode operation with the highest Vth (+2.3 V) after initialization. Moreover, the gate leakage of the HfON sample was further reduced due to the nitrogen incorporation, leading to a more complete charging process during initialization. The Vth instability is also addressed and investigated. The FEG-HEMT with HfON as the charge trapping layer showed a negligible Vth hysteresis (-43mV) and the highest Vth stability in both the PBTI (positive bias threshold voltage instability) and NBTI (negative bias threshold voltage instability) test measurements.

The Road to a Robust and Affordable SiC Power MOSFET Technology

This article provides a detailed study of performance and reliability issues and trade-offs in silicon carbide (SiC) power MOSFETs. The reliability issues such as threshold voltage variation across devices from the same vendor, instability of threshold voltage under positive and negative gate bias, long-term reliability of gate oxide, screening of devices with extrinsic defects by means of gate voltage, body diode degradation, and short circuit withstand time are investigated through testing of commercial devices from different vendors and two-dimensional simulations. Price roadmap and foundry models of SiC MOSFETs are discussed. Future development of mixed-mode CMOS circuits with high voltage lateral MOSFETs along with 4−6× higher power handling capability compared to silicon circuits has been described.

Identification of bulk and interface state-induced threshold voltage instability in metal/SiNx(insulator)/AlGaN/GaN high-electron-mobility transistors using deep-level transient spectroscopy

The physical mechanism of threshold voltage (VTH) instability in AlGaN/GaN metal-insulator-semiconductor high electron mobility transistors (MIS-HEMTs) was identified via capacitance-mode deep-level transient spectroscopy characterization. MIS-HEMTs with low-pressure chemical vapor deposited (LPCVD) SiNx as the gate insulator feature two distinctive trap-emission transients. The initial transient corresponds to emission of states at the SiNx/AlGaN interface, and the extracted density of state exhibits an exponential decay distribution. The subsequent transient is revealed due to hybrid emission of the interface and bulk states from the LPCVD-SiNx gate insulator, which features an activation energy higher than 1.1 eV and a capture cross section that ranges between 1 × 10−11 and 1 × 10−10 cm2. The bulk states in the LPCVD-SiNx gate insulator become charged under high gate voltage overdrive, leading to severe VTH instability in GaN-based MIS-HEMTs.

(Invited) BTI Reliability Issues for SiC MOSFETs

This work will provide an updated overview of our understanding of key reliability issues related to Bias Temperature Instability (BTI) for SiC power MOSFETs.BTI is also often referred to as threshold-voltage instability. This phenomenon likely occurs due to the charging and discharging of near-interfacial oxide traps in response to a change in gate bias. If enough traps change charge state, it can lead to significant shifts in the threshold voltage, which may in turn lead to increases in leakage current in the off state, or increases in on-state resistance in the on state.Key questions include what is the best way to characterize this instability, as well as its potential importance on performance and reliability during normal device operation. This work will address these and related questions, including potential degradation mechanisms based on new insights.

Impact of an AlGaN spike in the buffer in 0.15 μm AlGaN/GaN HEMTs during step stress

On-wafer robustness and short-term reliability of 0.15 μm AlGaN/GaN HEMTs, fabricated on AlGaN buffer with a ‘mono-layer’ and c backbarrier between channel and buffer layers, have been compared. Results of DC characterization showed that devices with AlGaN ‘bi-layer’ backbarrier have better subthreshold behaviour, reduced on-resistance and leakage current, together with a slightly lower current and transconductance. Electroluminescence measurements suggested an increase of electric field in the ‘bi-layer’ devices. Observed failure modes are the following: (a) during off-state stress, threshold voltage shifts towards more negative values; (b) for semi-on and on-state tests, a non-monotonic threshold voltage instability, which initially becomes negative and then recovers is common to both types of devices; (c) during semi-on and on-state tests, a significant increase of RON occurs, which seems to be faster in devices without spike, despite the lower electric field suggested by EL measurements. Degradation of electrical characteristics has been attributed to the instability of charge on Carbon-related acceptor levels, enhanced by hot-electron effects.

Investigation of the threshold voltage instability in normally-off p-GaN/AlGaN/GaN HEMTs by optical analysis

A normally-off p-GaN/AlGaN/GaN high-electron-mobility transistor (p-GaN HEMTs) with a semitransparent gate electrode was investigated. Under forward gate bias, electroluminescence (EL) emission was observed which demonstrated the hole injection in the gate heterostructure. The hole injection emerged at a gate bias of 3.5 V and was significantly enhanced when the gate bias was larger than 6 V, the corresponding EL emission intensity was increased by approximately 100 times. It was also found that the electron injection and trapping in the p-GaN resulted in the threshold voltage (V TH) instability of the p-GaN HEMTs, while the hole injection resulted in the electron–hole recombination and the suppression of electron trapping. The carrier injection dynamics in the p-GaN gate region were quantitatively identified at different temperatures. Finally, the GaN band-edge ultraviolet emission with an energy of 3.4 eV was demonstrated as the most effective component in EL emission for V TH instability suppression in the p-GaN HEMTs.

Gate-Induced Threshold Voltage Instabilities in p-Gate GaN HEMTs

In this study, we investigate the threshold voltage ( V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> th</sub> ) instability of p-gate GaN HEMTs induced by gate bias. Experimental results are acquired by a custom pulse setup for two commercially available devices with an ohmic gate and a Schottky gate. A transient drain current change is observed, which corresponds to a shift of V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> th</sub> . A negative V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> th</sub> instability is identified for the ohmic gate, a mostly positive for the Schottky gate that can also become negative depending on the gate bias voltage and duration. The impact of the gate-bias-induced V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> th</sub> instability on the Schottky-gate device is significantly higher compared to the ohmic-gate device, but clearly noticeable at the nominal rated ON-state gate voltage for both devices. Electron depletion and trapping as well as hole accumulation and trapping are identified to cause this transient V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> th</sub> instability.

Influence of the carrier behaviors in p-GaN gate on the threshold voltage instability in the normally off high electron mobility transistor

Threshold voltage (VTH) instability has been studied in the as-fabricated p-GaN gated enhancement-mode high electron mobility transistors (p-GaN E-HEMTs) under a positive gate stress. A negative VTH shift (ΔVTH) obtained by dynamic measurement has been observed more severely when compared to the static one. The VTH deviation is attributed to the complicated influence of carrier transport behaviors in the p-GaN gate. The impacts of hole accumulation, trapping, and consumption on the VTH instability and drain current variation can be effectively distinguished according to the transfer characteristics obtained from the pulse I–V measurement. Moreover, the density of hole traps in the p-GaN gate is estimated to be around ∼2 × 1011 cm−2 by the capacitance–voltage measurement, and the energy level is calculated to be around EV + 0.62 eV by fitting the recovery curve of gate current after positive gate bias. This study focusing on the in-depth influence of different carrier behaviors on the gate performance can help with the understanding and further improvement of the dynamic instability and reliability of the GaN-based HEMTs.

Characterization of Threshold Voltage Instability Under Off-State Drain Stress and Its Impact on p-GaN HEMT Performance

The p-GaN gate technology is commonly implemented to achieve normally OFF gallium nitride (GaN) devices. Nonetheless, the threshold voltage instability under OFF-state stress remains a concern. In this article, the characterization technique of threshold voltage shift is proposed and the V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> shift's impact on device performance is investigated. Specifically, a fast V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> the measurement circuit is introduced and validated to successfully characterize both the magnitude and the time-constant of the V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> shift. According to the experimental results, the V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> increases by more than 50% within several μs after the high drain voltage is applied. In contrast, the V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> slowly (tens of seconds) gets back to the static value after the stress is removed. Following the characterization, the threshold voltage instability's impact on the device's static/switching performance is studied experimentally. A knee point shift is observed at low gate voltage, and the static ON-resistance value remains unchanged. Regarding the switching performance, the turn-ON loss increases by >20% after the high drain voltage stress. The change in turn-ON loss can be reduced when the gate resistance is decreased from 20 to 0 Ω. In terms of the turn-OFF loss, the impact of the V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> shift is negligible. It is concluded that time-dependent threshold voltage shift needs to be considered in p-GaN device's modeling, and high gate drive voltage together with low gate resistance is recommended to mitigate the V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> instability's effect on p-GaN high-electron-mobility transistor's performance.

Negative Bias Instability of InZnO-Based Thin-Film Transistors Under Illumination Stress.

In this study, we investigated the threshold voltage (Vth) instability of solution-processed indium zinc oxide (IZO) thin film transistors (TFTs) prior to and after negative bias illumination stress (NBIS) with varying carrier suppressors (Ga, Al, Hf, and Zr). Variations in electrical properties of the IZO-based TFTs as a function of carrier suppressors were attributed to the differences in metal-oxygen bonding energy of the materials, which was numerically verified by calculating the relative oxygen deficient ratio from the X-ray photoelectron spectroscopy analysis. Furthermore, the values of Vth shift (ΔVth) of the devices subjected to negative gate bias stress under 635 nm (red), 530 nm (green), and 480 nm (blue) wavelength light irradiation increased as the incident photon energy increased. IZO TFTs doped with Ga atoms demonstrated weaker metal-oxygen bonding energy compared to the others and exhibited the largest ΔVth. This result was attributed to the suppressor-dependent distribution of neutral oxygen vacancies which determine the degrees of photon energy absorption in the IZO films. Then, the ΔVth instability of IZO-based TFTs under NBIS correlated well with a stretched exponential function.

Degraded power MOSFET effects on Class-A power amplifier: Modelling studies considering feedback

The purpose of the study is proposing a gate oxide degraded MOSFET model that represents the degraded MOSFET effects on Class-A power amplifier parameters. The model includes electrical stress induced threshold voltage and transconductance parameter instabilities of transistor. The change in threshold voltage is between 3.2 V and -1 V; the change in transconductance parameter is between 0.4A/V2 and 0.004A/V2. The circuit model is formed by using a voltage source at the gate terminal and a resistor at the source terminal of transistor. Simulations with the proposed model are performed and simulation results are compared experimental DC and AC measurements of Class-A amplifier with and without feedback resistor during stress. To improve the model, we also proposed a tuning circuit. Its seen that, the proposed model in the study is successful to simulate the stress induced change in gain, efficiency of Class-A power amplifier.

Impact of Bias Temperature Stress on IGZO/Ni/IGZO Steep Subthreshold Vertical Current Driver Fabricated at Room Temperature

Impact of bias-temperature stress (BTS) has been assessed in a three-terminal vertical current driver fabricated by room temperature processing of IGZO/Ni/IGZO stack on a p-silicon substrate. Under normal working condition and at a low voltage, the driver exhibits 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sup> ON-OFF current ratio with remarkable 46 mV/decade subthreshold slope, because of 0.89 eV Schottky barrier presented by the Ni/IGZO interfaces and linear superposition of thermionic-field, thermionic and diode currents of the driver as obtained by bias dependent variable energy offsets between the Ni and the IGZO Fermi energy levels. Furthermore, Schottky gate eliminates charge trapping induced threshold voltage instability as commonly found in planar IGZO thin film transistors, as a result of which excellent current stability under both ON and OFF states was found even when bias stress of more than 5 times the nominal working bias was applied to the driver for 12 hours. Employing accelerated stress bias progressive current degradation of the driver was further induced and assessed in detail

Threshold voltage instability and polyimide charging effects of LTPS TFTs for flexible displays

In this paper, we investigate the Vth shift of p-type LTPS TFTs fabricated on a polyimide (PI) and glass substrate considering charging phenomena. The Vth of the LTPS TFTs with a PI substrate positively shift after a bias temperature stress test. However, the Vth with a glass substrate rarely changed even with increasing stress. Such a positive Vth shift results from the negative charging of fluorine stemmed from the PI under the gate bias. In fact, the C–V characterization on the metal–insulator-metal capacitor reveals that charging at the SiO2/PI interface depends on the applied gate bias and the PI material, which agrees well with the TCAD simulation and SIMS analyses. As a result, the charging at the SiO2/PI interface contributes to the Vth shift of the LTPS TFTs leading to image sticking.

GaN power IC design using the MIT virtual source GaNFET compact model with gate leakage and V T instability effect

This work presents the MIT virtual source GaNFET model for GaN integrated circuit (IC) design, which is adapted to model the threshold voltage (V T) instability and p-GaN gate leakage. Because of the lack of GaN pFETs, the source follower topology is often implemented in GaN ICs, suffering from an instable V T drop from rail to gate. With the adapted model, the simulation successfully reproduced the evolution of the output waveforms of a monolithically integrated GaN driver circuit under switching stress. Moreover, the gate voltage redistribution of the power p-GaN gate HEMTs controlled by the integrated GaN driver is evidently proved to strongly depend on the gate leakage. If neglecting the V T shift and gate leakage, the design could induce some malfunction.

On the Challenges of Reliable Threshold Voltage Measurement in Ohmic and Schottky Gate p-GaN HEMTs

For large scale testability of p-GaN HEMTs it is essential to investigate threshold voltage ( $\text{V}_{\mathrm{ th}}$ ) instability from the perspective of the measurement induced instability. In this paper the impact of accumulated gate bias stress during standard transfer characteristic measurements ( $\text{I}_{\mathrm{ D}}$ - $\text{V}_{\mathrm{ G}}$ ) in a p-GaN AlGaN/GaN-on-Si normally off HEMT is quantitatively analysed and modeled. This illustrates the associated threshold voltage ( $\text{V}_{\mathrm{ th}}$ ) instabilities and leads to a better understanding of the $\text{V}_{\mathrm{ th}}$ measurement challenges of a p-GaN HEMT. Upon an application of a constant gate bias close to nominal $\text{V}_{\mathrm{ th}}$ the drain current $\text{I}_{\mathrm{ D}}$ shows an initial marginal rise, followed by a short stable period ( $\text{I}_{\mathrm{ Dstable}}$ - $\text{T}_{\mathrm{ zone}}$ ) and a steep decay period. The effective bias history built on the gate stack varies when pulse on-time (Ton) or step time (Tstep), corresponding to pulsed or DC step $\text{I}_{\mathrm{ D}}$ - $\text{V}_{\mathrm{ G}}$ measurements, are varied. We find that this can lead to a $\text{V}_{\mathrm{ th}}$ variation of up to 20%. It is also observed that the choice of Ton and Tstep determines whether $\text{I}_{\mathrm{ D}}$ is measured in $\text{I}_{\mathrm{ Dstable}}$ - $\text{T}_{\mathrm{ zone}}$ or the rise or decay periods. Measurement induced $\text{V}_{\mathrm{ th}}$ instability is attributed to trapping of 2DEG electrons at the AlGaN barrier and we demonstrate that an ohmic gate contact, in comparison to the Schottky gate contact, may compensate for the trapped 2DEG electrons by hole injection across the AlGaN barrier. Experimental results of $\text{V}_{\mathrm{ th}}$ stability under the same stress conditions for a Schottky and ohmic gate contact are supported by a detailed TCAD analysis.

Bias Temperature Instability of Silicon Carbide Power MOSFET under AC Gate Stresses

With increasing applications of silicon carbide power MOSFETs, more attention is being paid to reliability issues, among which the long-term stability of the gate threshold voltage is of paramount importance. In this article, laboratory experiments are conducted to investigate the threshold voltage instability under ac gate stresses with different duty ratios, and on and off -state gate voltages. It is found that no prominent drift would occur even for bipolar gate stresses, as long as the off -state gate voltage is within (higher than) the critical negative bias voltage which is related to the device fabrication process. Furthermore, not only the gate voltage swing but also the gate voltage polarity will affect the speed of threshold voltage drift when it occurs. The findings are intended for better understanding and management of potential threshold voltage drift in device applications.

Current Understanding of Bias-Temperature Instabilities in GaN MIS Transistors for Power Switching Applications

GaN-based high-electron mobility transistors (HEMTs) have brought unprecedented performance in terms of power, frequency, and efficiency. Application of metal-insulator-semiconductor (MIS) gate structure has enabled further development of these devices by improving the gate leakage characteristics, gate controllability, and stability, and offered several approaches to achieve E-mode operation desired for switching devices. Yet, bias-temperature instabilities (BTI) in GaN MIS transistors represent one of the major concerns. This paper reviews BTI in D- and E-mode GaN MISHEMTs and fully recess-gate E-mode devices (MISFETs). Special attention is given to discussion of existing models describing the defects distribution in the GaN-based MIS gate structures as well as related trapping mechanisms responsible for threshold voltage instabilities. Selected technological approaches for improving the dielectric/III-N interfaces and techniques for BTI investigation in GaN MISHEMTs and MISFETs are also outlined.

Deep Trap Characterization and the Kink Effect in AlGaN/GaN HEMTs

This article presents the study of trapping effects in AlGaN/GaN high electron mobility transistors (HEMTs). Conventional methods like temperature-dependent capacitance-voltage (CV) and pulsed-IV (PIV) have been employed to quantify the traps present in the device layers. Apparent threshold voltage (VTH) instability as well as lag in the drain current after pulsing are evident. The kink in the drain current has been taken up to observe the trapping signature for devices with two different gate lengths. A modified drain and gate pumping methodology which has been designated as pre-measurement run (PMR) has been presented to get a deeper insight into the kink effect in these devices. Constant maximum field (CMF) PMR shows substantial change in the drain current, whereas negligible change for variable maximum field (VMF) PMR is observed, which confirms the dominant impact of trapping within the heterostructure and field assisted detrapping through Poole-Frenkel emission. Multiple traps have also been identified within the epitaxial layers with the E2 trap (Ea (activation energy) = 0.69 eV) which can be held responsible for the kink observed in the DC characteristics as observed from pulsed drain lag characteristics.

Surface Preconditioning and Postmetallization Anneal Improving Interface Properties and Vth Stability under Positive Gate Bias Stress in AlGaN/GaN MIS‐HEMTs

Trap states at the dielectric/GaN interface of AlGaN/GaN‐based metal–insulator–semiconductor high electron mobility transistors (MIS‐HEMTs) can cause threshold voltage (Vth) instability especially under positive gate bias stress. Herein, the influence of O2 plasma surface preconditioning (SPC) before the atomic layer deposition of the Al2O3 gate dielectric and of N2 postmetallization anneal (PMA) after gate metallization on the Al2O3/GaN interface quality is investigated. The interface is characterized by multifrequency capacitance–voltage measurements which show a smaller frequency dispersion after the employment of SPC and PMA treatments with a reduction of the interface trap density Dit to a value in the order of 2 × 1012 cm−2 eV−1 near the conduction band edge. The effectiveness of SPC and PMA is demonstrated in Al2O3/AlGaN/GaN MIS‐HEMTs by pulsed current–voltage measurements which reveal improved Vth stability.