Threshold Logic Gates Research Articles

Tunable anti-ambipolar vertical bilayer organic electrochemical transistor enable neuromorphic retinal pathway

Increasing demand for bio-interfaced human-machine interfaces propels the development of organic neuromorphic electronics with small form factors leveraging both ionic and electronic processes. Ion-based organic electrochemical transistors (OECTs) showing anti-ambipolarity (OFF-ON-OFF states) reduce the complexity and size of bio-realistic Hodgkin-Huxley(HH) spiking circuits and logic circuits. However, limited stable anti-ambipolar organic materials prevent the design of integrated, tunable, and multifunctional neuromorphic and logic-based systems. In this work, a general approach for tuning anti-ambipolar characteristics is presented through assembly of a p-n bilayer in a vertical OECT (vOECT) architecture. The vertical OECT design reduces device footprint, while the bilayer material tuning controls the anti-ambipolarity characteristics, allowing control of the device’s on and off threshold voltages, and peak position, while reducing size thereby enabling tunable threshold spiking neurons and logic gates. Combining these components, a mimic of the retinal pathway reproducing the wavelength and light intensity encoding of horizontal cells to spiking retinal ganglion cells is demonstrated. This work enables further incorporation of conformable and adaptive OECT electronics into biointegrated devices featuring sensory coding through parallel processing for diverse artificial intelligence and computing applications.

Implementation and Applications of a Ternary Threshold Logic Gate

Implementation and Applications of a Ternary Threshold Logic Gate

Don’t-Care-Based Logic Optimization for Threshold Logic

In this paper, we present a don’t-care-based threshold logic gate (TLG) minimization method for threshold logic network (TLN) optimization. We first introduce a sufficient condition for the don’t cares of a TLG to exist in a TLN and propose a logic-implication-based method to identify the don’t cares. Then, we present two different methods for minimizing the TLG with the don’t cares. The first one is an integer linear programming (ILP)-based method. We model the minimization problem as an ILP problem, and propose an approach to compute the necessary constraints of the ILP formulation. The second one is a heuristic method adapted from a threshold function identification approach. In the experiments, we applied the proposed methods to two sets of TLNs generated by the up-to-date synthesis technique. The results show that, for the two sets of TLNs, the ILP-based method achieves an average of 12% and 23% area reduction without any overhead on the TLG count and logic depth. Furthermore, the heuristic method is more efficient than the ILP-based method with only a little quality loss.

A Novel ASIC Design Flow Using Weight-Tunable Binary Neurons as Standard Cells

In this paper, we describe a design of a mixed signal circuit for a binary neuron (a.k.a perceptron, threshold logic gate) and a methodology for automatically embedding such cells in ASICs. The binary neuron, referred to as an FTL (flash threshold logic) uses floating gate or flash transistors whose threshold voltages serve as a proxy for the weights of the neuron. Algorithms for mapping the weights to the flash transistor threshold voltages are presented. The threshold voltages are determined to maximize both the robustness of the cell and its speed. The performance, power, and area of a single FTL cell are shown to be significantly smaller (79.4%), consume less power (61.6%), and operate faster (40.3%) compared to conventional CMOS logic equivalents. Also included are the architecture and the algorithms to program the flash devices of an FTL. The FTL cells are implemented as standard cells, and are designed to allow commercial synthesis and P&R tools to automatically use them in synthesis of ASICs. Substantial reductions in area and power without sacrificing performance are demonstrated on several ASIC benchmarks by the automatic embedding of FTL cells. The paper also demonstrates how FTL cells can be used for fixing timing errors after fabrication.

Heterogeneous FPGA Architecture Using Threshold Logic Gates for Improved Area, Power, and Performance

The flexibility of field-programmable gate arrays (FPGAs) is attributed to the reconfigurability of their basic logic elements (BLEs). Traditionally, the BLEs are comprised of one or more lookup tables (LUTs) of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$n$ </tex-math></inline-formula> inputs, that are designed to implement Boolean functions of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$n$ </tex-math></inline-formula> or fewer inputs. In an attempt to reduce the area and power consumption that comes from using LUTs, a number of complex LUT architectures have been reported. Although most of the proposed complex LUT architectures have resulted in reduced area and power, this has always been at cost of the decreased performance. This article proposes a new FPGA architecture, called threshold logic FPGA (TLFPGA), which results in significant improvement in performance, power, and area (PPA). TLFPGA is comprised of a combination of LUTs and a new type of BLE referred to as a threshold logic cell (TLC) (Muroga, 1987). Although TLCs implement a relatively small subset of Boolean functions known as threshold functions (Muroga, 1987), they require far fewer registers and multiplexers than an LUT, and are also significantly faster. This article describes the architecture of the TLFPGA and a technology mapping algorithm tailored for a TLFGA. On average, TLFPGA designs use 18% fewer registers and multiplexers, which improves the collective area of BLEs by approximately 16%, power by 14%, and performance by 5%. The improvements have been demonstrated in both 40 and 28 nm technologies for ISCAS-85 circuits as well as practical circuits, using industry-standard flows. The improvements were also demonstrated using a layout of the architecture.

Don’t Care Computation and De Morgan Transformation for Threshold Logic Network Optimization

Threshold logic has been attracting great attention from researchers due to the rapid development in nanotechnology-based devices. In the state-of-the-art approach to Threshold Logic Network (TLN) synthesis using don’t cares, we observed that not all the computed don’t cares contribute to the cost minimization of Threshold Logic Gate (TLG). Therefore, in this work, we focus on computing the don’t cares that effectively provide the opportunities for cost minimization. Furthermore, De Morgan’s law for TLGs is applied such that global TLN optimization considering the cost and the number of inverters can be achieved. The experimental results show that the proposed approach is capable of obtaining efficiently a smaller cost and fewer inverters for a set of TLN benchmarks.

A Collision Free Network with Minimal Routing Path for 2&lt;sup&gt;n&lt;/sup&gt; Nodes

In the present work, a simple but complex network which has collision free communications is created. With the help of the binary n-cube the network is formed. This n-cube network connection is formed by connecting distinct N number of nodes which are expressed as a power of 2. If each node has an address of m bits then there are N=2^m number of nodes in the n-cube network. To find out the predefined routing path for the case of this n-cube network, we can apply deterministic algorithm providing us a collision /deadlock free concept. In calculating the predefined routing path(s), node addresses involved in the path are calculated by using the exclusive OR operation, firstly, upon the two node addresses of source and destination, and then, on the derived node-addresses according to the algorithm stated in section 2. Here, the Exclusive-OR operation is performed simply by using 2-input XOR gate which may be made up of either (i) classical CMOS based material, or (ii) Multiple input threshold logic gate , or (iii) Single electron tunneling Transistor (SET). We are concentrated in the case of CMOS based XOR circuit. In this work, an E-cube Routing on a 6-dimensional hypercube has been designed and constructed. We have tried to find out the node addresses for predefining the deadlock free routing path for any set of “source and destination”. To develop a “Collision free network with minimal Routing”, a number of Exclusive-OR gates are arranged in a pattern discussed in section 3 and the desired circuit is implemented. The implemented circuit can supply the predefined path nodes through which the signal/packets/data can pass. Regarding the experimental input –output values, some truth tables are depicted in substantial places. At the time of applying the algorithm, we have investigated that for 6-dimentional hypercube, the maximum path length are confined to 6, i.e. whenever the source and destination points are provided, then 6-node points are produced. Among these 6-pionts some of them may have identical values. As a result path length should be less than 6. For the network, the time required to travel a path is measured and shown. The net designed and implemented must a be a collision free one, since when a truth table is written, there would not be any pair of nodes identical in a column.

Threshold Logic Technology based E-cube Routing on a 4-dimensional hypercube

Hypercube network connection is formed by connecting different N number of nodes that are expressed as a power of 2. If each node has an address of m bits then the total number of nodes in the Hypercube network is N=2^m. In calculating the predefined routing path for the case of this E-cube network, we apply deterministic algorithm which gives a deadlock free concept. For determining predefined routing path, node addresses involved in the path are calculated by using the exclusive operation, firstly, on the node addresses of source and destination, next, on the derived nodes according to the algorithm. In the present work, the Exclusive-OR operation is performed with the help of electron-tunneling based XOR gate which is made up of Multiple input threshold logic gate. This multiple input threshold logic gate technology is really different from the existing one. By using an emerging technology we are capable of making an electronic circuit with high speed, low cost, high concentration density, light in weight, reduced gate numbers and low power consumption. This technology is relies on the condition of linear threshold logic and electron-tunneling event. When we are interested in implementing a circuit, a multi-inputs but one-output based logic-gate will be taken account of consideration. In this work, we have designed an E-cube Routing on a 4-dimensional hypercube to find out the node addresses for predefining the deadlock free routing path from source to destination. To develop this “E-cube Routing on a 4-dimensional hypercube”, we must require a specific logic called Exclusive-OR gate and for this, some small components like 2-input OR gate, 2-input AND gates of different input conditions are essential. After arranging this XOR gate in a pattern discussed in section 2, a desired circuit is implemented. All the circuit we are intended to construct are given in due places with their threshold logic and simulation set, the simulation results are provided as well. Different truth tables, derivation of threshold logic expressions are given for clear understanding. We have taken our consideration of whether the present work circuits are faster or slower than the circuits of CMOS based- and Single electron transistor (SET) based-circuits. The power consumed at the time of tunneling event for a circuit is measured and sensed that it exists in the range between 10meV to 250meV which is very small amount. All the combinational circuits we have presented in this work are of ‘generic multiple input threshold logic gate’-based.

An Accumulator using Electron Tunneling Through Tunnel Junction

Instead of an existing logical Technology, by using an emerging technology we will be able to make an electronic circuit with high speed, low cost, high concentration density, light in weight, reduced gate numbers and low power consumption. This technology is based on the linear threshold logic condition and electron-tunneling event. At the time of implementing a circuit, a multi-inputs but one-output based logic-node will be brought in our consideration. In this work, we have designed a 1-bit accumulator and then implemented it. To develop an accumulator, some small components like 2-input AND, 3-input AND, 3-input OR, 8-input OR, 9-input OR gate and above all a JK Flip-flop (for 1-bit) are to be collected and connected them in logical order to obtain the proper circuit. After verifying all their characteristics with the results obtained from the simulator, we have built a 1-bit accumulator. All the small components are provided in due places. They are analyzed, detected their threshold logic equations, shown their threshold logic gates (TLGs), tabulated their truth tables, drawn their input-output waveforms, given their respective circuits with exact parameter values. In the accumulator, there are nine control variables S1 through S9 in view of performing the operations (i) Addition, (ii) clear, (iii) complement, (iv) AND, (v) OR, (vi) XOR, (vii) Right-shift, (viii) Left-shift and (ix) increment with positive triggering clock pulses. Whether our present work’s circuits are faster or slower with respect to the similar circuits of CMOS based- and Single electron transistor (SET) based circuits are compared and observed that our TLG based circuits are faster than the CMOS and SET based circuits. The power consumed for tunneling event for a circuit is measured and sensed that it would remain in the range of 10meV to 250meV which is low. All the circuits we have presented in this work are of ‘generic multiple input threshold logic gate’ which is elaborately discussed.

Optical Bistability of 1-D Photonic Crystals Containing of Nonlinear Plasma

In this article, a novel nonlinear model is proposed to describe the permittivity of the plasma, and the nonlinear optical bistable phenomenon of the 1-D photonic crystals, which is composed of a nonlinear plasma defect layer, is theoretically investigated by the conventional transfer matrix method (TMM) under TM wave. It is figured out that the permittivity of nonlinear plasma exists in bistable state. Then, the tuning effects of the number of the photonic crystals’ (PCs) periodic layers, the incident frequency, the thicknesses of the nonlinear plasma layer, and the incident angle on the optical bistability (OB) have been emphatically studied. Additionally, the transmission and the reflectance under the influences of this bistable tuning are further proposed. The calculated results show that the adjustment of the OB can be achieved without changing the multi-layer material geometry. This multi-composite nonlinear plasma defect structure with the tunable bistable phenomenon can be applied to numerous valuable optical devices, such as novel optical power threshold devices, logic gates, and optical information memory.

A High-Speed Bidirectional Register with Parallel Loading using single electron Threshold Logic Technology

In this work we have concentrated our attention to a High Speed 4-bit Bidirectional Register with Parallel Loading counting on the principle of threshold logic gates (TLG). After determining the number of logic gates and other circuits needed to complete the desired circuit for our work, we implement some gates and circuits made up of tunnel junctions and capacitances. Some multi-inputs (greater than two) are designed or implemented with the assistance of modified version of the generic multi-input TLG. The types of gates suitable for the implementing the bidirectional Register are 3-input AND, 3-input NAND and 4-input OR gates, in addition an inverter and a more complex circuits like 4:1 Multiplexer are the part and parcel of the desired device. With the help of a 3-input AND gate and a 4-input OR gate, a 4:1 Multiplexer is built. By using the 3-input NAND gate a memory element – D Flip-flop is constructed. At last 4 number of 4:1 Multiplexers and another four number of D Flip-flops are combined in a parallel pattern to implement a 4-bit Bidirectional Register with Parallel Loading. Each component is made after analyzing their corresponding threshold linear equations. After constructing the threshold circuits, again they are formed by using the parameters as capacitors, tunnel junctions with their internal resistances. All the circuit, which are constructed, are verified by simulation with the help of SIMON and the result obtained are investigated and found that they are matched with the theoretical results. For comparing the fastness of our circuit with the CMOS-based or single electron transistor (SET) based circuit, the processing delays of all gates/ circuits are determined. How much power they consume are measured as well. Comparing the delays of CMOS-based and SET based circuit with the TLG based circuit we have decided that our 4-bit Bidirectional Register with Parallel Loading is speedier.

Design of basic logic gates using optical threshold logic

Threshold Logic Gate (TLG) is a potential alternative of Boolean Logic circuit. It is one of the fundamental components of neural network. An Optical Threshold Logic Gate (OTLG) has been designed in this paper, using a reflector telescopic system and a resonant Fabry-Perot cavity. Threshold logic gate consists of a weighted summing unit followed by a comparator. In the proposed OTLG, the weight of the input signal is varied using a polarizer-analyser combination. The threshold value, which is the reference of the comparator, is applied into the Fabry–Perot cavity with the help of a Beam splitter . AND, OR and NOT gates are implemented by setting the threshold values of the proposed OTLG.The system has been modelled analytically and studied using MATLAB and FINESSE. The simulation results for OTLG based Basic Gates are presented here.

An 8-Bit Full-Adder Implementation Using Single Electron Tunneling (SET) Technology (Dept.E)

Single Electron Tunneling (SET) devices have come to be considered as promising candidates for future ultra-low power and high-density integrated circuits. Their potential for ultra-low power is related to that the operation is based on only a few electrons. The term Single Electron Tunneling (SET) technology has been selected for devices sensitive to the manipulation of a single electron even if the device itself requires in fact few electrons. Besides, SET provides a simple and elegant solution for implementing threshold Logic Gates (TLGs). This paper presents a SET TLG one-bit full-adder implemented in SET technology. The paper then introduces the design and implementation of an 8-bit SET TLG full-adder and presents its SIMON 2 simulation results.

Threshold Function Identification by Redundancy Removal and Comprehensive Weight Assignments

The identification of threshold function (TF), which determines whether a Boolean function can be represented by an linear threshold logic gate (LTG) or not, is a fundamental but important task in the theories of threshold logic. In this paper, we propose a more efficient and effective algorithm of TF identification by constructing the system of irredundant inequalities and adjusting the weight assignment comprehensively. This is the first non-ILP-based approach that is able to identify all the eight-input TFs. The experimental results demonstrated that the proposed approach is more effective than all the existing non-ILP-based approaches and the LTGs obtained by the proposed approach are optimal for near 100% cases. For TFs with 9–15 inputs, the proposed approach can identify 100 000 randomly generated TFs as well in a reasonable CPU time.

Magnitude Comparator Realization using Threshold Logic

Threshold logic design can be regarded as an alternative method of traditional logic gate design. Threshold logic can be considered as the primary logic of brain. Neurons can be considered as threshold logic gates. Each neuron fires when its activation threshold is crossed. The basic idea behind threshold logic is threshold decision principle. Threshold decision principle checks whether the weighted sum of inputs crosses a threshold and accordingly output is defined. Several implementations for threshold logic were proposed. Resistive threshold logic is a new method for threshold logic implementation. In this paper, using the concept of resistive threshold logic, a magnitude comparator is realized. LTSpiceIV and Electric VLSI Design System are the simulation tools used in this work.

Practical Implementation of Memristor-Based Threshold Logic Gates

Current advances in emerging memory technologies enable novel and unconventional computing architectures for high-performance and low-power electronic systems, capable of carrying out massively parallel operations at the edge. One emerging technology, ReRAM, also known to belong in the family of memristors (memory resistors), is gathering attention due to its attractive features for logic and in-memory computing and benefits which follow from its technological attributes, such as nanoscale dimensions, low-power operation, and multi-state programming. At the same time, the design with CMOS is quickly reaching its physical and functional limitations, and further research toward novel logic families, such as threshold logic gates (TLGs), is scoped. In this paper, we introduce a physical implementation of a memristor-based current-mode TLG (MCMTLG) circuit and validate its design and operation through multiple experimental setups. We demonstrate two-input, three-input, and four-input MCMTLG configurations and showcase their reconfiguration capability. This is achieved by varying memristive weights arbitrarily for shaping the classification decision boundary, thus showing a promise as an alternative hardware-friendly implementation of artificial neural networks. Through the employment of real memristor devices as the equivalent of synaptic weights in TLGs, we are realizing components that can be used toward an in silico classifier.

Design and Simulation of a Nanoscale Threshold-Logic Multiplier

Multiplication is one of the most important operations in microprocessors and digital signal processing systems. Different multiplier architectures have been proposed in the literature. One of the most widely used architecture is the Wallace tree multiplier. This multiplier is known for its high speed. However, it occupies a large area. In this paper, we used Threshold Logic Gates instead of conventional logic gates to reduce the area. The multiplier was designed in 65nm CMOS technology, and achieved 28% reduction in the number of transistors compared to the one with conventional logic gates. It also achieved a lower power-delay-product.

Effective Logic Synthesis for Threshold Logic Circuit Design

This paper presents a novel and effective logic synthesis flow able to identify threshold logic functions during the technology mapping process. It provides more efficient logic covering, exploring also redundant cuts. Moreover, the proposed design flow takes into account different circuit area estimations, such as the sum of input weights and threshold values, the gate fanin and the number of threshold logic gates. As a result, the mapped circuits present a reduction up to 47% and 67% in area and logic depth, respectively, in comparison to the most recent related approaches.

Reconfigurable arithmetic logic unit designed with threshold logic gates

In recent years, there is a trend towards the development of reconfigurable circuits where devices using them offer flexibility and performance. Different technologies are explored, such as threshold logic gates (TLGs), which are one of the most promising future technologies, and researchers are examining and improving different characteristics such as density, performance and power dissipation. This research presents a 4-bit arithmetic logic unit (ALU), which was designed using TLGs through reconfigurable logic blocks with a universal circuit configured with three stages based on a floating-gate metal oxide semiconductor transistor with more than one control gate, which was named neu-complementary metal oxide semiconductor (ν-CMOS). The main contribution is that this device is configured as a ν-CMOS inverter and has the ability to program the threshold voltage of its transfer curve by applying an external voltage to the additional control gates. The number of input bits and the magnitude of the weighted input capacitances related to control gates of the ν-CMOS inverters is obtained and analyzed by using the graphical method (floating-gate potential diagram). Finally, the proposed 4-bit ALU shows similar results as those measured from the ALUs implemented in the field programmable gate array evaluation kit and the Motorola chip MC14581B.

Clockless Spintronic Logic: A Robust and Ultra-Low Power Computing Paradigm

Asynchronous logic offers the advantages of no clock tree, robust circuit operation, avoidance of worst-case timing margins, and a reduced emission spectrum. Thus, computational paradigms are sought to attain advantages of clockless logic by leveraging the complementary characteristics of emerging devices and CMOS transistors within novel circuit designs. This paper introduces Spin Torque Enabled NULL Convention Logic (STENCL), which exploits the physical characteristics of non-volatile Domain-Wall (DW) and memristive devices to realize the Quasi-Delay-Insensitive (QDI) NULL Convention Logic (NCL) asynchronous design methodology. First, a formal algorithm is developed to transform NCL-based threshold m-of-n gate realizations to STENCL, in order to generate the corresponding input memristance and NULL module memristance required for nominal currents achieving DW device biasing. Second, hysteresis and set/reset conditions are realized by determining the corresponding current fluctuations required to move the DW within each threshold logic gate to realize all 27 foundational NCL gate structures, which are then simulated to assess energy and delay metrics. Third, a case study of a four-stage pipelined 32-bit IEEE single-precision floating point co-processor implemented as a dual-rail STENCL architecture is compared to a conventional CMOS-based NCL design implemented by an IBM SOI1250 45nm CMOS process. Fourth, a sensitivity analysis is performed to assess the impact of write accuracy and drift on memristor and DW device operation. Results indicate that STENCL-based designs achieve between 2-fold to 20-fold reduction in energy consumption with up to 8-fold reduction in area, over an equivalent CMOS-based NCL design for 32-bit full adders. Comparisons for various four-stage pipelined 32-bit IEEE single-precision floating-point co-processors and ISCAS benchmarks further substantiate those benefits for operation within acceptable tolerances at identical process technology nodes.