Three-variable Functions Research Articles

Implications of nonplanar dual conformal symmetry

Recently, Bern et al. observed that a certain class of next-to-planar Feynman integrals possess a bonus symmetry that is closely related to dual conformal symmetry. It corresponds to a projection of the latter along a certain lightlike direction. Previous studies were performed at the level of the loop integrand, and a Ward identity for the integral was formulated. We investigate the implications of the symmetry at the level of the integrated quantities. In particular, we focus on the phenomenologically important case of five-particle scattering. The symmetry simplifies the four-variable problem to a three-variable one. In the context of the recently proposed space of pentagon functions, the symmetry is much stronger. We find that it drastically reduces the allowed function space, leading to a well-known space of three-variable functions. Furthermore, we show how to use the symmetry in the presence of infrared divergences, where one obtains an anomalous Ward identity. We verify that the Ward identity is satisfied by the leading and subleading poles of several nontrivial five-particle integrals. Finally, we present examples of integrals that possess both ordinary and dual conformal symmetry.

Three-variable symmetric and antisymmetric exponential functions and orthogonal polynomials

Abstract The common exponential functions whose exponents are the scalar products 〈λ,x〉, where x is a real variable and λ is an integer, admit two generalizations to any higher dimension, the symmetric and the antisymmetric ones [KLIMYK, A.—PATERA, J.: (Anti)symmetric multivariate exponential functions and corresponding Fourier transforms, J. Phys. A: Math. Theor. 40 (2007), 10473–10489]. Restriction in the paper to the three variables only allows us to work out many specific properties of the symmetric and antisymmetric functions useful in applications. Such are (i) the orthogonalities, both the continuous one and the discrete one on the 3D lattice of any density; (ii) corresponding discrete and continuous Fourier transforms; (iii) generating functions for the related polynomials in three variables, and others. Rapidly increasing precision of the interpolation with increasing density of the 3D lattice is shown in an example.

Recursion formulas for Srivastava’s general triple hypergeometric function

This paper continues the study of recursion formulas of multivariable hypergeometric functions. In [Recursion formulas for multivariable hypergeometric functions, Asian-Eur. J. Math. 8(4) (2015) Article ID: 1550082, 50 pp.], the authors have given the recursion formulas for three-variable Lauricella functions, three Srivastava’s triple hypergeometric functions and four [Formula: see text]-variable Lauricella functions. We present here the recursion formulas for the general triple hypergeometric function.

Design of a novel RTD-based three-variable universal logic gate

Traditional CMOS technology faces some fundamental physical limitations. Therefore, it has become very important for the integrated circuit industry to continue to develop modern devices and new design methods. The threshold logic gate has attracted much attention because of its powerful logic function. The resonant tunneling diode (RTD) is well suited for implementing the threshold logic gate because of its high-speed switching capability, negative differential resistance (NDR) characteristic, and functional versatility. In this paper, based on the Reed-Muller (RM) algebraic system, a novel method is proposed to convert three-variable non-threshold functions to the XOR of multiple threshold functions, which is simple and has a programmable implementation. With this approach, all three-variable non-threshold functions can be presented by the XOR of two threshold functions, except for two special functions. On this basis, a novel three-variable universal logic gate (ULG3) is proposed, composed of two RTD-based universal threshold logic gates (UTLG) and an RTD-based three-variable XOR gate (XOR3). The ULG3 has a simple structure, and a simple method is presented to implement all three-variable functions using one ULG3. Thus, the proposed ULG3 provides a new efficient universal logic gate to implement RTD-based arbitrary n-variable functions.

Function Synthesis Algorithm of RTD-Based Universal Threshold Logic Gate

The resonant tunneling device (RTD) has attracted much attention because of its unique negative differential resistance characteristic and its functional versatility and is more suitable for implementing the threshold logic gate. The universal logic gate has become an important unit circuit of digital circuit design because of its powerful logic function, while the threshold logic gate is a suitable unit to design the universal logic gate, but the function synthesis algorithm for then-variable logical function implemented by the RTD-based universal logic gate (UTLG) is relatively deficient. In this paper, three-variable threshold functions are divided into four categories; based on the Reed-Muller expansion, two categories of these are analyzed, and a new decomposition algorithm of the three-variable nonthreshold functions is proposed. The proposed algorithm is simple and the decomposition results can be obtained by looking up the decomposition table. Then, based on the Reed-Muller algebraic system, the arbitraryn-variable function can be decomposed into three-variable functions, and a function synthesis algorithm for then-variable logical function implemented by UTLG and XOR2 is proposed, which is a simple programmable implementation.

Тривимірні узагальнені моментні зображення та апроксимації типу Паде для функцій трьох змінних

Тривимірні узагальнені моментні зображення та апроксимації типу Паде для функцій трьох змінних

Complete Logic Functionality of Reconfigurable RTD Circuit Elements

Innovative nanoscale devices have been developed to enhance future circuit design to overcome physical barriers hindering the CMOS technology. Among the emerging nanodevices, resonant tunneling diodes (RTDs) have demonstrated promising electronic features due to their high-speed switching capability and functional versatility. Great circuit functionality can be achieved through integrating heterostructure FETs (HFETs) in conjunction with RTDs to modulate effective negative differential resistance. In this paper, we propose novel programmable logic elements (PLEs) implemented in threshold gates (TGs) and multithreshold TGs by exploring RTD/HFET monostable-bistable transition logic element (MOBILE) principles. Our three-input PLE can be configured through five binary control bits to realize all the three-variable logic functions, which is, to the best of our knowledge, the first single RTD-based structure that provides complete Boolean logic implementation. It is also a more efficient reconfigurable circuit element than a general lookup table that requires eight configuration bits for three-variable functions. We further extend the design concept to construct a more versatile four-input PLE. A comprehensive comparison of three- and four-input PLEs provides an insightful view of design tradeoffs between performance and area. We present the mathematical proof of PLE's logic completeness based on Shannon expansion, as well as the HSPICE simulation results of the programmable and primitive RTD/HFET gates that we have designed. An efficient control bit generating algorithm is developed by using a special encoding scheme to implement any given logic function. Based on our PLE structures, we propose a reconfigurable architecture, namely MORE, which offers dynamic reconfigurability without incurring latency overheads, due to the intrinsic self-latching property of MOBILE circuits. An efficient reconfiguration data generation algorithm is also built to take full advantage of our MORE architecture. The experimental results indicate that it can help reduce the reconfiguration cost by 37% on average.

Reversible logic synthesis with Fredkin and Peres gates

Reversible logic has applications in low-power computing and quantum computing. Most reversible logic synthesis methods are tied to particular gate types, and cannot synthesize large functions. This article extends RMRLS, a reversible logic synthesis tool, to include additional gate types. While classic RMRLS can synthesize functions using NOT, CNOT, and n -bit Toffoli gates, our work details the inclusion of n -bit Fredkin and Peres gates. We find that these additional gates reduce the average gate count for three-variable functions from 6.10 to 4.56, and improve the synthesis results of many larger functions, both in terms of gate count and quantum cost.

Modelling of ultrafiltration of non-sucrose compounds in sugar beet processing

This paper is a contribution to mathematically describing sugar syrup purification, i.e. ultrafiltration of non-sucrose compounds, based on the experimental data, acquired in a series of batch experiments on flat polyethersulfone cross-flow membranes. Experiments were performed to final concentration factors not less than 1.5 and not greater than 2.3, with flow rates 0.2 and 0.4 m 3 h −1, at the temperatures 30 and 60 °C and for the transmembrane pressures 1 and 4 bar. The suggested mathematical model enables prediction of separation time if the permeate flux models as well as the initial and final concentrations of undesired non-sucrose compounds are known. In this paper, the flux models are proposed as functions of concentration factor ( CF), flow rate ( Q), temperature ( t) and transmembrane pressure (Δ p) as independent variables. So, the following one-, two- and three-variable functions are suggested: J −1( CF), J −1( CF, Q), J −1( CF, t), J −1( CF,Δ p), J −1( CF, Q, t) and J −1( CF, Q,Δ p). By the regression analysis method, parameters in the flux models are determined and they are used for the calculation of process duration. It is concluded that the predicted times underestimate the real times by 10–40% in particular cases. One can assume that the incomplete rejection of non-sucrose compounds by polyethersulfone membranes as well as the loss of sugar due to accumulation at the membrane is responsible for process prolongation.

Properties of Wired Logic

When we design networks with NOR or NAND gates which are implemented with bipolar and MOS transistors, wired logic is usually allowed. The usage of wired logic reduces the network cost and possibly improves the speed because of shorter delays on wired logic than on a gate. Typical logic functions performed by wired logic are AND and OR, which are called wired-AND and wired-OR, respectively. Properties of networks with NOR gates and wired-AND (or wired-OR) are discussed. Some of these properties are used in developing synthesis procedures of optimum networks by the integer programming logic design method. For all three-variable functions, the optimum networks with NOR gates and wired-OR's, designed by this synthesis approach, are shown.

A new classification of logic functions of three variables

This letter presents a new categorization of three-variable logic functions based on tree type multiplexer implementation. Certain generalizations useful in implementing logic functions of a large number of variables are brought out.

Optimum Logic Modules

The results of an exhaustive analysis undertaken to determine the optimum three-input logic modules are examined. The optimum logic module is restricted to realize all three-variable functions in two logic levels, with one polarity available for each input variable. Only one three-input logic module satsifies these restrictions for three variables. All realizations with the fewest logic modules and minimum number of interconnections for all three-variable functions with this logic mocOule are included in a catalog. An algorithm is presented which extends the three properties of this three-input logic module. The four-input logic module from the algorithm has been verified to realize all four-variable functions in two logic levels.

Redundancy for LSI Yield Enhancement

Methods of supplementing digital LSI integrated networks with redundant elements, or groups of elements, for the purpose of increasing network yields during their manufacture are described. It is shown how, with a small percentage of spare rows of memory elements in memory arrays or a small percentage of additional groups of elements in shift-register-like structures, substantial yield improvements may be economically achieved. A limited discretionary-wiring technique for random logic is contrasted with an existing more general approach. The concept of treating groups of interconnected elements, rather than single gates, as the smallest units that are to be diagnosed and replaced with spares, is proposed as a means for reducing the complexity (and the corresponding shrinkage) as well as the cost of discretionary interconnections. The concept of a temporary test metallization that deliberately interconnects groups of elements (where each group realizes some combinational switching function) into testable arrays, as one step in manufacturing to reduce the number of test probings and tests, is introduced. The efficient testing of an array of three-variable parity functions with four array tests is demonstrated. The tests applied to such an array, unlimited in dimension, can detect and locate a single failed group and can detect the presence of more than one failed group. Multiple faults can be located with additional sequential array tests if the number of defective groups is not large.