Redundancy for LSI Yield Enhancement

Abstract

Methods of supplementing digital LSI integrated networks with redundant elements, or groups of elements, for the purpose of increasing network yields during their manufacture are described. It is shown how, with a small percentage of spare rows of memory elements in memory arrays or a small percentage of additional groups of elements in shift-register-like structures, substantial yield improvements may be economically achieved. A limited discretionary-wiring technique for random logic is contrasted with an existing more general approach. The concept of treating groups of interconnected elements, rather than single gates, as the smallest units that are to be diagnosed and replaced with spares, is proposed as a means for reducing the complexity (and the corresponding shrinkage) as well as the cost of discretionary interconnections. The concept of a temporary test metallization that deliberately interconnects groups of elements (where each group realizes some combinational switching function) into testable arrays, as one step in manufacturing to reduce the number of test probings and tests, is introduced. The efficient testing of an array of three-variable parity functions with four array tests is demonstrated. The tests applied to such an array, unlimited in dimension, can detect and locate a single failed group and can detect the presence of more than one failed group. Multiple faults can be located with additional sequential array tests if the number of defective groups is not large.