Ternary Logic Research Articles

Design of Low Power Ternary Logic Encoder and ADC using CNTFET

Ternary logic has received substantial attention over the past decade due to its compensations of smaller chip area and interconnection compared to outmoded binary logic. Carbon Nanotube Field Effect Transistor (CNTFET) technology is widely used for ternary logic implementation due to its versatile threshold voltages. The increased power consumption in current designs utilizing CNFETs, as linked to binary logic, is attributed to elevated static power dissipation within the design. This work recommends alternative triple encoder designs with a focus on reducing the consumption of power. The model uses an additional Vdd/2 supply voltage to decrease static power dissipation and encoder power delay. Cadence virtuoso-based circuit simulations are implemented for the proposed encoder design.

A Ternary Inverter Based on Hybrid Conduction Mechanism of Band-to-Band Tunneling and Drift-Diffusion Process.

In this paper, a novel transistor based on a hybrid conduction mechanism of band-to-band tunneling and drift-diffusion is proposed and investigated with the aid of TCAD tools. Besides the on and off states, the proposed device presents an additional intermediate state between the on and off states. Based on the tri-state behavior of the proposed TDFET (tunneling and drift-diffusion field-effect transistor), a ternary inverter is designed and its operation principle is studied in detail. It was found that this device achieves ternary logic with only two components, and its structure is simple. In addition, the influence of the supply voltage and the key device parameters are also investigated.

Ternary logic in the optical controlled-SWAP gate based on Laguerre-Gaussian modes of light

The need set by a computational industry to increase processing power, while simultaneously reducing the energy consumption of data centers, became a challenge for modern computational systems. In this work, we propose an optical communication solution, that could serve as a building block for future computing systems, due to its versatility. The solution arises from Landauer’s principle and utilizes reversible logic, manifested as an optical logical gate with structured light, here represented as Laguerre-Gaussian modes. We introduced a phase-shift-based encoding technique and incorporated multi-valued logic in the form of a ternary numeral system to determine the similarity between two images through the free space communication protocol.

A Mixture of Negative-, Zero-, and Positive-Differential Transconductance Switching from Tellurium/Indium Gallium Zinc Oxide Heterostructures.

Conventional transistors have long emphasized signal modulation and amplification, often sidelining polarity considerations. However, the recent emergence of negative differential transconductance, characterized by a drain current decline during gate voltage sweeping, has illuminated an unconventional path in transistor technology. This phenomenon promises to simplify the implementation of ternary logic circuits and enhance energy efficiency, especially in multivalued logic applications. Our research has culminated in the development of a sophisticated mixed transconductance transistor (M-T device) founded on a precise Te and IGZO heterojunction. The M-T device exhibits a sequence of intriguing phenomena, zero differential transconductance (ZDT), positive differential transconductance (PDT), and negative differential transconductance (NDT) contingent on applied gate voltage. We clarify its operation using a three-segment equivalent circuit model and validate its viability with IGZO TFT, Te TFT, and Te/IGZO TFT components. In a concluding demonstration, the M-T device interconnected with Te TFT achieves a ternary inverter with an intermediate logic state. Remarkably, this configuration seamlessly transitions into a binary inverter when it is exposed to light.

A ternary gate-connected threshold switching thin-film transistor

Multi-valued logic has been a significant focus of research in various fields with the advancement of information technology. One approach to realizing ternary logic is integrating of a threshold switching (TS) device with a transistor, but this method often entails a complex fabrication process. This work suggests a ternary gate-connected threshold switching thin-film transistor (TS-TFT) by serially connecting the TS device with a bottom-gate thin-film transistor (TFT). The fabrication process is simplified with a structure that shares electrodes and insulators. Different threshold voltages from TS and TFT devices produce stable multiple states. The Pt/HfO2/TiN TS device has an electronic trapping/detrapping switching mechanism that exhibits low power consumption and high reliability. With the superior electrical performance of an amorphous indium gallium zinc oxide TFT, the TS-TFT has stable endurance. Furthermore, pulse switching and ternary inverter are demonstrated from the practical point of view.

Control Unit of a Three-Ports Hybrid Converter of a Microgrid Based on Ternary Logic Circuits

This paper, provides the design and simulation of the control modes of three different power sources that are commonly used in hybrid systems especially when combining the sources of photovoltaic (PV), electric vehicles (EV) and Energy storage system (ESS). The control scenarios discuss the different combinations of sources and loads based on ternary logic system (0,1,2) that has many advantages over the classical binary logic system (0,1). To prove that, first, the ternary logic gates must be verified and simulated as MOSFET by Matlab / Simulink then a ternary logic control (TLCU) will be designed. TLCU can select the right direction of power flow from the energy source to the load based on the ternary truth table that shows the relationship between the inputs (ternary states of sources and loads) and each output that has only two states (ON or Off). At the end of the paper, the circuit of a ternary logic control circuit that can optimize the number of used elements of MOSFET is designed and tested. Comparing to binary, it is expected not only to optimize the number of MOSFET but also to accelerate the speed of operation.

Enhancing high-speed digital systems: MVL circuit design with CNTFET and RRAM

Multiple Value Logic (MVL) circuits in high-speed digital systems can represent significantly more information than traditional binary logic circuits. The increasing demand for enhanced data storage capacity has driven the adoption of MVL circuits. However, designing MVL circuits presents challenges, particularly in achieving improved performance aligned with the desired threshold voltage. To address this challenge, harnessing carbon nanotube field-effect transistors (CNTFETs) has been instrumental in designing MVL circuits. CNTFETs offer distinct advantages due to their large resistors. Furthermore, substituting these resistors with Resistive Random Access Memory (RRAM) to implement Ternary logic circuits enhances storage capacity by enabling multiple resistance states within a single cell. This paper presents a novel MVL circuit design that leverages the unique characteristics of CNTFETs and RRAM. Additionally, gate implementation is explored using a Recurrent Neural Network − Long-Short Term Memory (RNN-LSTM) based Tasmanian Devil Optimization algorithm. The practical implementation uses Synopsis HSPICE software with CNTFET technology at 32 nm. A comprehensive performance analysis compares this approach with state-of-the-art solutions regarding delay, area, and power consumption. Significant reductions in area, power consumption, and transistor count are revealed with the proposed approach.

Philosophy and Logic in a Time of War

Abstract This interview was given by Yaroslav Shramko (b. 1963), professor of the Department of Philosophy and rector of the Kryvyi Rih State Pedagogical University (Ukraine). His main research interests lie in the fields of logic and analytical philosophy. He has carried out several projects on modern non-classical logic: 1996–1998, within the Alexander von Humboldt Foundation Fellowship at Humboldt University in Berlin (Germany); 1999–2000, within the Fulbright Program at Indiana University in Bloomington (USA); and 2003–2004, as a Wilhelm Bessel Awardee at Dresden University of Technology (Germany), among others. He has been a frequent invited speaker at international conferences and congresses. He is a member of the editorial boards of several international logic journals, such as Logic and Logical Philosophy (Torun, Poland), Bulletin of the Section of Logic (Łódź, Poland), European Journal of Mathematics (Springer), and Studia Logica (Springer). Prof Shramko is the author of “Truth and falsehood: An inquiry into generalized logical values” (Springer, 2011, joint work with Heinrich Wansing) and a number of articles on logic and analytic philosophy in peer-reviewed international journals.

Implementation of Full adder in Multiple valued Logic for Performance Optimization

Multiple valued logic is now becoming more significant in real-world applications. Mathematical design blocks are essential in digital and mixed-signal systems. A system's arithmetic blocks often use the most power because of the high switching activity. Implementations of quaternary arithmetic may be a way to cut down on energy use while improving system performance. In this paper, quaternary adders are developed using three different approaches, and their binary equivalents are evaluated in terms of size, predicted logic depth, and performance estimation.

On state monadic MV-algebras

Monadic MV-algebras are an algebraic model of the predicate calculus of the Łukasiewicz infinite valued logic in which only a single individual variable occurs. In this paper, we extend monadic MV-algebras with a state operator that describes algebraic properties of states. The resulting variety of algebras will be called state monadic MV-algebras. First, we introduce state monadic MV-algebras and establish a natural equivalence between the category of state monadic MV-algebras and the category of state monadic ℓ-groups with strong units. Moreover, we prove that the class of all state monadic ideals in state monadic MV-algebras is a complete Heyting algebra. In particular, by studying extended state monadic ideals, we prove that the set of all stable state monadic ideals in state monadic MV-algebras is a complete Heyting algebra. Also, the class of all involutory state monadic ideals in state monadic MV-algebras is a complete Boolean algebra. Finally, we introduce and characterize some members in the variety of state monadic MV-algebras, which are subdirectly irreducible, simple, semisimple, local and semilocal, respectively.

Tri-state GNRFET-based fast and energy-efficient ternary multiplier

As silicon field-effect transistors encounter increasing scaling challenges, digital system designers are shifting their attention towards multi-valued logic (MVL), specifically ternary logic. The graphene nanoribbon field-effect transistor (GNRFET) emerges as a compelling alternative among post-MOSFET technologies for the implementation of ternary logic. This paper delves into the computational intricacies of ternary logic, underscores the outstanding features of GNRFET technology, and introduces a novel GNRFET-based 1-trit ternary multiplier (TMUL) requiring only 26 transistors. The performance of the design is assessed using the Synopsis HSPICE simulator with a 32-nm GNRFET model file operating at VDD = 0.9 V. The proposed TMUL surpasses existing designs due to its efficient paths with a minimal number of transistors for each output transition, a singular power supply voltage, and an extended voltage division scheme. In comparison to other contemporary TMUL designs, the proposed design exhibits a notable enhancement, showcasing a 21.42 % reduction in delay, a 33.11 % decrease in power-delay-product (PDP), and a 58.17 % decrease in energy-delay-product (EDP). Additionally, the design is subjected to thorough testing under diverse conditions including process, voltage, temperature (PVT) fluctuations, and load variations, validating its reliability and robustness.

Taking back and giving back on TikTok: Algorithmic mutual aid in the platform economy

This article explores three genres of TikTok content in which creators and users collaborate to re(direct) the value they create on-platform toward specific needs, people, and causes. Drawing from literatures on platform economies, user and creator labor, algorithmic imaginaries and resistance, and mutual aid, we used algorithmic ethnography to identify and define major genres of content, eventually creating a sample of 192 TikTok videos (including comments and metadata) and conducting a thematic analysis. The videos and practices shared the following themes: realizations of on-platform value, tactics oriented against platform logics and monetization programs, shared theories of value, and digital collaboration for a cause. We argue the genres constitute forms of algorithmic mutual aid, a practice unfolding in platform economies that demonstrates people’s increased recognition of the value of their digital labor, and efforts to reorient platform logics of value, visibility, and compensation to care for one another.

Reimagining the municipal economy: The emancipatory politics of the people’s budget movement

Budgets are often thought of as boring, invoking the tedium of bookkeeping. The summer of 2020 suggested otherwise. As America’s plague of police brutality combined with the death-dealing blows of the COVID-19 pandemic and a wave of urban uprising gripped US cities, activists turned their organising attention to municipal budgeting. From Seattle to Atlanta, demands rang out for cities to #defund the police, rethink public safety and adopt budgets for the people. Since then, the people’s budget movement has grown in strength at the municipal level, including in Los Angeles, Chicago, Louisville, Jacksonville, Minneapolis and Nashville, among other cities. What should urban studies scholars make of these struggles and from the aspirations and visions that impel them? This paper uses a case study of the Nashville People’s Budget Coalition (NPBC) to examine how municipal budgeting processes and public financing have become new sites of theorisation, debate and political intervention. We demonstrate how the people’s budget movement offers a new calculus for municipal budgeting that radically reconceptualises the logics of value and care that underpin economic thought and public accounting practices. We conclude by considering avenues through which a scholarly agenda for economic democracy in solidarity with movement organisers could be expanded.

Binary and ternary logic-in-memory using nanosheet feedback field-effect transistors with triple-gated structure

In this study, we demonstrate binary and ternary logic-in-memory (LIM) operations of inverters and NAND and NOR gates comprising nanosheet (NS) feedback field-effect transistors (FBFETs) with a triple-gated structure. The NS FBFETs are reconfigured in p- or n-channel modes depending on the polarity of the gate bias voltage and exhibit steep switching characteristics with an extremely low subthreshold swing of 1.08 mV dec–1 and a high ON/OFF current ratio of approximately 107. Logic circuits consisting of NS FBFETs perform binary and ternary logic operations of the inverters and NAND and NOR gates in each circuit and store their outputs under zero-bias conditions. Therefore, NS FBFETs are promising components for next-generation LIM.

Efficient 3’s Complement Circuit for Ternary-ALU

Carrying more information makes the ternary-computation effective in order to reduce the interconnect complexity and hence, ternary computer can be the future alternative to conventional (binary) counterpart. As a consequence the ternary arithmetic has become the centre of choice among circuit/system researcher in recent time. Ternary adder/subtractor is the integral part of Ternary Arithmetic Logic Unit (TALU) and the 3’s complement is used to represent negative ternary number in TALU. This work proposes a new two-step low hardware-cost strategy to converts ternary input into its 3’s complement output. Novel hardware optimization using normal process Enhancement-type Metal Oxide Semiconductor (E-MOS)-transistor is explored and exploited to design proposed 4-trit 3’s complement generator on 32nm standard CMOS technology with 0.9V supply-rail at 27°C temperature using typical MOS-transistor. Unbalanced ternary digit “0”, “1” and “2” are denoted with ground, supply/2 and supply respectively. The T-Spice transient simulations with all possible test patterns validate the working of proposed circuit and the corresponding speed-power characteristic is compared with most recent counterpart. The circuit performance is also evaluated with different load condition. The 4-trit 3’s complement circuit is extended next to propose 16-trit 3’s complement generator and the impact of Process and Environmental variation on the proposed circuit is studied.

Design method for unbalanced ternary logic family based on binary memristors

Design method for unbalanced ternary logic family based on binary memristors

Path Analysis of Sustainable Business Models to Realise Triple Value

Sustainable business models play an important role in the ability of enterprises to achieve sustainable competitive advantage. The formation of sustainable business model needs to integrate the logic of business value and the logic of sustainable development value, and integrate the triple values of economy, society and environment. Taking Shandong Province as the research object, 36 PPP projects in Shandong Province are studied using the clear set qualitative comparative analysis method (csQCA) method to solve the multiple paths leading to high triple value and low triple value of PPP projects, and to explore the characteristics of the paths of sustainable business models to achieve triple value. The study finds that: each key attribute cannot alone constitute a necessary condition for generating the triple value of the PPP project business model; the realisation of the triple value of the PPP project business model is a synergistic effect of multiple complex factors; and there is a mutual substitution relationship between the antecedent and dependent variables under certain circumstances, which provides certain theoretical and managerial insights for sustainable development.

Implicatively Implicit Extensions in Three-Valued Logic

Implicatively Implicit Extensions in Three-Valued Logic

Charge transfer mechanism for realization of double negative differential transconductance

With development of information age, multi-valued logic (MVL) technology utilizing negative differential transconductance (NDT) phenomenon has drawn attention as next-generation computing technology that can replace binary logic. However, because conventional NDT devices primarily use ternary logic, multiple-peak NDT device is required for higher-radix MVL that can process more datasets. Here, van der Waals double-peak anti-ambipolar transistor (AAT) as NDT device was developed by utilizing peak voltage (Vpeak) modulation of NDT peak. For realization of quaternary logic, Vpeak modulation technology was developed through charge transfer mechanism from channel, thereby shifting NDT peak and increasing peak-to-valley current ratio (PVCR). Furthermore, Double-peak AAT was implemented through parallel configuration of two AATs with different Vpeak values. Finally, quaternary inverter with four widely stable logic states was implemented by utilizing the developed double-peak AAT with two distinct NDT peaks and high PVCR. This double-peak AAT is expected to contribute to the development of next-generation MVL technology capable of processing datasets.

Coordination nanosheets based molecular computing for detection and differentiation of high-energy explosives TATB and FOX-7

Detection and differentiation of explosives is an issue of immediacy for security and environmental monitoring. At present, the most operated explosive system combines primary and secondary explosives. Although various advances are presently equipped for identifying primary explosives, the insensitive nature of secondary explosives makes their detection and differentiation challenging. Here, we report three coordination nanosheets (CNs) AM-8-Eu, AM-8-Tb, and AM-8-Zn containing three-way terpyridine ligands (AM-8) and Eu(III), Tb(III), and Zn(II) ions. These CNs act as a highly selective platform for detecting unexplored high-energy explosive 1,1-Diamino-2,2-dinitro ethylene (FOX-7) in solid and solution phases. For AM-8-Zn, calculated molecular electrostatic surface potential revealed two modes of interactions for triaminotrinitrobenzene (TATB) and FOX-7, producing two distinct spectral responses. Digital analysis of these responses revealed a complimentary implication (IMP)/not implication (NIMP) logic function. Finally, the unique feature of IMP gate is used to define all possible sixteen distinct binary Boolean operations on two logic values for “functional completeness”. The detection and differentiation of such insensitive high-energy explosives TATB and FOX-7, where Boolean logic can process information through distinct binary responses in solid and solution phases, have not been witnessed hitherto in a single chemical platform.