Implementation of Full adder in Multiple valued Logic for Performance Optimization

Abstract

Multiple valued logic is now becoming more significant in real-world applications. Mathematical design blocks are essential in digital and mixed-signal systems. A system's arithmetic blocks often use the most power because of the high switching activity. Implementations of quaternary arithmetic may be a way to cut down on energy use while improving system performance. In this paper, quaternary adders are developed using three different approaches, and their binary equivalents are evaluated in terms of size, predicted logic depth, and performance estimation.