Universal Set of CMOS Gates for the Synthesis of Multiple Valued Logic Digital Circuits

Abstract

The design of Multiple Valued Logic (MVL) digital circuits is performed by increasing the representation domain from the two level (N=2) switching algebra to N > 2 levels. Universal sets of MVL CMOS gates allow the synthesis and implementation of any MVL digital circuit. The main drawback of this approach is the lack of existing integrated circuits that implement the universal set of MVL gates. This paper deals with: 1) the design and implementation of a universal set of IC gates, CMOS 0.35 μm technology, that carry out extended AND operators: eAND1, eAND2, eAND3, Successor (SUC), and Maximum (MAX) operators to perform synthesis of any MVL digital circuits; and 2) the synthesis of an MVL multiplexer and latch memory circuits, based on the IC MVL gates, to illustrate the utilization of the proposed IC MVL gates for quaternary MVL. Implemented circuits demonstrate correct functionality of the implemented gates and feasibility of the MVL combinatorial and memory circuit design. The proposed gates allow designing MVL digital circuit taking advantage of the knowledge coming from the binary circuits. By using a methodology based on the boolean algebra, digital circuits designers can take advantage of it to decrease the design learn curve.