Three-stage Operational Transconductance Amplifiers Research Articles

A three-stage single-miller CMOS OTA with no lower load capacitor limit

This work proposes a Single Miller Capacitor (SMC) compensated three-stage Operational Transconductance Amplifier (OTA) for a wide range of load capacitors with a zero minimum load capacitor. The proposed three-stage OTA does not require a minimum load capacitor for OTA to be stable. The proposed work uses two different feed-forward transconductors to enhance the small-signal and large-signal performances of the OTA. This OTA achieves more than 70° phase margin and more than 10dB gain margin with a load capacitor range of 0 to 500pF and consumes less quiescent current. The proposed OTA uses a smaller SMC of 2pF to drive a wide range of load capacitors. Furthermore, it saves the active area of the chip. The proposed OTA is simulated in a cadence virtuoso tool using UMC 90nm CMOS technology with BSIM4 MOSFETs.

Low power three-stage OTA using reverse nested frequency compensation without nulling resistor

This study introduces a novel reverse nested miller compensated high gain three stage operational transconductance amplifier (OTA) that exhibits lower power consumption and maximum allowable voltage swing. In this context, two amplifiers have been employed. The initial amplifier employs PMOS as the primary amplifying component, with a specified IDD value of 200 A. In the subsequent stages, both the second and third amplifiers are biased to operate at a current level of 2 times IDD. These operations are conducted within a 45 m Cadence Virtuoso environment. The other three-stage amplifier employs PMOS as the primary amplifier, with a bias current (IDD) of 4 μA. In a 90 m Cadence Virtuoso environment, both the second and third stages are biased to operate at a current of 5 times IDD. The primary design criteria introduced in this design approach are gain, phase margin, and power consumption, which are thoroughly stated. The circuits undergo Monte Carlo and corner evaluations, and the findings are deliberated about in the conclusion of the research. In order to attain the greatest allowable voltage swing, these amplifiers are fabricated with VDD values of 500 m and 900 m. The output voltage is set to a constant value of VDD/2.

Miller compensated three-stage OTA for a wide range of load capacitors (1 pF to 1 nF)

ABSTRACT In this work, the miller with a feed-forward capacitor compensated three-stage Operational Transconductance Amplifier (OTA) for a wide range of load capacitors is presented. The proposed OTA can drive a load capacitor with a phase margin of more than 60 o from a smaller load capacitor of 1 pF to a larger load capacitor of 1 nF . It is difficult to stabilise multi-stage OTA for a wide range of load capacitors. The OTA needs a good compensator to stabilise the OTA. The proposed compensator uses a miller capacitor along with the small feed-forward capacitor to stabilise the three-stage OTA for a wide range of load capacitors. Usually, the miller compensated multi-stage OTA with more than two stages is unstable for the smaller load capacitors and demands a minimum load capacitor for the OTA to be stable, but the proposed OTA is stable even for a very small load capacitor of 1 pF . The proposed structure uses a slew-rate enhancer (SRE) to enhance the transient performance of the OTA along with the feed-forward transconductors and achieves a settling time of 1.2 μs over the wide range of load capacitors.

A 0.3V Rail-to-Rail Three-Stage OTA With High DC Gain and Improved Robustness to PVT Variations

This paper presents a novel 0.3V rail-to-rail body-driven three-stage operational transconductance amplifier (OTA). The proposed OTA architecture allows achieving high DC gain in spite of the bulk-driven input. This is due to the doubled body transconductance at the first and third stages, and to a high gain, gate-driven second stage. The bias current in each branch of the OTA is accurately set through gate-driven or bulk-driven current mirrors, thus guaranteeing an outstanding stability of main OTA performance parameters to PVT variations. In the first stage, the input signals drive the bulk terminals of both NMOS and PMOS transistors in a complementary fashion, allowing a rail-to-rail input common mode range (ICMR). The second stage is a gate-driven, complementary pseudo-differential stage with an high DC gain and a local CMFB. The third stage implements the differential-to-single-ended conversion through a body-driven complementary pseudo-differential pair and a gate-driven current mirror. Thanks to the adoption of two fully differential stages with common mode feedback (CMFB) loop, the common-mode rejection ratio (CMRR) in typical conditions is greatly improved with respect to other ultra-low-voltage (ULV) bulk-driven OTAs. The OTA has been fabricated in a commercial 130nm CMOS process from STMicroelectronics. Its area is about 0.002 <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mm</i> <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , and power consumption is less than 35nW at the supply-voltage of 0.3V. With a load capacitance of 35pF, the OTA exhibits a DC gain and a unity-gain frequency of about 85dB and 10kHz, respectively.

Analysis and Design Procedures of CMOS OTAs Based on Settling Time

Analysis of generic single-pole, two-pole, and three-pole operational transconductance amplifiers (OTAs) is carried out based on settling time. The most important design metrics of the open-loop frequency response, such as the stability margins and the gain-bandwidth product (GBW) are related to the settling time of single-, two- and three-stage OTAs in closed-loop configuration, enabling to present a design procedure for each OTA based on the settling time specifications. Transistor-level design examples are provided for each case to validate the described settling-based design strategies.

A 0.25-V Three-stage State Feedback Bulk-driven OTA for Wide Range Load Applications

This article employs a nested state feedback compensation technique to a three-stage bulk-driven operational transconductance amplifier (OTA). The projected OTA circuit consists of a bulk-driven PMOS amplifier, gate-driven NMOS amplifier, and common source (CS) amplifier. The entire transistors in the amplifier core are configuredwith self-cascode transistor topology to increase its output impedance. All transistors are designed to operate in a weak inversion in order to dissipate less power. Cross-coupled transistor pair topology in the bulk-driven stage allows to improve the effective transconductance of OTA. The CS amplifier can drive a large load capacitor. The polarities and transconductance gains of feedback blocks are controlled appropriately to obtain the desired DC gain and bandwidth. The capacitor-less compensation strategy allows the fabrication of the OTA using the minimum area. Conventional bulk-driven miler OTA, Bulk-driven stage improved indirect-feedback OTA (BSIF OTA), Gate-driven stage added bulk-driven OTA (GSIF OTA), and proposed bulk-driven OTA topologies are designed and simulated using cadence spectre tool at 25 mV supply voltage in the 65nm CMOS process. These OTA circuits are analyzed and compared in terms of parameters like DC gain, unity-gain frequency, phase margin, CMRR, power dissipated, slew rate, and input referred noise.

High-Speed CMOS Three-Stage Amplifier Based on Feedback Attenuation

This paper presents a new and simple frequency compensation scheme for multistage CMOS operational transconductance amplifiers (OTAs). In this work, by applying a differential block frequency compensation (DBFC) technique to a compensation network of three-stage OTA, the dominant pole is drastically improved independent from the DC gain path. The DBFC introduces amplified signal directly to the second-stage output through the compensation capacitor. The signal injection increases operational frequency range while just a single and small value capacitor is used as the Miller capacitor, which leads to considering the proposed configuration as a low die area occupation and high-speed amplifier. The simulation results show with the same capacitive load and power dissipation the gain bandwidth (GBW) frequency can be improved considerably compared to conventional nested Miller compensation. The presented circuit is simulated in a 0.18[Formula: see text][Formula: see text]m CMOS technology with a 1.8[Formula: see text]V supply voltage. According to the results, the proposed circuit shows 102[Formula: see text]dB, 105[Formula: see text]MHz, and 343[Formula: see text][Formula: see text]W as the DC gain, GBW, and power consumption, respectively.

A gm/ID-Based Design Strategy for IoT and Ultra-Low-Power OTAs with Fast-Settling and Large Capacitive Loads

In this paper, a new strategy for the design of ultra-low-power CMOS operational transconductance amplifiers (OTAs), using the gm/ID approach, is proposed for the Internet-of-things (IoT) scenario. The strategy optimizes the speed/dissipation of the OTA in terms of settling time, including slew-rate effects. It was designed for large capacitive loads and for transistors biased in the sub-threshold region, but it is also suitable for low-capacitive loads or for transistors biased in the saturation region. To validate the proposed strategy, a well-known three-stage OTA was designed starting from capacitive load and settling time requirements. Simulations confirmed that the OTA satisfies the specifications (even under Monte Carlo analysis), thus proving the correctness of the proposed approach.

Design Trade-Offs in Common-Mode Feedback Implementations for Highly Linear Three-Stage Operational Transconductance Amplifiers

Fully differential amplifiers require the use of common-mode feedback (CMFB) circuits to properly set the amplifier’s operating point. Due to scaling trends in CMOS technology, modern amplifiers increasingly rely on cascading more than two stages to achieve sufficient gain. With multiple gain stages, different topologies for implementing CMFB are possible, whether using a single CMFB loop or multiple ones. However, the impact on performance of each CMFB approach has seldom been studied in the literature. The aim of this work is to guide the choice of the CMFB implementation topology evaluating performance in terms of stability, linearity, noise and common-mode rejection. We present a detailed theoretical analysis, comparing the relative performance of two CMFB configurations for 3-stage OTA topologies in an implementation-agnostic manner. Our analysis is then corroborated through a case study with full simulation results comparing the two topologies at the transistor level and confirming the theoretical intuition. An active-RC filter is used as an example of a high-linearity OTA application, highlighting a 6 dB improvement in P1dB in the multi-loop implementation with respect to the single-loop case.

Efficient Design Strategy for Optimizing the Settling Time in Three-Stage Amplifiers Including Small- and Large-Signal Behavior

An analytical criterion for the optimization of the small-signal settling time in three-stage amplifiers is carried out. The criterion is based on making equal the two exponential decays of the step response. Including slew-rate effects, a useful design strategy for the design of three-stage operational transconductance amplifier is provided. Extensive time-domain simulations on a transistor-level design in a 65-nm CMOS process confirm the validity of the proposed approach.

Design of Three-Stage OTA Based on Settling-Time Requirements Including Large and Small Signal Behavior

In this paper we are going to analyze the settling-time in single-, two- and three-stage amplifiers with the intent of deriving approximate but useful design equations that include the effects of the zeros and of the slew-rate limitations. The analysis is mainly devoted to the definition of an approach for the design of three-stage CMOS operational transconductance amplifiers from settling-time specifications. A design example is carried out to validate the proposed approach.

Design Techniques for High-Resolution Continuous-Time Delta–Sigma Converters With Low In-Band Noise Spectral Density

We present design considerations for CT $\!\Delta \!\Sigma $ Ms that attempt to achieve high resolution (16+ bits) over a wide bandwidth (>200 kHz), resulting in a low in-band noise spectral density. The main challenges in such designs are parasitic resistance in the reference path, inter-symbol interference (ISI) in the feedback-digital-to-analog converter (DAC) waveform, and flicker noise of the input operational transconductance amplifier (OTA). We introduce the virtual-ground-switched resistor DAC as a way to achieve low distortion by addressing parasitic resistance in the reference path and reducing the effects of ISI. Flicker noise is reduced by chopping the first stage of the input OTA. Chopping artifacts and clock jitter sensitivity are reduced by using a three-stage OTA and finite impulse response (FIR) feedback. These techniques are applied to the design of a 250 kHz bandwidth CT $\!\Delta \!\Sigma \text{M}$ targeting 108 dB signal-to-noise-and-distortion-ratio (SNDR) in a 180 nm CMOS process. The fabricated prototype, which operates at 32 MS/s, achieves 105.3/108.1 dB SNDR/signal-to-noise-ratio (SNR) and consumes 24 mW. The Schreier SNDR figure of merit (FoM) is 175.5 dB.

In-Depth Analysis of Pole-Zero Compensations in CMOS Operational Transconductance Amplifiers

In this paper we explore the effects of pole-zero compensation in the settling performance of operational transconductance amplifiers (OTAs). We carry out the analysis by exploiting a proficient technique that provides an in-depth comprehension of the time domain behavior from the contour plots of the Normalized Settling Time. Starting from the case of a single-pole amplifier, we show the conditions upon which the settling time is degraded by the slow time constant set by the pole-zero doublet. Then, we extend these results to two-pole amplifiers and provide a useful design equation. Design examples of a two-stage and a single-Miller three-stage OTAs confirm the validity of the proposed theoretical models.

Classification and Design Space Exploration of Low-Power Three-Stage Operational Transconductance Amplifier Architectures for Wide Load Ranges

Since operational transconductance amplifiers (OTAs) form the basic building blocks of many analog systems, the compensation of three-stage OTAs has attracted a lot of attention in the literature. Many different solutions to the stability problem of such OTAs have been proposed over the past 20 years, with each solution exhibiting different properties or targeting a different application. This work surveys a broad selection of previously reported architectures and proposes a novel classification scheme that exposes features common to seemingly different compensation architectures and serves as a guideline for which type of OTA is suitable for a given application. In addition, a novel figure of merit (FoM) is proposed to guide the designer in deciding which OTA architecture suits the tradeoffs specific to the application at hand. Theoretical discussions are further reinforced by transistor-level simulation results.

Improved reversed nested miller frequency compensation technique based on current comparator for three-stage amplifiers

This paper attempts to propose a newly modified method to improve the frequency compensation of three-stage operational trans-conductance amplifiers. In the topology of the new frequency compensation, a current comparator is placed on the feedback path, while the common node of Miller compensation capacitors, the feedforward path, is removed by eliminating the right-half plane zero. This tremendously improves the phase margin, stability, and gain band width product. Compared with other available frequency compensation methods, the newly proposed method manages to improve the figure of merits and lower power consumption while significantly decreasing the dimensions of capacitors in the compensation network. The superiority of the new method over other conventional methods for reversed nested Miller compensation has been examined by a three stage amplifier that has been designed and simulated through a 180 nm standard library CMOS. The results indicate that the new amplifier has achieved a power consumption of 285 µW, gain band width product of 14 MHz, and phase margin of 86° with 100 pF capacitance load at the supply voltage of 1.8 V.

High-Performance Three-Stage Single-Miller CMOS OTA With No Upper Limit of &lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;${C}_{L}$ &lt;/tex-math&gt; &lt;/inline-formula&gt;

This brief presents a low-power, area-efficient three-stage CMOS operational transconductance amplifier (OTA) suitable for very large capacitive loads, C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</sub> . A single Miller capacitor and an inverting current buffer embedded in the input stage are exploited to implement the frequency compensation network. An additional feed-forward path and a slew rate enhancer are also utilized to improve the large-signal transient response. Detailed small-signal analysis reveals that the proposed OTA does not exhibit an upper limit of drivable C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</sub> . The OTA is fabricated in a standard 0.35-μm technology and occupies 0.0027 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> of die area. Under 1.4-V supply and 6.36-μA quiescent current consumption, it provides a dc gain greater than 110 dB and is stable for any C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</sub> larger than 5 nF. Comparison with the state of the art shows remarkable improvement of both small- and large-signal performance.

Compensation strategy for high‐speed three‐stage switched‐capacitor amplifiers

In this Letter a new compensation strategy for a class of three-stage operational transconductance amplifiers is proposed. The proposed approach reduces the original third-order transfer function of the loop gain to that of a pure two-pole amplifier thus allowing the designer to use well-known and consolidated design rules. The approach, suitable for high-speed switched-capacitor circuits, is validated by means of intensive Monte Carlo simulations on a 65-nm three-stage CMOS amplifier.

Improved single-miller passive compensation network for three-stage CMOS OTAs

A compensation technique for low-power three-stage operational transconductance amplifiers is presented in this paper. The compensation network is made up of passive components and entails only one Miller capacitor. Design equations describing the amplifier behavior for different capacitive load conditions are reported along with three design examples for different capacitive loads, namely, 1 nF, 100 and 10 pF. The amplifier exhibits a gain-bandwidth product equal to 2.48, 6.74 and 7.66 MHz in the three cases while dissipating only 150, 150 and 57.5 μW from 2.5 V, respectively. Simulation results are found in good agreement with theoretical analysis and show an improvement in both small-signal and large-signal amplifier performance over many previously reported solutions.

High performance reversed nested Miller frequency compensation

This paper presents an enhanced technique to improve frequency compensation in three stages operational transconductance amplifiers (OTA). Based on the reversed nested Miller technique, it uses a current subtractor in the common node of the Miller capacitors, thus significantly improving the gain-band width product (GBW) while ensuring unconditional stability and removing the feed forward path. Also, compared to other existing frequency compensation techniques such as AC boosting compensation or active feedback frequency compensation, the proposed approach exhibits better figure of merits with less power consumption. The simulations of a three-stage OTA with 100 pF capacitive load exhibited 5 pF of total compensation capacitors, 63° phase margin and 4.75 MHz as GBW.

A three-stage class AB operational amplifier with enhanced slew rate for switched-capacitor circuits

In this paper, a three-stage class AB operational transconductance amplifier (OTA) with large slew rate is presented. The reversed nested Miller compensation technique is used to stabilize the proposed OTA, allowing the slew rate enhancement to be achieved by using class AB input and output stages. A flipped-voltage follower cell in the first stage in combination with a switched-capacitor level shifter in the last stage are utilized to implement the class AB operation. Circuit level simulation results are provided using HSPICE and a 90 nm CMOS technology which show 306 % enhancement in the large-signal FoM with approximately the same power dissipation compared to the class A OTA. The achieved settling time with 0.02 % accuracy for the proposed class AB and conventional class A OTAs are 7.5 and 15.3 ns, respectively.