Three-level Neutral Point Clamped Research Articles

A Modulation Strategy for a Three Level Inverter Synchronous Reluctance Motor (SynRM) Drive

In this paper, two modulation strategies called Mod-1 and Mod-2 are compared for a three-level diode neutral point-clamped (NPC) inverter synchronous reluctance machine (SynRM) drive. These modulation strategies do not operate at a fixed switching frequency. A new modulation strategy which operates at a fixed switching frequency is proposed called Mod3. The SynRM suffers from a poor power factor which makes it harder to archive capacitor voltage balancing for a three-level NPC inverter. These modulation strategies are of the nearest three vector (NTV) family. Mod-1 and Mod-3 choose certain vector states to achieve capacitor voltage balancing, whereas Mod-2 strategy makes use of the inverter vector state's dwell time. The parameters of interest are the torque ripple, the neutral point (NP) voltage ripple, the inverter efficiency, and the d-axis current ripple. Though lower torque ripple and better power quality are registered on Mod-2 strategy. Mod-1 strategy has 14% improvement in inverter efficiency at lower modulation index (m <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">i</sub> = 0.4). Mod-2 strategy has 11% more NP voltage ripple at a modulation index of 0.4. One of the disadvantages of Mod-1 strategy is the varying switching frequency. Mod-3 scheme produced higher inverter efficiency, better balancing of the capacitor voltages, and guaranteed fixed inverter switching frequency. The disadvantage with Mod-3 strategy is that it generated higher torque ripple, daxis current ripple, and current total harmonic distortion when compared to Mod-1 and Mod-2 at the same load conditions.

A Novel Neutral Point Voltage Control Strategy for Three-Level NPC APF Based on SVPWM

The unbalance of the neutral point voltage is an inherent problem of three-level neutral-point-clamped (NPC) Active Power Filter (APF); this paper analyzes the causes of unbalanced neutral point voltage and studies the reason of the unbalance of the neutral point voltage. A novel neutral point voltage control strategy using Space Vector Pulse Width Modulation (SVPWM) is proposed. The proposed strategy is based on the traditional SVPWM, by controlling the effect time of small vector, which can change the state of the midpoint voltage fluctuation, and the neutral point voltage can be maintained balance. The influence of the vector on neutral point balance is investigated in depth. Simulation results show the neutral point voltage balancing control strategy based on SPWM is effective.

Three-Level NPC Inverter Based SVM-VCIMD with Feed-forward Active PFC Rectifier for Enhanced AC Mains Power Quality

This paper presents a Scott-transformer-based power factor correction (PFC) rectifier for a three-level neutral-point-clamped (NPC) inverter-fed induction motor drive (IMD) for enhanced power quality at ac mains. Here, the Scott-transformer-based PFC rectifier is digitally controlled by a current feedforward control. The torque component of the stator current is added to the output of the dc-bus voltage proportional plus integral (PI) controller as a feedforward term, which enhances the dynamic performance of the dc-bus voltage regulation. The three-level NPC inverter is controlled by a space vector-modulated (SVM) indirect vector control scheme. The performance of the proposed dc-bus voltage loop with feedforward control is compared with the conventional one and found to offer faster response with less overshoot and undershoot. The proposed IMD system is simulated using MATLAB/Simulink and the same is validated experimentally. The proposed drive system is analyzed for a wide variation in reference speed and load torques demonstrating significant improvement in the performance indices.

Approach for torque ripple reduction for brushless DC motor based on three‐level neutral‐point‐clamped inverter with DC–DC converter

This study proposes a novel topology for reducing commutation torque ripple in a brushless DC motor (BLDCM) drive system using a three-level neutral-point-clamped (NPC) inverter combined with single-ended primary-inductor converter (SEPIC) converters. In the BLDCM, current ripples arise because of the influence of stator winding inductance, which generates torque ripples. The torque ripple that is generated in the commutation period prevents the use of BLDCM in high-precision servo drive systems. In this study, two-stage converters are proposed to reduce the torque ripple. The first stage consists of two SEPIC converters to obtain the desired commutation voltage according to motor speed. A dc-link voltage selection circuit is combined with the SEPIC converters to apply the optimised voltage during the commutation interval. To reduce the torque ripple further, a three-level NPC inverter is used to apply a half dc-link voltage across the motor winding and this effectively reduces the torque ripple. Experimental results show that the proposed topology is able to reduce commutation torque ripple significantly under both low-speed and high-speed operation.

A Three-Level DTC System Based on Virtual Space Vector Modulation for Bearingless Permanent Magnet Synchronous Motor

In This paper, a direct torque control (DTC) method for bearingless permanent magnet synchronous motor (BPMSM) based on three-level neutral-point clamped (NPC) inverter is described. Through the analysis of virtual space vector modulation, an independent control strategy is adopted into the suspension winding control and a flux linkage error vector SVM-DTC method supplied by three-level NPC inverter is introduced into the torque windings control. By using the proposed control strategy, the neutral-point voltage variation can be greatly limited and the voltage shifting can be eliminated. The results of simulation verify the feasibility of the control algorithm, the dv/dt of output voltage and the torque ripple are restrained effectively, satisfactory robustness and the good performance of the radial levitation can be achieved in a wide speed range by using the proposed method.

A Family of New Multiport Power-Sharing Converter Topologies for Large Grid-Connected Fuel Cells

This paper presents a family of new multiport power-sharing converter (PSC) topologies for utility-scale fuel cell (FC) power generation. The proposed system connects multiple FC sources to a medium-voltage grid via a single multilevel neutral point clamp (NPC) inverter interface with high-frequency isolation. High-voltage series-connected inputs are achieved, despite safely referencing each source to ground. Also, unique power-sharing technology decouples series-connected source currents and enables control of each FCs individual power level. Multidimensional modeling and analysis of the proposed system's PI- and PV-behavior is presented. Then, system topology and design considerations are discussed. Case study simulations show how this topology can operate four 250-kW FCs at separate power levels between 20% and 100%, while connecting to a single three-level NPC utility-interface. Correspondingly, a reduced-scale hardware prototype provides further proof of concept. Altogether, the proposed family of multiport PSC topologies realizes independent power control per source as well as increased output power, operational flexibility, thermal balancing, source availability, and cost effectiveness for utility FC power generation.

Loss Analysis of Low-Voltage TLNPC Step-Up Converters

Power losses in high-efficiency dc–dc step up converters based on the synchronous three-level neutral-point-clamped (TLNPC) configuration were investigated. TLNPC converters benefit from the reduced stress on components and from the non-insulated stacked-boost output stage to provide reduced power losses and large voltage gains. Several prototypes with increasing efficiency were produced and tested; voltage gains larger than $20\times$ were achieved by means of hard-switched prototypes with composite switches consisting of both low- $R_{ds(ON)}$ and high-speed MOSFETs. At lower voltage gains conversion efficiencies exceeding 98% were demonstrated. A thorough loss analysis is reported, extended to subtle power dissipation processes, which in high efficiency converters grow in relevance after weakening of the major loss mechanisms. The related model is proven capable to accurately predict circuit performance in a wide range of operating conditions.

A Generalized Loss Analysis Algorithm of Power Semiconductor Devices in Multilevel NPC Inverters

In this paper, a generalized power loss algorithm for multilevel neutral-point clamped (NPC) PWM inverters is presented, which is applicable to any level number of multilevel inverters. In the case of three-level inverters, the conduction loss depends on the MI (modulation index) and the PF (power factor), and the switching loss depends on a switching frequency, turn-on and turn-off energy. However, in the higher level of inverters than the three-level, the loss of semiconductor devices cannot be analyzed by conventional methods. The modulation depth should be considered in addition, to find the different conducting devices depending on the MI. In a case study, the power loss analysis for the three- and five-level NPC inverters has been performed with the proposed algorithm. The validity of the proposed algorithm is verified by simulation for the three-and five-level NPC inverters and experiment for three-level NPC inverter.

Space Vector Modulation for Three-Level NPC Converter With Neutral Point Voltage Balance and Switching Loss Reduction

This paper investigates the different control objectives, such as loss reduction, neutral point (NP) balance and noise reduction of the space vector modulation (SVM), for the three-level neutral point clamped (NPC) converter. A detailed loss model and simulation model is built for quantitative loss and NP voltage ripple analysis. An improved SVM method is proposed to reduce NP imbalance and switching loss/noise simultaneously. The coordinately selected small vectors consider both the NP charge and the pulse sequence so that the minimized NP ripple and switching events are guaranteed in one switching cycle. In addition, the switching events between switching cycles are also considered to reduce the total switching loss. This method ensures an evenly distributed device loss in each phase leg and also a constant system efficiency under different power factors. The control result for NP balance and loss reduction is verified by using both a simulation model and an experimental prototype on a 200-kVA three-level NPC converter hardware.

부트스트랩 회로를 적용한 3-레벨 NPC 인버터의 저속 운전을 위한 PWM 스위칭 전략

This paper proposes the pulse width modulation (PWM) control strategy for low-speed operation in the three-level neutral-point-clamped (NPC) inverters based on the bootstrap gate drive circuit. As a purpose of the cost reduction, several papers have paid attention to the bootstrap circuit applied to the three-level NPC inverter. However, the bootstrap gate driver IC cannot generate the gate signal to the IGBT for low-speed operation, because the bootstrap capacitor voltage decreases under the threshold level. For low-speed operation, the dipolar and partial-dipolar modulations can be the effective solution. However, these modulations have drawbacks in terms of the switching loss and THD. Therefore, this paper proposes the PWM control strategy to operate the inverter at low-speed and to minimize the switching loss and harmonics. The experimental results are presented to verify the validity on the proposed method.

A Study of Three-Level Neutral Point Clamped Inverter Topology

The three-level Neutral Point Clamped (NPC) inverter has become matured and widely used topology in high-power medium-voltage applications due to several advantages associated with it as compared to other available multilevel topologies. This paper presents a brief review on operation of three-level NPC inverter. Different modulation strategies used in NPC inverter is also discussed. The problem of neutral point voltage balancing with its solution is presented. Finally, the simulation and experimental results for three-level NPC inverter are given which validates the proper operation of this topology.

Unified power quality conditioner based on a three-level NPC inverter using fuzzy control techniques for all voltage disturbances compensation

This paper presents a novel and efficient control scheme for unified power quality conditioner (UPQC) based on three-level neutral point clamped (NPC) inverter using fuzzy logic techniques. The proposed UPQC is capable of mitigating source current harmonics and compensate all voltage disturbances such as voltage sags, swells, unbalances and harmonics. It is designed by the integration of series and shunt active filters (AFs) sharing a common DC bus capacitor. The DC voltage is maintained constant using proportional integral voltage controller. The synchronous reference frame (SRF) theory is used to get the reference signals for shunt active power filters (APFs) and the power reactive theory (p-q theory) for series APFs. The shunt and series APF reference signals derived from the control algorithm and sensed signals are injected in two controllers to generate switching signals. To improve the UPQC capability, fuzzy logic techniques are introduced to control the series APF. The performances of the proposed UPQC system are evaluated in terms of power factor correction, mitigation of voltage or current harmonics and all other voltage disturbances compensation using Matlab-Simulink software and SimPowerSystem toolbox. The simulation results illustrate the performance of the proposed UPQC at the common connection point of the nonlinear load to improve the power energy quality.

Modified Unipolar Carrier-Based PWM Strategy for Three-Level Neutral-Point-Clamped Voltage Source Inverters

This paper presents a simple modified unipolar carrier-based pulsewidth modulation (CB- PWM) strategy for the three-level neutral-point-clamped (NPC) voltage source inverter (VSI). Analytical expressions for the relationship between modulation reference signals and output voltages are derived. The proposed modulation technique for the three-level NPC VSI includes the maximum and minimum of the three-phase sinusoidal reference voltages with zero-sequence voltage injection concept. The proposed modified CB-PWM strategy incorporates a novel method that requires only of one triangular carrier wave for generate the gating pulses in three-level NPC VSI. It has the advantages of being simplifying the algorithm with no need of complex two/multi-carrier pulsewidth modulation or space vector modulation (SVM) and it's also simple to implement. The possibility of the proposed CB-PWM technique has been verified though computer simulation and experimental results.

Three-level NPC rectifier-based midpoint converter-fed SRM drive

This paper deals with a three-level Neutral Point Clamped (NPC) rectifier-based midpoint converter-fed Switched Reluctance Motor (SRM) drive. The three-level NPC rectifier for midpoint converter-fed SRM drive is used for improving power quality at AC mains and to balance the DC link capacitor voltages. The proposed three-level NPC rectifier is designed, modelled and its performance simulated using MATLAB/Simulink environment. The performance of proposed three-level NPC rectifier-based midpoint converter-fed SRM drive is compared with a six-pulse bridge converter-fed SRM drive to demonstrate its improved power quality.

Direct active and reactive power control of 3-level NPC-fed DFIG considering power ripple minimisation

Despite the advantages of three-level neutral point clamp (NPC) converters compared with standard voltage source inverters (VSIs), most of the direct power control (DPC) strategies for doubly fed induction generator (DFIG) reported in the literature, only utilise VSIs. As regards three-level NPC converter generates higher number of voltage vectors compared with standard VSIs, This paper presents a DPC strategy for DFIG using three-level NPC converters in which three-level NPC voltage vectors are employed to reduce large power ripples of conventional DPC. Therefore, a new optimised switching table is derived. Using this table, DFIG provides not only elaborate active and reactive powers which track their reference values very well, but also large power ripple is compensated. Also, because of ripple reduction, total harmonic distortion of rotor current, stator current, stator voltage and grid line-to-line voltage is reduced in proposed strategy compared with conventional DPC. Simulation results show the effectiveness of proposed method and have a reasonable correspondence with theoretical and mathematical analysis.

Switching Loss Analysis of 4.5-kV–5.5-kA IGCTs Within a 3L-ANPC Phase Leg Prototype

Three-level active neutral-point-clamped (NPC) (3L-ANPC) voltage-source converters (3L-ANPC-VSCs) enable additional switch states and commutations compared to the three-level NPC voltage-source converters (3L-NPC-VSCs). They are used to overcome one important disadvantage of the 3L-NPC-VSC, the unequal semiconductor loss distribution. With an accurate switching model (obtained directly from the measurements), it is possible to improve the junction temperature distribution among the power devices, increasing the 3L-ANPC-VSC output power and/or increasing the frequency and/or decreasing the derating of the converter. This paper presents the characterization of a 4.5-kV-5.5-kA integrated gate-commutated thyristor (IGCT) within a 3L-ANPC phase leg. A quantitative analysis of the switching losses using 5SHY55L4500 IGCTs and D1961SH45T press-pack diodes for a current range from 1 to 4.5 kA and junction temperatures between 25 ° C and 125 ° C is presented. The 3L-ANPC phase leg performs 32 different commutations. Each commutation exhibits different switching losses, as a result of the different commutation paths and their stray inductances. This switching energy range is presented and quantified. Finally, a simplified switching loss model considering the maximal switching losses in terms of the commutation current and the junction temperature is presented.

Passivity Based Hybrid Controller of Dual Euler Lagrange Model of Three-Level Three-Phase Neutral Point Clamped Voltage Source Rectifier

The PBHC (Passivity Based Hybrid Controller, PBHC) with damping injection and neutral point potential balance was based on a dual-EL (Euler Lagrange, EL) model of three-level three-phase dual load NPC (Neutral Point Clamped, NPC) VSR (Voltage Source Rectifier, VSR) in dq reference frame. The simulation results from Matlab/Simulink show that the proposed control strategy has excellent performances: at the AC side, the THD (Total Harmonious Distortion, THD) is less than 5%, the PF (Power Factor, PF) is higher than 98%; at the DC side, the output voltage is able to track the desired voltage quickly, the capacitors votages are equal.

Experimental Investigation of the Commutations of a 3L-ANPC Phase Leg Using 4.5-kV–5.5-kA IGCTs

Three-level active neutral-point-clamped (NPC) (ANPC) (3L-ANPC) voltage-source converters (3L-ANPC VSCs) offer three additional switch states and an increase of commutations by a factor of four, compared to the three-level NPC voltage-source converter. This paper presents, for the first time, a detailed analysis of all 3L-ANPC VSC commutations using high-power 5SHY55L4500 integrated gate-commutated thyristors. Starting with a description of the switching states and commutations, a new 3-kV 5-kA medium-voltage 3L-ANPC testbench is described. To verify the function of all commutations, this paper derives suitable switching sequences and analyzes the commutations and switching transients in detail for dc-link voltages of 2.13–2.43 kV and load currents of 3.95–4.36 kA. The experimental investigations show that, although the ANPC commutations substantially differ from NPC commutations, the ANPC commutations do not present critical operating conditions for the power semiconductors or the converters. Thus, all 32 ANPC commutations can be applied in a new medium-voltage converter realization.

A Carrier-Based PWM Strategy With the Offset Voltage Injection for Single-Phase Three-Level Neutral-Point-Clamped Converters

Single-phase three-level neutral point clamped (NPC) converters are widely applied in high-speed railway electrical traction drive systems. A significant problem related to the single-phase three-level NPC converters is the fluctuation of the neutral-point voltage. In this paper, a capacitor voltage balancing technique is proposed that injects an offset voltage into the sinusoidal modulating signals of the conventional carrier-based pulsewidth modulation (CBPWM) method. Furthermore, when the injected offset voltage is maximized, it cannot only balance the dc-link capacitors voltages, but also reduce switching losses. Theoretical analysis has shown that both methods can control the neutral point voltage effectively, but the neutral point voltage controller in the CBPWM with maximum offset voltage injection (CBPWM-MOVI) has a faster dynamic response. It was observed that the high-order harmonics frequencies of the line current are centered around the twice switching frequency in the CBPWM with the offset voltage injection (CBPWM-OVI) but are centered around the switching frequency in the CBPWM-MOVI. And also, the CBPWM-MOVI has switching commutations number at least 25% below that of the CBPWM-OVI in one modulating signal period. The performances of the two strategies were verified by simulation and experimental tests.

Space Vector Pulse Width Modulation for Three-Level NPC-VSI

This work addresses the design and experimental validation of a three-level Neutral-Point Clamped (NPC) inverter. A Space-Vector Modulation (SVM) algorithm which simplifies the space-vector diagram of a three-level inverter so that it can be used with a two-level inverter is developed. The dwell times are calculated on the simplification process in the same way as for a conventional two-level SVM method. Experimental results that validate the SVM algorithm developed to control the three-level NPC are presented. The SVM algorithm is programmed on a Freescale DSP56F8037 development system.