Three-level Neutral Point Clamped Inverter Research Articles

Three‐level saddle space vector pulse width modulation strategy based on two‐level space vector pulse width modulation for neutral‐point‐clamped three‐level inverters

This study proposes a three-level saddle space vector pulse width modulation (SVPWM) strategy based on two-level SVPWM (TBT_SAPWM) for neutral-point-clamped (NPC) three-level inverters. According to the analysis of the conventional three-level SVPWM strategy based on two-level SVPWM (CTBT_SVPWM) and the proposed TBT_SAPWM strategy, the modulation wave expressions of the two strategies are derived. Compared to the CTBT_SVPWM strategy, each main sector has its own independent area, and determining the main sectors or regions becomes easier with the proposed TBT_SAPWM strategy. Moreover, by optimising the switching states, the proposed TBT_SAPWM strategy makes on-state duration of one selected phase equal to that of the other selected phases in a switching cycle. Therefore, the three-phase modulation waves are saddle waves at the full range of fundamental wave modulation ratios. According to the experimental results in this study, the proposed TBT_SAPWM strategy has better performances in terms of the output harmonics and the neutral-point voltage ripple, compared to the CTBT_SVPWM strategy. The feasibility and effectiveness of the proposed strategy are verified by the experimental platform of an NPC three-level inverter based on the digital signal processor and complex programmable logic device.

Z-source T-type inverter for renewable energy systems with proportional resonant controller

In this study, a novel z-source T-type inverter for grid connected renewable energy system is proposed. The proposed system has ability of boosting voltage level without any additional DC–DC converter or transformer through the z-impedance network. The size of the system is reduced by eliminating DC–DC converter or step-up transformer requirement. Furthermore, an additional improvement in system efficiency is obtained by using T-type inverter structure which is more efficient than the conventional two-level inverter or three-level neutral point clamped inverter. Inverter output currents are controlled by the proportional resonant controller. MATLAB/Simulink simulations show that, fast dynamic response is obtained and steady state error is eliminated. In addition, the inverter output currents are in sinusoidal waveforms and synchronous with the grid frequency and phase. Besides, total harmonic distortion values of the inverter currents are measured as 2.41% which meets the international standards such as IEC61727 and IEEE1547.

Simple carrier‐based pulse‐width modulation scheme for three‐phase four‐wire neutral‐point‐clamped inverters with neutral‐point balancing

Neutral-point-clamped (NPC) three-level inverters can drive a combination of single- and three-phase loads or non-linear in a three-phase four-wire distribution system. However, an intrinsic problem with NPC three-level inverters is the fluctuation in the neutral-point (NP) voltage. In this study, a dynamic model of the NP voltage in a three-phase four-wire system will be analysed and developed. On the basis of this model, a simple carrier-based pulse-width modulation scheme for NP balancing is proposed. The proposed scheme decouples the NP voltage balancing from the necessity to control phase voltages, and controls the NP voltage without introducing zero-sequence voltage, thus the scheme can be applied to a general NPC voltage source inverter. The effectiveness of the proposed modulation scheme is verified by both simulation and experimental results. Finally, these results are compared with those reported in the literature.

Improved SVPWM vector selection approaches in OVM region to reduce common-mode voltage for three-level neutral point clamped inverter

Abstract Multilevel inverters (MLIs) have an essential portion in industrial applications. Eventhough there are various elementary developments in MLI and its pulse width modulation (PWM) control strategies, unfortunately those strategies are least bothered about the common mode voltage (CMV). The CMV appears at the neutral point of the motor’s star connected stator windings with respect to the source ground. This study proposes PWM schemes for three level diode clamped multilevel inverter (DC-MLI) which use an unpretentious switching sequence to determine the triangle for maximum output voltage and minimum CMV in entire modulation range. Here two types of approaches are proposed: (i) Partial elimination SVPWM (PE-SVPWM) and (ii) Full elimination (FE-SVPWM). The proposed strategies suggest switching selection by using the control degree of freedom available in SVPWM without affecting the inverter output voltage. As a result, CMV reduction and elimination with maximum output voltage and better THD is achieved. The proposed PWM approaches can be extended for any number of levels. The theoretical study, the MATLAB/Simulink software based computer simulation and Field Programmable Gate Array (FPGA) SPARTAN-III-3AN-XC3S400 processor supported hardware corroboration have shown the superiority of the proposed technique over the existing SVPWM schemes.

Variable Modulation Offset SPWM Control to Balance the Neutral-Point Voltage for Three-Level Inverters

In order to solve the neutral-point voltage unbalancing problem for three-level inverters, this paper proposes a method to balance the neutral-point voltage for three-level inverters with variable modulation wave offset sinusoidal pulse-width modulation (SPWM) control. Based on the mathematical expressions of neutral-point voltage unbalancing, the factors are studied, which affect the fluctuation of neutral-point voltage. Theoretically the mathematical expressions of the neutral-point voltage with the proposed method are derived, and the mathematical relationship between the fluctuation of neutral-point voltage and the adjusting offset of modulation wave is studied. This proposed method realizes controlling the neutral-point voltage balance by dynamically calculating the offset superimposed to the modulation wave based on SPWM (DCOSPWM). This DCOSPWM method is very simple, which has good steady-state performance and is easy for digital implementation. The simulation results verify the correctness of the theoretical analysis in this paper, and the feasibility and effectiveness of this method is verified by the experiments in the experimental platform of neutral point clamped three-level inverters based on digital signal processor (DSP)-complex programmable logic device (CPLD).

DC-Bus Voltage Range Extension in 1500 V Photovoltaic Inverters

Solar plants based on single-stage conversion photovoltaic (PV) inverters (no dc–dc boost stage) have gained popularity due to their simplicity, high efficiency, and cost effectiveness. Existing PV plants mostly operate under 1000 V and are subject to wide dc-bus voltage variations due to the effect of PV cell temperature and the voltage of the maximum power point (well below the open-circuit voltage). In particular, attractive locations, such as U.S.–Canada mountain and central regions, are subject to extreme PV surface temperatures, making the dc-bus voltage variation a challenge for single-stage solar inverters. This paper investigates 1500 V solar inverters with a focus on dc-bus voltage range extension capabilities through novel modulation and power devices utilization. A comparative analysis with the existing 1000 V solar inverters is presented to illustrate the significant advantages of the wide dc-bus range in 1500 V systems. A lower voltage limit in the dc-bus is achieved by employing a novel voltage reactive power dc-bus control strategy and modified modulation. A higher dc-bus peak voltage is obtained by maximizing the use of power switches. As a result, the 1500 V inverter dc-bus voltage is significantly extended to capture energy under extreme PV surface temperatures, greatly improving the limited range of traditional 1000 V inverters. Simulations and experimental results using a three-phase three-level neutral point-clamped inverter level are presented to validate the proposed dc-bus extension range, control strategy, and modulation scheme.

A Generalized Natural Balance Model and Balance Booster Filter Design for Three-Level Neutral-Point-Clamped Converters

Three-level neutral point clamped (NPC) inverters exhibit a natural balancing property that can self-regulate the intermediate neutral point voltage to half the overall dc-link voltage. However, the underlying mechanisms of this process are not well understood, its performance under various load conditions has not been properly explored, and the requirements and benefits of (RLC) balance booster filters to enhance the natural balancing response are not clear. This paper presents a generalized model of an NPC natural balancing process that allows these issues to be explored for various load structures and balance booster configurations (i.e., isolated wye, wye with a grounded star point, etc.). The model accurately predicts the dominant balancing time constant, identifies the harmonics that drive the balancing process, and can quantify the steady-state balance booster losses for a designed target natural balance response. Extensive simulation and experimental tests have been performed to validate the theoretical model.

Duty cycle‐based three‐level space‐vector pulse‐width modulation with overmodulation and neutral‐point balancing capabilities for three‐phase neutral‐point clamped inverters

In this study, a duty cycle-based space-vector pulse-width modulation (SVPWM) with overmodulation and capacitor voltage balance control for three-phase three-level neutral-point clamped (NPC) inverters is presented. On the basis of simple linear calculations of three-phase reference voltages, the proposed SVPWM can be derived, which avoids the trigonometry operation required by the conventional SVPWM. The modulation region can also be smoothly extended from the linear region to the overmodulation region through re-synthesising the three-phase reference voltages. This avoids the conventional non-linear function and look-up table. The neutral-point voltage balancing control is achieved via changing the duty cycle of the redundant small vectors in each switching period, which can be easily embedded into the proposed duty cycle-based SVPWM. The dynamic and steady-state performances of the proposed SVPWM are eventually verified by both simulation and experimental results.

A New DPWM Method to Suppress the Low Frequency Oscillation of the Neutral-Point Voltage for NPC Three-Level Inverters

In order to suppress the low frequency oscillation of the neutral-point voltage for three-level inverters, this paper proposes a new discontinuous pulse width modulation (DPWM) control method. The conventional sinusoidal pulse width modulation (SPWM) control has no effect on balancing the neutral-point voltage. Based on the basic control principle of DPWM, the relationship between the reference space voltage vector and the neutral-point current is analyzed. The proposed method suppresses the low frequency oscillation of the neutral-point voltage by keeping the switches of a certain phase no switching in one carrier cycle. So the operating time of the positive and negative small vectors is equal. Comparing with the conventional SPWM control method, the proposed DPWM control method suppresses the low frequency oscillation of the neutral-point voltage, decreases the output waveform harmonics, and increases both the output waveform quality and the system efficiency. An experiment has been realized by a neutral-point clamped (NPC) three-level inverter prototype based on STM32F407-CPLD. The experimental results verify the correctness of the theoretical analysis and the effectiveness of the proposed DPWM method.

Generalised look‐up table concept for direct torque control in induction drives with multilevel inverters

This study deals with direct torque control (DTC) of induction motor drives when a multilevel inverter is involved. The proposed control technique is finalised to reduce the amplitude of torque oscillations and to improve the motor dynamic response regardless of operating speed conditions while assuring a satisfactory input current distortion. This is achieved by using a special look-up-table built with a novel approach. The control itself is based on the application in each sampling interval of one or two voltage vectors suitably selected, in order to ensure low electromagnetic torque ripple in steady-state operations and fast dynamic behaviour in transient operations. In the algorithm, the converter voltage vectors selection is carried out by using a novel look-up table whose entry points are computed by means of a specialised relation, starting from the outputs of multilevel hysteresis controllers. The suggested method, suitable for a generic multilevel inverter, is detailed for a neutral point clamped three-level inverter. The proposed algorithm is validated by several numerical results, and compared with a DTC algorithm based on a traditional three-speed range look-up tables. Finally, some experimental results, obtained with a scale laboratory setup, are shown, discussed and compared with the numerical ones.

Discontinuous Space Vector Modulation Strategy for Three-Level Neutral Point Clamped Inverter

This paper presents a discontinuous space vector modulation (SVM) strategy for a three-level neutral point clamped (3L-NPC) inverter. The proposed scheme, calculation switching time of the 3L-NPC inverter is fully described. A mathematical analysis of the duty cycle is determined by utilizing the calculated switching time method. The main advantages of the proposed method are minimization of the number of commutations of switches and reduction of the switching losses. Simulated and calculation results are presented to verify the validity and effectiveness of the proposed modulation scheme.

Hybrid SHM–SHE Modulation Technique for a Four-Leg NPC Inverter With DC Capacitor Self-Voltage Balancing

In this paper, selective harmonic mitigation (SHM) and selective harmonic elimination (SHE) modulation techniques have been combined to produce appropriate pulses for a four-leg three-level neutral point clamped (NPC) inverter. In the proposed hybrid method, the SHM technique is applied to phase legs in order to mitigate non-triplen harmonics (fifth, seventh, . . .), and the fourth leg is controlled by the SHE principle to eliminate important low-order triplen harmonics (third, ninth, . . .) completely. In this context, it is demonstrated that using SHM instead of an SHE modulator for phase legs leads to a reduced vast range of harmonic orders in the NPC output voltage, significantly. Moreover, it is proved that the presented hybrid switching technique has the ability of dc-bus capacitor voltage balancing, inherently. Furthermore, analyses are performed to calculate the dc-bus capacitances accurately to show 5% voltage ripple acceptably. Simulation and experimental results validate a good dynamic performance of the proposed hybrid modulation technique in firing the NPC inverter switches to generate low-harmonic voltage waveforms supplying balanced and unbalanced loads while balancing the dc capacitor voltages in a four-wire network with small dc-link capacitors.

Harmonic analysis of DC capacitor current in sinusoidal and space-vector modulated neutral-point-clamped inverters

The voltage ripple and power loss in the DC-capacitor of a voltage source inverter depend on the harmonic currents flowing through the capacitor. This paper presents a double Fourier series based analysis of the harmonic contents of the DC capacitor current in a three-level neutral-point clamped (NPC) inverter, modulated with sine-triangle pulse-width modulation (SPWM) or conventional space vector pulse-width modulation (CSVPWM) schemes. The analytical results are validated experimentally on a 3-kVA three-level inverter prototype. The capacitor current in an NPC inverter has a periodicity of 120∘ at the fundamental or modulation frequency. Hence, this current contains third-harmonic and triplen-frequency components, apart from switching frequency components. The harmonic components vary with modulation index and power factor for both PWM schemes. The third harmonic current decreases with increase in modulation index and also decreases with increase in power factor in case of both PWM methods. In general, the third harmonic content is higher with SPWM than with CSVPWM at a given operating condition. Also, power loss and voltage ripple in the DC capacitor are estimated for both the schemes using the current harmonic spectrum and equivalent series resistance (ESR) of the capacitor.

Space Vecor Modulated Three Level NeutralPoint Clamped Inverter Using A Single ZSource Network

The Neutral Point Clamped (NPC) three-level inverter with Z-source network is a relatively recent converter topology that exhibits both voltage-buck and voltage-boost capability. This concept can be applied to all acto- ac, dc-to-dc, ac-to-dc, and dc-to-ac power conversion whether two-level or multilevel. However, multilevel inverters offer many benefits for higher power applications. Existing publications have shown the control of a Z-source flying capacitor inverter using the carrier-based modulation technique. This paper presents the control of a neutral point clamped three-level inverter with Z-source network using the space vector modulation technique. This gives a number of benefits in both implementation and harmonic performance which enables the operation of the Z-source arrangement to be optimized and implemented digitally without introducing any extra commutations.

Common-Mode Voltage and Vibration Mitigation of a Five-Phase Three-Level NPC Inverter-Fed Induction Motor Drive System

Common-mode (CM) voltage is one of the main reasons for the flow of bearing currents in induction motors (IM) that ultimately leads to the bearing failure and causes severe vibrations. For three-phase IM drives, many works have been reported either on the reduction or on the elimination of CM voltages that are generated due to pulse width modulation (PWM) action of the feeding power converters. However, for five-phase IM drives, very few studies are available with the perspective of the CM voltage elimination. Also, the effect of CM voltage on the mechanical vibrations of a five-phase IM has not been reported in the literature. Hence, in this paper, firstly, the modeling of CM current generated in the five-phase IM is done and its expression based on admittance transfer function is derived. Then the CM voltage is eliminated from a five-phase three-level neutral point clamped (NPC) voltage source inverter. The space vector pulse width modulation (SVPWM) technique is developed for the elimination of CM voltages. Only those switching states are selected which give zero CM voltage. The same selected switching states also give the balanced dc link capacitor voltages. Its effect is observed on the mechanical vibration of the motor and it is correlated with the CM current. The mechanical vibration is observed for both, with and without CM voltage elimination. Both the simulation and experimental results are given to validate the concept proposed.

IJIREEICE - Electrical, Electronics, Instrumentation and Control

Three-level Neutral-Point Clamped (NPC) inverter has become established to be a preferred topology for medium-power motor drive applications operating at several kilovolts. Still several research continues to find solutions to the problem of maintaining a stable neutral-point voltage in the converter. This paper presents the analysis and simulation of a three-level diode-clamped multilevel inverter, employing a sine-triangle modulator with addition of continuous variable offset voltage which regulates the midpoint potential of the dc bus. By maintaining dc-bus voltage balance, a significant reduction in the voltage distortion at the neutral point and also allowing a definitive reduction in the required dc bus capacitance. The effectiveness of the Pulse Width Modulation (PWM) strategies developed with continuous offset addition is demonstrated by MATLAB/SIMULINK based simulation presented in this paper.

Thermal analysis and efficiency of an induction motor driven by a fault-tolerant multilevel inverter using FEM

Purpose– The purpose of this paper is to present a comparative study of the thermal behavior and efficiency of an induction motor fed by a fault-tolerant Three-Level Neutral Point Clamped (3LNPC) inverter, under normal conditions as well as after a post-fault reconfiguration, following an open-circuit fault in the inverter. For this purpose, a Matlab/Simulink model and three-phase induction motor models using a finite element method (FEM) software were developed. Besides, some experimental tests were conducted for different values of the induction motor load torque and speed reference to validate the models.Design/methodology/approach– To assess the thermal behavior and efficiency of the motor, electromagnetic and thermal models using a FEM software were developed. The coupling with the inverter drive is accomplished through a developed model in Matlab/Simulink which also includes the control system. The simulation tests were performed for a healthy and faulty inverter at different operating points of the three-phase induction motor. To validate the FEM models some experimental tests were performed.Findings– When the inverter operates in reconfigured mode the motor losses are higher and consequently temperature is higher and the motor efficiency is lower. The developed models are an alternative to a more detailed study of the motor when fed by a 3LNPC inverter and consequent optimization of the control system.Originality/value– With the developed tools, a better understanding of the motor behavior and performance is gained, allowing to forecast scenarios and optimize fault-tolerant control strategies for the drive.

Pulse delay control for capacitor voltage balancing in a three‐level boost neutral point clamped inverter

The cross regulation effect in multi-output DC/DC converters offers a reliable support for the grid integration of multilevel inverters by balancing the capacitor voltages. The capacitor voltage balancing by single input dual output boost converter is often realised by conventional three-level switching scheme. The three-level operation benefits lower inductor ripple current, but it limits the maximum possible compensation voltages. In this study, the entire operating modes of the boost converter is presented and all the possible cases which contribute to the voltage balancing are employed for balancing the capacitor voltages in a three-level neutral point clamped inverter. A proportional-integral controller based duty ratio control and pulse delay control are used for DC link voltage regulation and capacitor voltage balancing. Since the classical state-space averaging technique is not suitable for SIDO converters, inductor current ripple averaging technique is utilised for controller design. The circuit simulation is performed in Matlab/Simulink. The digital controller is realised using the Virtex-5FPGA in Labview/CompactRIO module. Both simulation and experimental results are presented to validate the controller performance.

Direct Torque Control of Induction Motor Using Three-Level Neutral Point Clamped Inverter

The direct torque control strategy of squirrel-cage induction motor using three-level neutral point clamped inverter is presented. The strategy used for controlling the torque of induction motor includes the change in applied voltage to the squirrel-cage induction motor .The variable voltage is provided with the help of look up table to the inverter. It is observed that the torque ripples are much in three-level inverter as compared to three level ineverter. This is because of the high dv/dt ratio of the output voltage of inverter. The current ripple produces torque ripples in steady state. The performance of motor in transient state and steady state are shown. The parameters of machine are given and the controlling strategy is performed using MATLAB/Simulink software. The control strategy is simulated on a 5 hp SQIM drive with three-level insulated-gate bipolar transistor (IGBT) inverter in MATLAB/Simulink software.

Single phase three‐level neutral‐point‐clamped quasi‐Z‐source inverter

This study presents a novel three-level neutral-point-clamped quasi-Z-source inverter in the single-stage buck-boost multilevel inverter family. The topology was derived by combining the properties of the quasi-Z-source network with those of a three-level neutral point clamped inverter. It features such advantages as low voltage stress of the switches, single-stage buck-boost power conversion, continuous input current, short-circuit withstandability and low total harmonic distortion of the output voltage and current. The authors present a steady state analysis of the topology along with a special modulation technique to distribute shoot-through states during the whole fundamental period. Component design guidelines for a single-phase case study system are described. All the findings have been confirmed by simulations and experiments. The topology could be recommended for applications requiring continuous input current, high input voltage gain and enhanced quality of the output voltage.