Three-level Neutral Point Clamped Inverter Research Articles

A Carrier-based PWM Control Strategy for Three-level NPC Inverter Based on Bootstrap Gate Drive Circuit

This paper proposes a pulsewidth modulation (PWM) control strategy for the efficient operation of the three-phase three-level neutral-point-clamped (NPC) inverters based on a bootstrap gate drive circuit. The bootstrap circuit used in the three-level NPC inverter has advantages in terms of the cost reduction and the compact circuit design. However, the bootstrap circuit has a drawback due to the low gate-emitter voltage during the low-frequency and variable load condition of the inverter system. This problem leads to lower efficiency and reliability of the inverter. Therefore, this paper analyzes the causes of the voltage decrease in bootstrap capacitors and proposes PWM control strategy to increase the voltage level of bootstrap capacitors for the efficient operation of the inverter. The proposed PWM control strategy provides efficient and stable operation of the inverter system by selecting the unipolar, dipolar, or partial-dipolar modulation methods according to the fundamental output frequency and load current of the inverter system. Furthermore, this paper proposes a design method of the size of bootstrap capacitors for the optimal circuit design. The effectiveness of the proposed PWM control strategy is verified using the experimental results.

Torque Ripple Reduction and Flux-Droop Minimization of DTC With Improved Interleaving CSFTC of IM Fed by Three-Level NPC Inverter

Direct torque control (DTC) is known for its fast control in AC motor drives due to its simple control structure that directly controls the torque without the need for modulation blocks or frame transformations. However, when used in induction motor (IM) drives it has three main drawbacks: large torque ripples, variable switching frequency, and sector flux-droop at the low-speed region due to the employment of the torque hysteresis controller (THC). Torque ripple minimization can be achieved in DTC drives by replacing the originally proposed two-level inverter with a three-level neutral-point clamped (3L-NPC) inverter. Nevertheless, the switching frequency remains variable and low, which produces an elevated torque ripple and asymmetrical switching signals for the inverter. In addition, sector flux-droop resulting from driving the IM at the low-speed region produces a high current distortion that consequently eliminates the robustness of DTC. To alleviate these problems, an interleaving constant switching frequency torque controller-based DTC (CSFTC-DTC) was implemented. It improves the operation of the IM at the low-speed region by increasing the duty-cycle of the applied active voltage vector and reducing the duration of the applied zero vectors. Although the conventional CSFTC-DTC regulates the stator flux of the IM at the low-speed region and minimizes the total harmonic distortion (THD) of the stator current, it produces a high torque ripple-one of the main disadvantages of classical DTC. In this paper, an interleaving CSFTC-DTC is proposed to subdivide the duty cycle of the applied vectors of the 3L-NPC inverter to limit the influence of the large duty-cycle of the applied vectors on flux-regulation and torque ripples. The simulation and experimental results presented validate the effectiveness of the proposed method over the conventional method.

Application of Barycentric Coordinates in Space Vector PWM Computations

This paper proposes the use of barycentric coordinates in the development and implementation of space-vector pulse-width modulation (SVPWM) methods, especially for inverters with deformed space-vector diagrams. The proposed approach is capable of explicit calculation of vector duty cycles, independent of whether they assume ideal positions or are displaced due to the DC-link voltage imbalance. The use of barycentric coordinates also permits a well-defined and universal approach to the problem of identifying the region in which the reference vector is located. It completely avoids the use of angles, trigonometric functions, and inverse trigonometric functions and is chiefly based on matrix operations which are well suited for digital signal processor implementation. The proposed approach is exposed and validated for the special case of three-level neutral-point clamped (NPC) inverter controlled by a discontinuous space-vector PWM.

An Improved Fault-Tolerant Control Strategy for High-Power ANPC Three-Level Inverter Under Short-Circuit Fault of Power Devices

The high-power active neutral-point clamped (ANPC) three-level inverter has high-reliability requirements for the system operation, and short-circuit fault, very common, and serious problem in the operation will affect the operation stability. To solve this problem, the fault current path analyses under a single device and multi-device short-circuit fault were carried out first in this paper. Second, on the basis of the different fault condition, an improved fault-tolerant control strategy was proposed. This strategy maintains the three-level operation under a single device short-circuit fault, and under multiple device, fault operates with low withstanding voltage. Finally, the experiment was made on a 1 MW ANPC three-level platform, which proved the effectiveness of the proposed method.

An Overall Minimized Switching Loss Discontinuous PWM Strategy for Neutral Point Clamped Three Level Inverters

Aim at reducing switching loss (SL) of neutral-point clamped three-level inverter (NPC TLI) as much as possible, a novel SL minimized discontinuous pulse width modulation (SLMDPWM) strategy is proposed in this paper. The core of SLMDPWM is that the specific maximum or middle phase current is clamped to positive bus, NP or negative bus according to modulation index and power factor angle. The realization of SLMDPWM based on carrier-based PWM (CBPWM) is revealed to simplify the calculation process. The performance characteristics of SLMDPWM and DPWM I-IV in term of the output voltage, SL and NP voltage ripple are compared by simulation and experimental results, and conclusion can be acquired that the SL of SLMDPWM is reduced significantly.

Influence of Digital Delay on the Zero-Sequence Voltage Injection Neutral-Point Potential Balance Algorithm for Three-Level NPC Inverters and Its Compensation Method

Three-level neutral-point-clamped (NPC) inverters need to ensure the balance of the neutral-point (NP) potential during operation. The zero-sequence voltage injection balance algorithms based on the carrier-based pulse width modulation (CBPWM) have been proposed in many papers and proved to be effective in controlling the NP potential. In industrial applications, the algorithms are mostly implemented by digital controllers, which have inherent computation digital delay. However, there is little attention to how the digital delay influences the balance algorithms. In this paper, the influence of the digital delay on the zero-sequence voltage injection balance algorithm has been studied in detail. It is found that the digital delay causes a fluctuation of the NP potential. The frequency of the fluctuation is 1/6 control frequency, and the amplitude of the fluctuation is related to the control frequency, the modulation index, the output current, and the dc-side capacitance. Furthermore, in order to eliminate the NP potential fluctuation caused by the digital delay, a digital delay compensation method is proposed in this paper. The correctness of the theoretical analysis and the effectiveness of the compensation method have been verified by the simulation and experiment results.

Capacitors Voltage Switching Ripple in Three-Phase Three-Level Neutral Point Clamped Inverters with Self-Balancing Carrier-Based Modulation

This paper provides a comprehensive analysis of the capacitors voltage switching ripple for three-phase three-level neutral point clamped (NPC) inverter topologies. The voltage ripple amplitudes of the two dc-link capacitors are theoretically estimated as a function of both amplitude and phase angle of output current and the inverter modulation index. In particular, peak-to-peak distribution and maximum amplitudes of the capacitor voltage switching ripple over the fundamental period are obtained. A comparison is made considering different carrier-based pulse-width modulations in the case of almost all sinusoidal load currents, representing either grid connection or passive load with a negligible current ripple. Based on the voltage switching ripple requirements of capacitors, a simple and effective original equation for a preliminary sizing of the capacitors has been proposed. Numerical simulations and experimental tests have been carried out in order to verify the analytical developments.

Novel Discontinuous PWM Method for a Single-Phase Three-Level Neutral Point Clamped Inverter With Efficiency Improvement and Harmonic Reduction

This paper proposes a novel discontinuous pulse-width modulation (DPWM) method to reduce the current harmonics and improve the system efficiency for a single-phase three-level neutral-point clamped inverter. In single-phase inverters, the unipolar pulse-width modulation (UP-PWM) method is commonly used. However, this method has the disadvantage of power losses due to numerous switching operations. Conventional DPWM methods reduce the power losses and improve efficiency but increase the current total harmonic distortion (THD). To overcome these weaknesses, this paper proposes a hybrid DPWM switching method combining two PWM methods: the UP-PWM method and the conventional DPWM method called one-pole clamped PWM method. Since the proposed DPWM method offers all the advantages of both PWM methods, the optimal performance—with regard to the power losses and current THD—is obtained. The combination of two PWM methods is investigated by analyzing the power losses and current THD. Based on the analysis, the process determining the optimal operating condition is introduced. The effectiveness of the proposed DPWM method is demonstrated through simulations and experiments.

Long-Horizon Direct Model Predictive Control: Modified Sphere Decoding for Transient Operation

In this paper, we present modifications to the sphere decoder initially introduced in the work of Geyer and Quevedo and modified in the work of Karamanakos et al. that significantly reduce the computation times during transients. The relative position of the unconstrained solution of the integer quadratic program underlying model predictive control (MPC) with respect to the convex hull of the (truncated) lattice of integer points is examined. If it is found that the unconstrained solution does not lie within the convex hull—a phenomenon that is observed mostly during transients—then a projection is performed onto the convex hull. By doing so, a new sphere that guarantees feasibility and includes a significant smaller number of candidate solutions is computed. This reduces the computation time by up to three orders of magnitude when solving the optimization problem at hand. Nonetheless, the reduction of the computational burden comes at a cost of (mild) suboptimal results. The effectiveness of the proposed algorithm is tested with a variable speed drive system consisting of a three-level neutral point clamped voltage source inverter and a medium-voltage induction machine. Based on the presented results, the sphere decoding algorithm with the proposed refinements maintains the very fast transient responses inherent to direct MPC. Moreover, it is observed that the occasional implementation of suboptimal solutions does not lead to a deterioration of the system performance.

Multi‐pulse AC–DC converter fed SVM controlled NPC inverter based VCIMD

A multi-pulse AC-DC converter fed space vector modulation (SVM) controlled neutral point clamped (NPC) inverter based vector control induction motor drive (VCIMD) is proposed here for medium power rating applications. To improve the power quality at supply side, a 12-pulse AC-DC converter is used and to meet the IEEE-519 standard, a high-pass filter is also used along with it. A three-level NPC inverter is utilised on the motor side to enhance the required performances of an induction motor drive (IMD). A modified SVM strategy is proposed to balance the capacitor voltages of the NPC inverter and to switch this inverter at very low switching frequency. The neutral point voltage balancing is achieved by the time adjustment between positive and negative small vectors. The model of proposed IMD is developed using the Simulink/MATLAB platform, and simulated response is validated with test results on a developed prototype in the laboratory to demonstrate its usefulness for medium power applications.

A Novel Phase Current Reconstruction Method for a Three-Level Neutral Point Clamped Inverter (NPCI) with a Neutral Shunt Resistor

This paper presents three phase current reconstruction methods for a three-level neutral point clamped inverter (NPCI) by measuring the voltage of a shunt resistor placed in the neutral point of the inverter. In order to accurately acquire the phase currents from the shunt resister, the dwell time of the active voltage vectors need to exceed the minimum time. On the other hand, if the time of active voltage is shorter than the minimum time, the current measurement becomes impossible. In this paper, unmeasurable regions for current are classified into three areas. Area 1 is a region in which both phase currents can be measure. Therefore, it is not necessary to restore the current. In Area 2, only one phase current can be measured. Thus, an estimation or restoration method is needed to measure another phase current. In this paper, the current estimation method using an electrical model of the motor is proposed. Area 3 is the region in which both phase currents can not be measured. In this case, it is necessary to move the voltage vector to the current measurable area by injecting the voltage. In this paper, Area 3 is divided into 36 sectors to inject optimal voltage. The proposed methods have the advantages of high current measurement accuracy and low THD (total harmonic distortion). The effectiveness of the proposed methods are verified through experimental results.

Selective finite‐states model predictive control of grid interfaced three‐level neutral point clamped photovoltaic inverter for inherent capacitor voltage balancing

A selective finite states model predictive control is proposed for a grid interfaced three-level neutral point clamped solar photovoltaic inverter. The proposed control approach eliminates the weighting factor selection for dc-link capacitor voltage balancing and reduces the computational burden for real-time implementation. The switching states required for the prediction and objective function optimisation are selected based on the position of reference voltage vector in the space vector plane, inverter current directions and the charge status of the dc-link capacitors. As a result, the selection of optimal switching state is fast, easy to implement and eliminates the selection of weighting factor for capacitor voltage balancing. The feasibility of the proposed control approach is verified through simulation and laboratory-scale experimentation. The results confirm that the proposed method attains the inherent dc-link capacitor voltage balance and also retains the dynamic and steady-state current tracking in comparison with the classical finite control-set model predictive control.

Control of Neutral-Point Voltage in Three-Phase Four-Wire Three-Level NPC Inverter Based on the Disassembly of Zero Level

It is important to maintain the neutral-point (NP) voltage balanced for the three-phase four-wire three-level neutral-point clamped (NPC) inverter. In this paper, after detailed discussion, a mathematical model of the neutral-point voltage are derived. Then a novel control strategy is proposed based on the disassembly of zero level (O Level) to maintain the neutral-point potential. A variable named neutral-point control margin (NPCM) is defined to represent the disassembly margin of each phase. The zero level of one of the three phase is disassembled quantitatively after calculation. Furthermore, the neutral-point voltage can keep balanced while the average output voltage remains unchanged. The proposed control strategy is verified by simulation and experiments.

An Improved PWM Scheme for Three-Level Inverter Extending Operation Into Overmodulation Region With Neutral-Point Voltage Balancing for Full Power-Factor Range

This paper presents a carrier-based pulsewidth modulation (PWM) strategy for a three-level neutral-point-clamped (NPC) inverter that exhibits good control over dc-link capacitor voltages and mitigates low-frequency oscillations in the neutral point (NP) for operation extending into overmodulation region. The overmodulation signals are derived in a generalized way by first determining a bias signal from the zero-sequence injected signals, and then adding the bias with the modulating signals. Such an approach enables seamless transition across different modulation modes covering full modulation depth. It is shown that the incorporation of a signal compression factor generates a nonzero duty ratio for NP connectivity in every PWM cycle in overmodulation region, and thereby creates a room for addition of unbalance compensation signal which can be used to generate neutral current to mitigate existing unbalance in capacitor voltages in the overmodulation region. The compensating signals are in phase with the load currents exhibiting linearity in compensation for full power-factor range. A thorough investigation of the PWM algorithm for operation in both undermodulation and overmodulation with NP voltage regulation is carried out. The performances of the proposed scheme are evaluated through extensive simulation and validated by experiments using a three-level NPC inverter prototype with induction motor load.

Fault Detection Methods for Three-Level NPC Inverter Based on DC-Bus Electromagnetic Signatures

This paper proposes two new open-circuit fault detection methods suitable for the diagnosis of power electronics converters. The faulty semiconductor devices are identified using conducted and radiated electromagnetic signatures of the dc bus through nonintrusive measurements. The first method uses a low-cost electromagnetic interference filter to collect the common-mode emissions signature. The second one utilizes an external antenna to collect the emitted near-field signature. Both methods are tested on a three-level neutral point clamped inverter (NPC) inverter with the aim to identify the clamping diodes open-circuit faults. Indeed, each open-circuit fault affects the common-mode emission signature in the time-domain, while the fast Fourier transform of the emitted near-field showed substantial reduction of spectrum amplitude at a specific radio frequency range and the appearance of a new spectral rail. The effectiveness of these two methods has been tested through numerical simulations and validated by experimental results which confirmed its high performance in detecting single as well as multiple open-circuit faults for three-level NPC inverter.

A new topology with the repetitive controller of a reduced switch seven-level cascaded inverter for a solar PV-battery based microgrid

In this manuscript, a repetitive control approach for the reduced switch seven-level cascaded inverter (RSCI) is proposed for active and reactive power control with enhanced power quality standard for a solar PV-battery based microgrid. The proposed repetitive control approach is applied for the RSCI and the performance is tested on a grid-connected microgrid integrated with photovoltaic (PV) and battery energy sources. To capture maximum power, a control strategy based on incremental conductance method (I&C) is adapted for optimal maximum power point tracking (MPPT) operation. The battery energy storage system in both charging and discharging mode of operation is controlled by repetitive controlled based RSCI as a support to PV for better power management. To show the feasibility and robustness in operation of the proposed approach, a variable irradiance input to the PV unit is considered. To justify the practical applicability of the proposed approach and to satisfy IEEE-1547 power quality constraints, a LCL filter is selected to minimize the harmonic distortion in the grid side current levels. The improved performance of the proposed technique is justified by presenting comparative simulation results with respect to three-level neutral point clamped inverter (NPC) with proportional integral (PI) controller. By using MATLAB software, the validity of the proposed approach is studied by simulation under constant and varying irradiance condition.

Optimisation of current harmonics for three‐level VSI based induction motor drive suitable for traction application

A method for minimisation of current harmonics spectrum for asynchronous traction motor fed from three-level neutral point clamped voltage-source inverter is described in this study. A selective harmonic elimination and mitigation-based algorithm using particle swarm optimisation has been utilised. Since the load is an induction motor suitable for traction application, a modified objective function with constraint of individual current harmonics has been proposed in this study to obtain improved harmonic elimination and control with low switching frequency. The proposed method has been compared with conventional technique considering only torque spectrum as objective function. Moreover, a suitable formulation for loss calculation has been proposed to optimise both the motor losses and torque harmonics. Suitable simulations along with experiments are performed with a practical induction motor of cage type to justify the proposed method.

Design and Control of Small DC-Link Capacitor-Based Three-Level Inverter with Neutral-Point Voltage Balancing

This paper presents a method to improve the quality of input-output currents in a three-level neutral-point clamped (NPC) inverter with small direct current-link (DC-link) capacitor systems. The inverter systems with the small DC-link capacitors have several advantages in terms of cost, volume, life-time, and reliability when compared to inverters that use large DC-link capacitors. However, there are problems with respect to the deterioration of the input current quality and a severe ripple of neutral-point voltage (NPV), which can cause an aggravated output current. To mitigate these issues, an additional circuit is applied for the input current shaping and a compensation algorithm is applied to reduce the ripple voltage of NPV. The effectiveness of the proposed design and control method is verified with various simulation and experimental results.

Bidirectional Power Converter for Solar Grid Interface Applications: An Experimental Investigation

Switching control of a current controlled grid integrated inverter using three-level neutral point clamped (NPC) inverter is investigated in this paper. The proposed scheme uses both the hysteresis current control (HCC) and carrier based switching schemes to improve the low switching frequency operation. To overcome the problems associated with current control techniques a simple carrier injection method is proposed in this paper. This current control method uses a high frequency triangular carrier injected to the current tracking error. The triangular carriers are chosen with minute amplitude comparable with current tracking error. This will enhance the switching frequency and stabilize the NPC inverter. This will ensure constant switching frequency operation of the grid interface inverter (GII). A comprehensive modeling of GII is carried out to study the stability of the system. A comparative study of switching frequency stabilization is presented. To verify the proposed current controller a prototype setup is developed. Analytical studies with experimental results of the proposed techniques are presented to show the superiority of results.

Research on the Neutral-Point Voltage Balance for NPC Three-Level Inverters under Non-Ideal Grid Conditions

In order to solve the neutral-point voltage unbalancing problem for neutral-point clamped (NPC) three-level inverters under non-ideal grid conditions, a novel zero-sequence component injection method for modulation signals was proposed in this paper. Based on the mathematical expressions of neutral-point voltage unbalancing, the fluctuation of the neutral-point voltage under different grid conditions was studied. The proposed method dynamically calculates the zero-sequence component for modulation signals by region selections based on sinusoidal pulse width modulation (DCR-SPWM). Under non-ideal grid conditions, this DCR-SPWM method can control the neutral-point voltage balance for NPC three-level inverters with different grid and output power conditions, and improves the grid current quality. The simulation results verified the correctness of the theoretical analysis in this paper, and the feasibility and effectiveness of this method were verified by the experiments in the experimental platform of the NPC three-level grid-connected inverter based on DSP-CPLD controllers.