Three-dimensional Integrated Circuit Applications Research Articles

Fabrication of Low Cost and Low Temperature Poly-Silicon Nanowire Sensor Arrays for Monolithic Three-Dimensional Integrated Circuits Applications.

In this paper, the poly-Si nanowire (NW) field-effect transistor (FET) sensor arrays were fabricated by adopting low-temperature annealing (600 °C/30 s) and feasible spacer image transfer (SIT) processes for future monolithic three-dimensional integrated circuits (3D-ICs) applications. Compared with other fabrication methods of poly-Si NW sensors, the SIT process exhibits the characteristics of highly uniform poly-Si NW arrays with well-controlled morphology (about 25 nm in width and 35 nm in length). Conventional metal silicide and implantation techniques were introduced to reduce the parasitic resistance of source and drain (SD) and improve the conductivity. Therefore, the obtained sensors exhibit >106 switching ratios and 965 mV/dec subthreshold swing (SS), which exhibits similar results compared with that of SOI Si NW sensors. However, the poly-Si NW FET sensors show the Vth shift as high as about 178 ± 1 mV/pH, which is five times larger than that of the SOI Si NW sensors. The fabricated poly-Si NW sensors with 600 °C/30 s processing temperature and good device performance provide feasibility for future monolithic three-dimensional integrated circuit (3D-IC) applications.

Gate capacitance effect on P-type tunnel thin-film transistor with TiN/HfZrO2 gate stack

In this work, the polycrystalline-silicon (poly-Si) tunnel field-effect thin-film transistors (TFETs) with TiN/HfZrO2 gate stack materials are demonstrated to exhibit low threshold voltage ~ –1.218 V, subthreshold swing (SS) ~ 0.311 V/decade and channel length insensitive transfer characteristics. Conventional carrier transport mechanism of poly-Si thin-film transistors (TFTs) is the thermionic emission with scattering effect, which is deduced as the drift-diffusion transport model with additional trap state induced energy barrier height, resulting in the stronger channel length dependence effect. For the poly-Si TFETs, the carrier transport mechanism is the interband tunneling, including band-to-band tunneling and trap-assisted tunneling, which is less affected by the channel length. The different carrier transport mechanisms of poly-Si TFETs and TFTs would lead to different gate dielectric thickness effect. When the thickness of gate dielectric HfZrO2 is reduced from 18 to 10 nm to increase the gate capacitance density, the SS and on-state current of poly-Si TFETs exhibit much higher improvement than them of poly-Si TFTs. It indicates that the high gate capacitance density is a key parameter for the development of poly-Si TFETs to replace the conventional poly-Si TFTs in three-dimensional integrated circuit applications.

Volume Shrinkage Induced by Interfacial Reaction in Micro-Ni/Sn/Ni Joints

Experiments are carried out to measure the volume shrinkage during solid-state reaction in micro-joints for three-dimensional integrated circuit applications. Surface profilometer is employed to measure the volume shrinkage for the reaction between Ni and Sn. The shrinkage is correlated with the microstructural evolution during the reaction. It is found that the volume shrinkage is released through both joint height reduction and void formation. The resulting internal stress and the void formation might post potential reliability issues.

Experimental characterization and modeling of the mechanical properties of Cu–Cu thermocompression bonds for three-dimensional integrated circuits

An analytical model is proposed which relates the bonding temperature, pressure and duration with the integrity of metal–metal thermocompression bonds. Unlike previous models, this approach takes into account the pressure-dependent time evolution of the thermocompression bond formation. The model allows calculation of the true contact area of rough surfaces, based on a creep-dominated plastic deformation. Verification of the model was provided through experiments on Cu–Cu thermocompression bonds of electroplated Cu on diced silicon wafers with chemically/mechanically polished surfaces. The samples were bonded at a range of temperatures, pressures and times. Shear strength measurements were used to characterize the effects of the bonding parameters on the interface bond strength. Calculated true contact area and bond shear strength can be related by a single proportionality factor. The model can be used to predict the thermocompression bond quality for given bonding parameters and process optimization for reliable bonds, thus assisting in the adoption of the Cu thermocompression bond process in three-dimensional integrated circuit applications.

Palladium-Induced Lateral Crystallization of Amorphous-Germanium Thin Film on Insulating Substrate

In this article, metal (palladium, Pd)-induced lateral crystallization (MILC) of amorphous-germanium (α-Ge) films prepared by room-temperature sputtering on an insulating material (SiO 2 ) is observed and investigated using micro-Raman microscopy and transmission electron microscopy. The planar α-Ge thin films were annealed at 300, 350, and 400°C in a N 2 ambient. The MILC phenomenon is not observed for the samples annealed at 300°C for 2 h, while the MILC phenomenon is observed for α-Ge films annealed at 350 and 400°C for 2 h with a lateral growth rate of ∼ 1.1 and 1.3 μm/h, respectively. A poly-Ge film with a 400°C annealing temperature exhibits a smaller full width at half-maximum and a higher intensity of the sharp c-Ge peak than that annealed at 350°C, which can be the promising material candidate for Si-based three-dimensional integrated circuit applications.

Process development and bonding quality investigations of silicon layer stacking based on copper wafer bonding

Process development of silicon layer stacking based on copper wafer bonding, grind-back, and etch-back was applied to demonstrate a strong four-layer-stack structure. Bonded copper layers in this structure became homogeneous layers and did not show original bonding interfaces. This process can be used in three-dimensional integrated circuit applications. Voids and total bonded area after each layer stacking were investigated for the bonding quality after each layer stacking. Large wafer bows from high residual stresses result in the structure failure at the stacking of a high number of layers.