Execution Of Threads Research Articles

GPU Parallel Computing Architectures : Unlocking the Power of Parallelism for High-Performance Applications

Graphics Processing Units (GPUs) have evolved from specialized graphics rendering hardware to become powerful parallel computing architectures, revolutionizing high-performance computing across diverse domains. This comprehensive article explores the fundamental principles of GPU parallel computing architectures, their design, and their impact on modern computational challenges. We begin by examining the multi-core structure, memory hierarchy, and data processing capabilities of GPUs, including the SIMD execution model and thread organization. The article then delves into prominent programming models like CUDA and OpenCL, discussing their features and comparative advantages. We explore how GPUs are leveraged for general-purpose computing in scientific simulations, machine learning, and big data analytics, while also addressing the challenges inherent in GPU parallel computing, such as data transfer bottlenecks and load balancing. Recent technological advancements, including tensor cores, unified memory architecture, and ray tracing acceleration, are analyzed for their transformative potential. The article concludes by examining future directions in GPU technology, including integration with emerging technologies like quantum computing, advancements in energy efficiency, and the potential impact on solving complex global challenges. Through this comprehensive analysis, we illustrate the pivotal role of GPU parallel computing architectures in shaping the future of high-performance computing and their potential to address some of the world's most pressing computational problems.

Acceleration of Tensor-Product Operations with Tensor Cores

In this paper, we explore the acceleration of tensor product operations in finite element methods, leveraging the computational power of the NVIDIA A100 GPU Tensor Cores. We provide an accessible overview of the necessary mathematical background and discuss our implementation strategies. Our study focuses on two common programming approaches for NVIDIA Tensor Cores: the C++ Warp Matrix Functions in nvcuda::wmma and the inline Parallel Thread Execution (PTX) instructions mma.sync.aligned . A significant focus is placed on the adoption of the versatile inline PTX instructions combined with a conflict-free shared memory access pattern, a key to unlocking superior performance. When benchmarked against traditional CUDA Cores, our approach yields a remarkable 2.3-fold increase in double precision performance, achieving 8 TFLOPS/s—45% of the theoretical maximum. Furthermore, in half-precision computations, numerical experiments demonstrate a fourfold enhancement in solving the Poisson equation using the flexible GMRES (FGMRES) method, preconditioned by a multigrid method in 3D. This is achieved while maintaining the same discretization error as observed in double precision computations. These results highlight the considerable benefits of using Tensor Cores for finite element operators with tensor products, achieving an optimal balance between computational speed and precision.

Software Model Checking Distributed Applications: A Hybrid Approach

Developing reliable distributed systems poses many challenges such as concurrency, failure handling, and scalability. It is due to the non-deterministic execution of threads within processes, and communication means. Formal verification methods, such as model checking, have been used to ensure the reliability of safety-critical systems. This technique systematically explores the complete behavior of the system under test (SUT), investigating each reachable state with different thread schedules. Recent software model-checking tools, employing cache and centralization, have been applied to distributed systems. The caching technique can only check one process at a time, while the centralization technique verifies all processes simultaneously. In the centralization technique, two "ArrayByteQueue" buffers are utilized to store communication and process data byte-by-byte. However, during the backtracking process, the read and write operations, involving data insertion and removal from the queue, become resource-intensive. As a consequence, existing interprocess communication (IPC) models encounter computational limitations and experience a rapid state space explosion. To address these challenges, our work proposes the remodeling of IPC models by introducing a request and response tree structure to store communication data. Additionally, we employ pointers to navigate through the data during the backtracking process. Through experimental evaluations, the proposed implementation choices have demonstrated significantly improved performance across various metrics. By incorporating the request and response tree, we enhance the efficiency of storing communication data, while the use of pointers optimizes navigation during backtracking. This remodeling of IPC models shows promise in mitigating computational limitations and state space explosion, thereby enhancing the model-checking process in distributed systems. Our research contributes to advancing the field of model checking in distributed systems and offers potential solutions to the challenges associated with resource-intensive read and write operations during the model-checking process.

X-OpenMP — eXtreme fine-grained tasking using lock-less work stealing

Processors with 100s of threads of execution are among the state-of-the-art in high-end computing systems. This transition to many-core computing has required the community to develop new algorithms to overcome significant latency bottlenecks through massive concurrency. However, implementing efficient parallel runtimes that can scale up to high concurrency levels with extremely fine-grained tasks remains a challenge. Existing techniques do not scale to a large number of threads due to the high cost of synchronization in concurrent data structures. We present a thorough analysis of various synchronization mechanisms including mutex, semaphore, spinlock and atomic fetch-and-add that are typically used to build concurrent data structures in task-parallel runtime systems. To overcome these limitations, in a recent work we proposed XQueue, a novel lock-less concurrent queuing system with relaxed ordering semantics that is geared towards realizing scalability up to hundreds of concurrent threads. In this work, we extend XQueue and present X-OpenMP, a library for enabling extremely fine-grained parallelism on modern many-core systems with hundreds of cores. Work stealing is a popular choice for load balancing in task-based runtime systems as it efficiently distributes the load across worker threads; however, traditional approaches rely on synchronization primitives and thus work stealing can incur overheads. Here we implement a lock-less algorithm for work stealing for total-store order (TSO) memory architectures and evaluate the performance using micro and macro benchmarks. We compare the performance of X-OpenMP with native LLVM OpenMP, GNU OpenMP, OpenCilk and oneTBB implementations using task-based linear algebra routines from PLASMA numerical library, Strassen’s matrix multiplication from the BOTS Benchmark Suite, and the Unbalanced Tree Search benchmark. Applications parallelized using OpenMP can run without modification by simply linking against the X-OpenMP library. X-OpenMP achieves up to 40X speedup compared to GNU OpenMP, up to 2X speedup compared to the native LLVM OpenMP, up to 6X speedup compared to OpenCilk and up to 5X speedup compared to oneTBB implementations. The tasking overheads in X-OpenMP are reduced by 50% compared to the native LLVM OpenMP.

HOL4P4: Mechanized Small-Step Semantics for P4

We present the first semantics of the network data plane programming language P4 able to adequately capture all key features of P4 16 , the most recent version of P4, including external functions (externs) and concurrency. These features are intimately related since, in P4, extern invocations are the only points at which one execution thread can affect another. Reflecting P4’s lack of a general-purpose memory and the presence of multithreading the semantics is given in small-step style and eschews the use of a heap. In addition to the P4 language itself, we provide an architectural level semantics, which allows the composition of P4-programmed blocks, models end-to-end packet processing, and can take into account features such as arbitration and packet recirculation. A corresponding type system is provided with attendant progress, preservation, and type-soundness theorems. Semantics, type system, and meta-theory are formalized in the HOL4 theorem prover. From this formalization, we derive a HOL4 executable semantics that supports verified execution of programs with partially symbolic packets able to validate simple end-to-end program properties.

Assessing the Impact of Compiler Optimizations on GPUs Reliability

Graphics Processing Units (GPUs) compilers have evolved in order to support general-purpose programming languages for multiple architectures. NVIDIA CUDA Compiler (NVCC) has many compilation levels before generating the machine code and applies complex optimizations to improve performance. These optimizations modify how the software is mapped in the underlying hardware; thus, as we show in this article, they can also affect GPU reliability. We evaluate the effects on the GPU error rate of the optimization flags applied at the NVCC Parallel Thread Execution (PTX) compiling phase by analyzing two NVIDIA GPU architectures (Kepler and Volta) and two compiler versions (NVCC 10.2 and 11.3). We compare and combine fault propagation analysis based on software fault injection, hardware utilization distribution obtained with application-level profiling, and machine instructions radiation-induced error rate measured with beam experiments. We consider eight different workloads and 144 combinations of compilation flags, and we show that optimizations can impact the GPUs’ error rate of up to an order of magnitude. Additionally, through accelerated neutron beam experiments on a NVIDIA Kepler GPU, we show that the error rate of the unoptimized GEMM (-O0 flag) is lower than the optimized GEMM’s (-O3 flag) error rate. When the performance is evaluated together with the error rate, we show that the most optimized versions (-O1 and -O3) always produce a higher amount of correct data than the unoptimized code (-O0).

An Improved Dynamic Slicing Algorithm to Prioritize a Concurrent Multi-threading in Operating System

One of the issues with multi-threading in operating systems is the concurrency of operations or threads. In a multithreaded process on a single processor, the processor can switch execution resources between threads, enabling concurrent execution. Concurrency indicates that more than one thread is making progress, but the threads are not actually running simultaneously. The switching between threads occurs rapidly enough that the threads might appear to run simultaneously. In this paper, three related strategies for prioritizing multi-threading are presented: ACE-thread, Semaphore coprocessor, and the Concurrent Priority Threads Algorithm. The aim of this work is to enhance an existing prioritization algorithm, specifically the Concurrent Priority Threads Algorithm, by extending a dynamic slicing algorithm to prioritize multi-threading concurrently. The algorithm is designed to compute correct slices in multi-threading prioritization scenarios. Threads with the same highest priority can perform in a synchronized manner without encountering deadlocks. The C++ programming language is used to implement the extended algorithms. The improved algorithm achieved results that were 3% more accurate than the existing one. The outcomes of this work would facilitate the simultaneous execution of threads with the same priority, ultimately reducing waiting and processing times.

Performance Evaluation on Parallel Speculation-Based Construction of a Binary Search Tree

Binary search trees (BSTs) are one of the most important data structures in the field of computer science. We may easily write a parallel construction program of a BST by extending the sequential algorithm straightly. However, in such conventional approaches, the order of nodes inserted into a BST is determined dynamically, depending on the occasional state of the parallel thread execution. It results in a BST with a different structure (node position) generated on every execution of the parallel program. On the other hand, we have been developing parallel construction schemes of the BST with the same structure as a BST generated by the sequential algorithm. One is the speculatively parallel construction of a BST. And another is the purely (non-speculatively) parallel construction, but it was derived through the concept of thread-level speculation. This paper evaluates the performances of those construction schemes on several types of shared-memory multiprocessors. For the large enough size of BST, our new parallel programs can construct a BST with always the same structure on a little lower or sometimes higher performance than the program that makes a BST with a different structure on every execution. And in contrast with the general expectation that simply enlarging the size of parallel tasks increases misspeculation and damages the performance, we found that it sometimes enhances the performance of speculatively parallel execution.

Synchronization Possibilities and Features in Java

Abstract In this paper we have discussed one of the greatest features of the general-purpose computer programming language –Java. This paper represents concepts of Synchronization possibilities and features in Java. Today’s operating systems support concept of “Multitasking”. Multitasking achieved by executing more than one task at a same time. Tasks runs on threads. Multitasking runs more than one task at a same time. Multitasking which means doing many things at the same time is one of the most fundamental concepts in computer engineering and computer science because the processor execute given tasks in parallel so it makes me think that are executing simultaneously. Multitasking is related to other fundamental concepts like processes and threads. A process is a computer program that is executing in a processor, while a thread is a part of a process that has a way of execution: it is a thread of execution. Every process has at least one thread of execution. There are two types of multitasking: process – based and thread – based. Process-based multitasking, means that on a given computer there can be more than one program or process that is executing, while thread-based multitasking, which is also known as multithreading, means that within a process, there can be more than one thread of execution, each of them doing a job and so accomplishing the job of their process. When there are many processes or many threads within processes, they may have to cooperate with each other or concurrently try to get access to some shared computer resources like: processor, memory and input/output devices. They may have to, for example: print a file in a printer or write and/or read to the same file. We need a way of setting an order, where processes and/or threads could do their jobs (user jobs) without any problem, we need to synchronize them. Java has built-in support for process and thread synchronization, there are some constructs that we can use when we need to do synchronization.This paper, a first phase discussed the concept of Parall Programming, threads, how to create a thread, using a thread, working with more than one thread. Second phase is about synchronization, what is in general and in the end we disscused the synchronization possibilities and feautures in Java.

NoC-based hardware software co-design framework for dataflow thread management

Applications running in a large and complex manycore system can significantly benefit from adopting the dataflow model of computation. In a dataflow execution environment, a thread can run only if all its required inputs are available. While the potential benefits are large, it is not trivial to improve resource utilization and energy efficiency by focusing on dataflow thread execution models (i.e., the ways specifying how the threads adhering to a dataflow model of computation execute on a given compute/communication architecture). This paper proposes and implements a hardware-software co-design-based dataflow threads management framework. It works at the Network-on-Chip (NoC) level and consists of three stages. The first stage focuses on a fast and effective thread distribution policy. The next stage proposes an approach that adds reconfigurability to a 2D mesh NoC via customized instructions to manage the dataflow thread distribution. Finally, a 2D mesh and ring-based hybrid NoC is proposed for better scalability and higher performance. This work can be considered a primary reference framework from which extensions can be carried out.

An Unequal Caching Strategy for Shared-Memory Graph Analytics

Recent advances in computer architecture significantly enhance the computational capacity of multicore systems. It allows large-scale graphs to be processed inside a single machine. Nevertheless, the irregular processing pattern of graph-structured data constrains the hardware resources from being productively utilized. In this paper, we investigate the constraints in two aspects: workload imbalance and parallel inefficiency. When a graph analytics algorithm is multithreaded, the thread time is highly diversified, indicating an uneven work distribution. Also, the intensive thread contention lowers the computing capacity of CPU cores, thereby hindering the effective utilization of CPU resources. To address these challenges, we present a proactive graph caching strategy that unequally segments graph components into cache-able subsets of varying sizes, namely Syze. First, the computational loads of cache-sized subgraphs are estimated. Then, the demanding subgraphs are further subdivided until certain threshold is met. Moreover, during the propagation of updates, a fraction of vertex ID (i.e., several bits) are encoded to facilitate the communication between subgraphs. As a result, Syze is able to balance the workloads amongst the logical cores by shortening the longest thread execution time. Meanwhile, it alleviates thread contention and thus elevates the parallel efficiency of multicores. Compared with well-optimized Ligra, Gemini and GPOP, Syze achieves accelerations by up to <inline-formula><tex-math notation="LaTeX">$17.76\times$</tex-math></inline-formula> , <inline-formula><tex-math notation="LaTeX">$11.67\times$</tex-math></inline-formula> and <inline-formula><tex-math notation="LaTeX">$2.81\times$</tex-math></inline-formula> respectively. Additionally, the side effects of Syze are evaluated, including raised cache misses and memory accesses. They play a trivial role in deciding the overall performance, as their costs are far outweighed by the gains from the even distribution of workloads and the improved utilization of multicores. <!--?query id="Q2"--> Author: Please confirm or add details for any funding or financial support for the research of this article. ?>

A GPU-accelerated sharp interface immersed boundary method for versatile geometries

We present a Graphical Processing Unit (GPU) accelerated sharp interface Immersed Boundary (IB) method that can be applied to versatile geometries on a staggered Cartesian grid. The current IB solver predicts the flow around arbitrary surfaces of both finite and negligible thicknesses with improved accuracy near the sharp edges. The proposed methodology first uses a modified signed distance algorithm to track the complex geometries on the structured Cartesian grid accurately. Afterwards, we impose the boundary conditions by reconstructing the flow variables on the near boundary nodes in both fluid and solid domains. We have also shown a reduction of Spurious Force Oscillations (SFOs) near the moving boundaries with reduced divergence error. The accuracy of the present solver is demonstrated at low Reynolds numbers over different stationary and moving rigid geometries associated with sharp edges pertaining to several engineering applications. We have discussed the steps for GPU optimisation of the present solver. Our implementation ensures the concurrent execution of threads for the field extension-based velocity and pressure reconstruction algorithm on a GPU. More than 100x speedup is obtained on NVIDIA V100 GPU for the three-dimensional oscillating sphere simulation. It is observed that the speedup is higher for larger mesh sizes. The computational performance over both the multi-core Control Processing Units (CPUs) and NVIDIA GPUs (V100 and A100) using OpenACC is also provided for the insect flow simulation.

CREATING MULTITHREADED PTOGRAMS IN C++

For many years, the increase in computing power of modern devices is achieved not by increasing the clock frequency and bandwidth of CPUs, but by using hyper-threaded and multicore architectures. This simple change in approach to the CPU design led to dramatic changes in the organization of computing and became a turning point for software developers. Software that is going to take advantage of the increased computing power of multi-core architectures must be designed to be able to perform multiple tasks simultaneously. When covering the topic of parallel/simultaneous computing, scientists and IT professionals use two terms: (1) parallelism and (2) concurrency. A third important term when considering parallel/simultaneous computing is “multithreading”. In C++, the two most common ways to implement parallelism are concurrency and parallelism itself. Although they can be used in other programming languages, C++ stands out for its ability to use concurrent computations with lower-than-average utilization of general machine resources, as well as its ability to execute complex instructions. The C++11 standard introduced support for multi-threaded programs. The C++ standard recognized the existence of multithreading in the language and provided components for writing multithreaded programs in the &lt;thread&gt; library. This made it possible to write multithreaded programs in C++ without relying on platform-specific extensions and enabled the creation of portable multithreaded code with guaranteed behavior. The &lt;thread&gt; library provides extensive opportunities for organizing parallel and concurrent calculations, it also contains the C++ memory model, conditional variables, mutexes, etc. for thread synchronization. The article analyzes the possibilities of writing programs in the C++ using multiple threads for parallel and concurrent execution of tasks. It also considers the features of the C++ and the tools of the &lt;thread&gt; library that make parallelism and concurrency possible.

EXPERTISE: An Effective Software-level Redundant Multithreading Scheme against Hardware Faults

Error resilience is the primary design concern for safety- and mission-critical applications. Redundant MultiThreading (RMT) is one of the most promising soft and hard error resilience strategies because it does not require additional hardware modification. While the state-of-the-art software RMT scheme can achieve a high degree of error protection, our detailed investigation revealed that it suffers from performance overhead and insufficient fault coverage. This paper proposes EXPERTISE, a compiler-level RMT scheme that can detect the manifestation of hardware faults in all processor components. EXPERTISE transformation generates a checker-thread for the main execution thread. These redundant threads are executed simultaneously on two physically different cores of a multicore processor and perform almost the same computations. After each memory write operation is committed by the main-thread, the checker-thread loads back the written data from the memory and checks it against its own locally computed values. If they match, the execution continues. Otherwise, the error flag is raised. In order to evaluate the effectiveness of the proposed solution, we performed soft and hard error injection experiments on all the different hardware components of an ARM Cortex53-like μ-architecturally simulated microprocessor. Based on statistical fault injection campaigns, we have found that EXPERTISE provides 188× better fault coverage with 27% faster performance as compared to the state-of-the-art scheme.

Implementation of a program for real-time processing and visualization of LIDAR scan data in the LabVIEW programming environment

The features of development and optimization of software for real-time LIDAR data processing are considered. The advantages of the LabVIEW graphical development environment for creating highly optimized applications using parallel execution threads and pipelined data processing are shown.

Improvement and comparison the performance of fuzzing testing algorithms for applications in Google Thread Sanitizer

It is difficult to imagine modern information systems without the use of multithreading. The use of multithreading can both improve the performance of the system as in whole so as slow down the execution of multithreaded applications due to the occurrence of multithreaded programming errors. To find such errors in C/C++ languages, there exists a Google Thread Sanitizer compiler module. The order of execution of threads can change every time the program is started for execution and can affect the appearance of such errors. To repeatedly change the order of execution of threads during the execution of the program, Google Thread Sanitizer has a fuzzing testing module that allows you to increase the probability of finding errors. But all the thread scheduling algorithms in this module are presented in the form of sequential execution of threads which can lead to a significant slowdown in Google Thread Sanitizer as well as can affect the testing of applications that depends on timers (waiting for network events, deadline for operations, ...). To speed up the work of fuzzing schedulers, a method for parallelizing independent transitions is proposed. From the point of view of multithreaded programming errors, it is only important to change the shared state between threads, and local calculations do not affect the reproduction of multithreaded errors. The changes of shared states themselves occur at synchronization points (places in the code where threads are switched according to the principle of cooperative multitasking). The method suggests ordering only the change of shared states at synchronization points, and performing local calculations in parallel, due to which parallelization is achieved. For the analysis of theoretical complexity of the algorithm, the method of combinatorial counting is used. A new approach to the organization of fuzzing testing based on the method of parallelization of independent transitions is proposed the implementation of which, according to theoretical and practical estimates, shows a noticeable acceleration of the work of fuzzing schedulers. According to the results of the experiment, it was revealed that for the algorithm of iterating through all execution variants, the acceleration of execution reaches 1.25 times for two threads. For an arbitrary number of threads, an estimate is presented in the form of a formula. The proposed approach allows fuzzing tests to cover multithreaded applications for which execution time is important — applications with reference to timers which improve the quality of the software.

An Efficient Parallel Algorithm for Detecting Packet Filter Conflicts

Advanced network services, such as firewalls, policy-based routing, and virtual private networks, must rely on routers to classify packets into different flows based on packet headers and predefined filter tables. When multiple filters are overlapped, conflicts may occur, leading to ambiguity in the packet classification. Conflict detection ensures the correctness of packet classification and has received considerable attention in recent years. However, most conflict-detection algorithms are implemented on a conventional central processing unit (CPU). Compared with a CPU, a graphics processing unit (GPU) exhibits higher computing power with parallel computing, hence accelerates the execution speed of conflict detection. In this study, we employed a GPU to develop two efficient algorithms for parallel conflict detection: the general parallel conflict-detection algorithm (the GPCDA) and the enhanced parallel conflict-detection algorithm (the EPCDA). In the GPCDA, we demonstrate how to perform conflict detection through parallel execution on GPU cores. While in the EPCDA, we analyze the critical procedure in conflict detection as to reduce the number of matches required for each filter. In addition, the EPCDA adopts a workload balance method to enable load balancing of GPU execution threads, thereby significantly improving performance. The simulation results show that with the 100 K filter database, the GPCDA and the EPCDA execute conflict detection 2.8 to 13.9 and 9.4 to 33.7 times faster, respectively, than the CPU-based algorithm.

Workload Balancing via Graph Reordering on Multicore Systems

In a shared-memory multicore system, the intrinsic irregular data structure of graphs leads to poor cache utilization, and therefore deteriorates the performance of graph analytics. To address the problem, prior works have proposed a variety of lightweight reordering methods with focus on the optimization of cache locality. However, there is a compromise between cache locality and workload balance. Little insight has been devoted into the issue of workload imbalance for the underlying multicore system, which degrades the effectiveness of parallel graph processing. In this work, a measurement approach is proposed to quantify the imbalance incurred by the concentration of vertices. Inspired by it, we present <i>Cache-aware Reorder (Corder)</i> , a lightweight reordering method exploiting the cache hierarchy of multicore systems. At the shared-memory level, Corder promotes even distribution of computation loads amongst multicores. At the private-cache level, Corder facilitates cache efficiency by applying further refinement to local vertex order. Comprehensive performance evaluation of Corder is conducted on various graph applications and datasets. Experimental results show that Corder yields speedup of up to <inline-formula><tex-math notation="LaTeX">$2.59\times$</tex-math></inline-formula> and on average <inline-formula><tex-math notation="LaTeX">$1.45\times$</tex-math></inline-formula> , which significantly outperforms existing lightweight reordering methods. To identify the root causes of performance boost delivered by Corder, multicore activities are investigated in terms of thread behavior, cache efficiency, and memory utilization. Statistical analysis demonstrates that the issue of imbalanced thread execution time dominates other factors in determining the overall graph processing time. Moreover, Corder achieves remarkable advantages in cross-platform scalability and reordering overhead.

Extending the wait-free hierarchy to multi-threaded systems

In modern operating systems and programming languages adapted to multicore computer architectures, parallelism is abstracted by the notion of execution threads. Multi-threaded systems have two major specificities: on the one part, new threads can be created dynamically at runtime, so there is no bound on the number of threads participating in long-running executions. On the other part, threads have access to a memory allocation mechanism that cannot allocate infinite arrays. These specificities make it challenging to adapt some algorithms to multi-threaded systems, in particular those that need to assign one shared register per process. This paper explores the synchronization power of shared objects in multi-threaded systems by extending the famous Herlihy’s wait-free hierarchy to take these constraints into consideration. It proposes to subdivide the set of objects with an infinite consensus number into nine new degrees, depending on their ability to synchronize a bounded, finite or infinite number of processes, with or without the need to allocate an infinite array. To show the relevance of the proposed extension, for each new degree it is either proved that it is empty, or an object illustrating it is proposed.

Simulation modeling of a computer system multithreaded architecture using AnyLogic

The simulation is the most effective way to investigate information processing in computer systems. Computer system simulation is advantageous due to the fact, that such class of systems are well formalized in the form of queuing systems. Any computer system can be considered in terms of queuing system theory as an interconnected set of requests for service, system re-sources, queues to resources, and rules of service. The problem with the study of computer systems is that the existing simulation software tools have been developed as universal tools for the study of general-purpose systems. There are no specialized libraries or separate modeling tools for the study of computer systems. Therefore, modeling computer systems based on the use of standard libraries of such a modern modeling tool as AnyLogic, and the possible creation of elements of a specialized library is of great importance. The objective of the paper is to model multithreaded computing in a multiprocessor computer system using AnyLogic software. The designed computer system diagram enables us to have a deep insight into all details of information processing, and the obtained characteris-tics of the computer system, such as CPU usage coefficients, queue dynamics, distribution of thread execution time in the system, etc., allow us to determine the most effective configuration of the system, the parameters of its elements and operation modes.