Execution Of Threads Research Articles

Generality and Speed in Nonblocking Dual Containers

Nonblocking dual data structures extend traditional notions of nonblocking progress to accommodate partial methods, both by bounding the number of steps that a thread can execute after its preconditions have been satisfied and by ensuring that a waiting thread performs no remote memory accesses that could interfere with the execution of other threads. A nonblocking dual container, in particular, is designed to hold either data or requests . An insert operation either adds data to the container or removes and satisfies a request; a remove operation either takes data out of the container or inserts a request. We present the first general-purpose construction for nonblocking dual containers, allowing any nonblocking container for data to be paired with almost any nonblocking container for requests. We also present new custom algorithms, based on the LCRQ of Morrison and Afek, that outperform the fastest previously known dual containers by factors of four to six.

The Integer Nucleolus of Directed Simple Games: A Characterization and an Algorithm

We study the class of directed simple games, assuming that only integer solutions are admitted; i.e., the players share a resource that comes in discrete units. We show that the integer nucleolus—if nonempty—of such a game is composed of the images of a particular payoff vector under all symmetries of the game. This payoff vector belongs to the set of integer imputations that weakly preserve the desirability relation between the players. We propose an algorithm for finding the integer nucleolus of any directed simple game with a nonempty integer imputation set. The algorithm supports the parallel execution of multiple threads in a computer application. We also consider the integer prenucleolus and the class of directed generalized simple games.

AN OPTINIZED ALGORITHM OF PARALELL DATA PROCESSING BY SNORT CORE

The paper addresses the problem of optimizing the firmware algorithm of detecting and preventing computer attacks on the Internet access workstations and networking equipment. The main objective was to boost the device capacity and save data processing resources. It has been proved that existing soft products that have been developed for single thread execution architectures need to be modified. In particular the paper discusses Snort network intrusion and prevention system that initially has been made to operate on the processor single core in single thread mode. Snort core paralleling principle is based on dividing the inbound traffic into lower-speed atomic channels that are distributed over several individually runnable Snort cores as individual processes that are interconnected and can exchange information. The authors suggest the algorithm optimization way that consists in utilizing the fast shared memory to facilitate information exchange between the processes. The paper focuses on a key element in the data processing paralleling algorithm which is the balance algorithm. The proposed algorithm has been used to optimize the performance of the inbound traffic balancing unit, which increased the operation speed of the total system. A test facility has been developed to simulate and refine the constructed intrusion detection distributed system. The paper presents the testing facility structure, testing method and test numerical results. The test item was a standard traffic routed to the system input from backbone link. The research results were used to determine the dependency of the traffic processing speed on the number of cores in the system.

Data-Driven Thread Execution on Heterogeneous Processors

In this paper we report our experience in implementing and evaluating the Data-Driven Multithreading (DDM) model on a heterogeneous multi-core processor. DDM is a non-blocking multithreading model that decouples the synchronization from the computation portions of a program, allowing them to execute asynchronously in a dataflow manner. Thread dependencies are determined by the compiler/programmer while thread scheduling is done dynamically at runtime based on data availability. The target processor for this implementation is the Cell processor. We call this implementation the Data-Driven Multithreading Virtual Machine for the Cell processor (DDM- $$\hbox {VM}_c$$ ). Thread scheduling is handled in software by the Power Processing Element core of the Cell while the Synergistic Processing Element cores execute the program threads. DDM- $$\hbox {VM}_c$$ virtualizes the parallel resources of the Cell, handles the heterogeneity of the cores, manages the Cell memory hierarchy efficiently and supports distributed execution across a cluster of Cell nodes. DDM- $$\hbox {VM}_c$$ has been implemented on a single Cell processor with six computation cores, as well as, on a four Cell processor cluster with 24 computation cores. We present an in-depth performance analysis of DDM- $$\hbox {VM}_c$$ , using a suite of standard computational benchmarks. The evaluation shows that DDM- $$\hbox {VM}_c$$ scales well and tolerates scheduling overheads, memory and communication latencies effectively. Furthermore, DDM- $$\hbox {VM}_c$$ compares favorably with other platforms targeting the Cell processor, such as, the CellSs and Sequoia.

Software Analysis Techniques for Detecting Data Race

Data races are a multithreading bug. They occur when at least two concurrent threads access a shared variable, and at least one access is a write, and the shared variable is not explicitly protected from simultaneous accesses of the threads. Data races are well-known to be hard to debug, mainly because the effect of the conflicting accesses depends on the interleaving of the thread executions. Hence there has been much effort to detect data races through sophisticated techniques of software analysis by automatically analyzing the behavior of computer programs. Software analysis techniques can be categorized according to the time they are applied: static or dynamic. Static techniques derive program information, such as invariants or program correctness, before runtime from source code, while dynamic techniques examine the behavior at runtime. In this paper, we survey data race detection techniques in each of these two approaches.

Parallel implementations of the 3D fast wavelet transform on a Raspberry Pi 2 cluster

Current low-cost general-purpose single-board computing (SDC) devices are gaining increasing interests in research computing due to their very low cost/performance ratio and energy consumption. Among all the SDCs available nowadays, Raspberry Pi devices constitute maybe the most renowned representatives. On the other hand, the wavelet transform plays an important role in contemporary standards for image compression (such as JPEG-2000) and video compression (MPEG-4). In this work, we present and evaluate three parallelization strategies of the 3D fast wavelet transform (3D-FWT) on a cluster of Raspberry Pi 2 SDCs. Each parallelization strategy has been implemented using both POSIX Threads (shared memory) and MPI (message passing). The set of implementations using POSIX Threads is restricted to runs on a single board, whereas multiple boards can be used for the MPI versions. We find out that noticeable speed-ups can be obtained when all MPI processes or POSIX Threads are run using the cores of a single Raspberry Pi 2 SDC. However, in the case of the MPI versions, we observe that performance drops drastically when all MPI processes spread to several boards. The reason for this is the limited bandwidth that the onboard LAN port can deliver, and that proves insufficient for the fine-grained, high-volume communication requirements of the studied parallelization strategies. Finally, we have also considered the execution of the POSIX Threads and MPI versions on a very high-performance but power-hungry 4-core Intel Xeon CPU E5606, obtaining that the Raspberry Pi 2 SDC can do the task with much lower total energy consumption (up to 4 times).

Concurrent JavaScript Parsing for Faster Loading of Web Apps

JavaScript is a dynamic language mainly used as a client-side web script. Nowadays, web is evolving into an application platform with its web apps , and JavaScript increasingly undertakes complex computations and interactive user interfaces, requiring a high-performance JavaScript engine. There have been many optimizations for efficient JavaScript engines, but one component that has not been optimized much is JavaScript parsing . A JavaScript function needs to be parsed before being executed, and the parsing overhead takes a substantial portion of JavaScript execution time for web apps, especially during app loading . This article proposes concurrent parsing of JavaScript, which performs the parsing of JavaScript functions in advance on different threads, while the main thread is executing the parsed JavaScript functions. This can hide the parsing overhead from the main execution thread, reducing the JavaScript execution time, thus reducing the overall app loading time. More specifically, we separated JavaScript parsing and made it run on different threads without violating the execution semantics of JavaScript. We also designed an efficient multi-threaded parsing architecture, which reduces the synchronization overhead and schedules the parsing requests appropriately. Finally, we explored two methods of choosing the target functions for concurrent parsing: one based on profiled information and the other based on speculative heuristics. We performed experiments on the WebKit browser with the JSC engine for real web apps. The result shows that the proposed concurrent parsing can improve the JavaScript performance during app loading by as much as 64% and by 39.7% on average. This improves the whole app loading performance tangibly, by as much as 32.7% and by 18.2%, on average.

Task Mapping for Redundant Multithreading in Multi-Cores with Reliability and Performance Heterogeneity

Due to the architectural design, process variations and aging, individual cores in many-core systems exhibit heterogeneous performance. In many-core systems, a commonly adopted soft error mitigation technique is Redundant Multithreading (RMT) that achieves error detection and recovery through redundant thread execution on different cores for an application. However, task mapping and the task execution mode (i.e., whether a task executes in a reliable mode with RMT or unreliable mode without RMT) need to be considered for achieving resource-efficient reliability. This paper explores how to efficiently assign the tasks onto different cores with heterogeneous performance properties and determine the execution modes of tasks in order to achieve high reliability and satisfy the tolerance of timeliness. We demonstrate that the task mapping problem under heterogeneous performance can be solved by employing Hungarian Algorithm as subroutine to efficiently assign the tasks onto the cores to optimize the system reliability with polynomial time complexity. To obtain the efficient task execution modes, we also propose an iterative mode adaptation technique and guarantee the tolerable timing constraint. Our results illustrate that compared to state-of-the-art, the proposed approaches achieve up to $80$ percent reliability improvement (on average $20$ percent) under different scenarios of chip frequency variation maps.

Portability with efficiency of the advection of BRAMS between multi‐core and many‐core architectures

SummaryThe continuous growth of spatial resolution and forecasting period in current atmospheric models demands increasing processing power supplied by supercomputers with hundreds or thousands of nodes. Currently, most of these models are operationally executed on supercomputers composed of nodes with tens of cores (multi‐core architecture). Newer supercomputer generations have nodes with multi‐core processors coupled to processing accelerators, typically graphics cards with hundreds of cores (many‐core architecture). The rewriting of model codes to use both architectures efficiently, that is, executing with or without graphics cards, represents a challenge because these models have hundreds of thousands of lines. The OpenMP programming interface proposed decades ago is a de facto standard that efficiently explores multi‐core architectures. A new programming interface, OpenACC, is being proposed for many‐core architectures. These two programming interfaces are similar, because they are based on parallelization directives for the concurrent execution of threads. This work shows the feasibility of writing a single portable code embedding both interfaces and presenting acceptable efficiency when executed on nodes with multi‐core or many‐core architecture. The code chosen as a case study is the advection of scalars, a part of the dynamics of the regional atmospheric model Brazilian Regional Atmospheric Modeling System (BRAMS). The dynamics of a model is harder to parallelize because of data dependencies between adjacent grid points. Single‐node executions of the advections of scalars for different grid sizes using OpenMP or OpenACC yielded similar speed‐ups, showing the feasibility of the proposed approach. Copyright © 2016 John Wiley & Sons, Ltd.

A Tutorial on Pharmacodynamic Scripting Facility inSimcyp.

The Simcyp Simulator provides a framework for mechanistic Physiologically‐Based Pharmacokinetic/Pharmacodynamic modeling of potentially interacting drugs. It also provides a scripting facility, using the Lua language, for developing customized pharmacodynamic and toxicity models driven by drug concentrations at the site of action. We present an overview of the scripting facility including the scripting language, the editor, and how scripts are embedded within the Simulator. Examples incorporating differential equations and including inter‐individual variability on parameters are presented.

Efficient resource sharing algorithm for physical register file in simultaneous multi-threading processors

Simultaneous Multi-Threading (SMT) processors increase performance by allowing concurrent execution of multiple independent threads with sharing of key datapath components and better utilization of the resources. An SMT processor usually maintains a shared register file to accommodate multiple threads for register renaming. By supporting inter-thread sharing of the physical registers, an SMT system processor can reduce the number of registers that would have been required in multiple superscalar processors while achieving a comparable throughput. However, congested shared resources due to slower threads can easily lead to inefficient usage of the resources and thus an undesirable performance outcome. In this paper, we propose an allocation algorithm at the architectural level for a better utilization of the shared register file. We show that, by limiting the number of the physical register entries each thread is allowed to occupy at any given time, the overall system throughput is enhanced by a substantial margin. An improvement in IPC of up to 44.6% and 32.7% is observed when the proposed technique is applied to a 4-threaded and a 6-threaded SMT system, respectively. Furthermore, a 4-threaded system with a physical register file of 160 entries can deliver a performance comparable to that of a default system with 256 entries, reflecting a resource saving of 37.5%.

Genetic-variable neighborhood search with thread replication for mobile cloud computing

The resource-intensive resettlement procedure and inherent restrictions of the wireless medium obstruct the understanding of faultless implementation in mobile cloud computing (MCC) surroundings. In MCC, transfer of thread execution to high end servers allows the processing of those jobs which demand more resources on the mobile equipment. Hence, implementing the application with stumpy cost, least overhead and non-obtrusive relocation is a demanding research area in MCC. Many scheduling mechanisms have been proposed so far to balance the load between the given set of mobile servers, but it is found to be NP-Hard problem. Therefore, evolutionary techniques are required to balance the load among mobile servers. Genetic Algorithm (GA) has been verified to be fine by jumble up the key values, but it becomes unsuccessful to strengthen the exploration in the rising areas. In Variable Neighborhood Search (VNS), local exploration technique is implemented continually to evaluate optimistic outcomes in neighborhood to attain local best solution. But VNS is still prone to premature convergence traps only because of limited search capability. Therefore hybridization with non-global finding techniques may conquer the limitations and guide the dominant search mechanisms to some extent. The GA along with VNS using thread replication (GVNSTR) is implemented to set stability of non-local searching and local utilization for an evolutionary processing period and get the optimized solution.

Improvement in the distribution of services in multi-agent systems with SCODA

The distribution of services on multi-agent systems allows it to reduce to the agents their computational load. The functionality of the system does not reside in the agents themselves, however it is ubiquitously distributed so that allows you to perform tasks in parallel avoiding an additional computational cost to the elements in the system. The distribution of services that offers SCODA (Distributed and Specialized Agent Communities) allows an intelligent management of these services provided by agents of the system and the parallel execution of threads that allow to respond to requests asynchronously, which implies an improvement in the performance of the system at both the computational level as the level of quality of service in the control of these services. The comparison carried out in the case of study that is presented in this paper demonstrates the existing improvement in the distribution of services on systems based on SCODA.

Warped-slicer

As technology scales, GPUs are forecasted to incorporate an ever-increasing amount of computing resources to support thread-level parallelism. But even with the best effort, exposing massive thread-level parallelism from a single GPU kernel, particularly from general purpose applications, is going to be a difficult challenge. In some cases, even if there is sufficient thread-level parallelism in a kernel, there may not be enough available memory bandwidth to support such massive concurrent thread execution. Hence, GPU resources may be underutilized as more general purpose applications are ported to execute on GPUs. In this paper, we explore multiprogramming GPUs as a way to resolve the resource underutilization issue. There is a growing hardware support for multiprogramming on GPUs. Hyper-Q has been introduced in the Kepler architecture which enables multiple kernels to be invoked via tens of hardware queue streams. Spatial multitasking has been proposed to partition GPU resources across multiple kernels. But the partitioning is done at the coarse granularity of streaming multiprocessors (SMs) where each kernel is assigned to a subset of SMs. In this paper, we advocate for partitioning a single SM across multiple kernels, which we term as intra-SM slicing. We explore various intra-SM slicing strategies that slice resources within each SM to concurrently run multiple kernels on the SM. Our results show that there is not one intra-SM slicing strategy that derives the best performance for all application pairs. We propose Warped-Slicer , a dynamic intra-SM slicing strategy that uses an analytical method for calculating the SM resource partitioning across different kernels that maximizes performance. The model relies on a set of short online profile runs to determine how each kernel's performance varies as more thread blocks from each kernel are assigned to an SM. The model takes into account the interference effect of shared resource usage across multiple kernels. The model is also computationally efficient and can determine the resource partitioning quickly to enable dynamic decision making as new kernels enter the system. We demonstrate that the proposed Warped-Slicer approach improves performance by 23% over the baseline multiprogramming approach with minimal hardware overhead.

A Survey on Parallelization of Neural Network using MPI and Open MP

Background: Neural networks are relatively crude computerized model based on the neural system of the human brain. The Complex problems may require sophisticated processing techniques to achieve practical speed. In human brain millions of neurons form a massively parallel information system. Method: A neural network is a parallel and distributed process. The parallel execution of the neural network is achieved up to the level of the training process. Parallelization approaches may work well on hardware implementations, a software package (SPANN), special purpose hardware and multicore CPUs through MPI. Findings: In order to achieve parallelism and speed up the training process, each neuron and full neural network is duplicated to multiple threads. In modern Microprocessor number of cores is rapidly increasing. So high-performance computing is a great challenge for the application developers. Improvements: Our future work directs to distribute neurons to multiple threads for parallel execution and duplicate the full neural network for parallel training.

Modern multicore and manycore architectures: Modelling, optimisation and benchmarking a multiblock CFD code

Modern multicore and manycore processors exhibit multiple levels of parallelism through a wide range of architectural features such as SIMD for data parallel execution or threads for core parallelism. The exploitation of multi-level parallelism is therefore crucial for achieving superior performance on current and future processors. This paper presents the performance tuning of a multiblock CFD solver on Intel SandyBridge and Haswell multicore CPUs and the Intel Xeon Phi Knights Corner coprocessor. Code optimisations have been applied on two computational kernels exhibiting different computational patterns: the update of flow variables and the evaluation of the Roe numerical fluxes. We discuss at great length the code transformations required for achieving efficient SIMD computations for both kernels across the selected devices including SIMD shuffles and transpositions for flux stencil computations and global memory transformations. Core parallelism is expressed through threading based on a number of domain decomposition techniques together with optimisations pertaining to alleviating NUMA effects found in multi-socket compute nodes. Results are correlated with the Roofline performance model in order to assert their efficiency for each distinct architecture. We report significant speedups for single thread execution across both kernels: 2-5X on the multicore CPUs and 14-23X on the Xeon Phi coprocessor. Computations at full node and chip concurrency deliver a factor of three speedup on the multicore processors and up to 24X on the Xeon Phi manycore coprocessor.

Shared write buffer to boost applications on SpMT architecture

With the trend of growing number of integrated processing cores on Chip Multiprocessors, researchers are working hard to increase the available parallelism of software programs so as to efficiently harness the growing computing power. One noticeable direction among these efforts is speculative multi-threading (SpMT), a.k.a thread level speculation, which aims to extract thread level parallelism by splitting a sequential execution thread into several finer ones and execute them on parallel. A SpMT thread is in speculative status before it “knows” all its input data are correct. A speculative thread needs to write to the L1 cache, but its output might be discarded if the speculation eventually fails. However, another speculative thread may have already read in such speculative output. Therefore, some mechanism is needed to support speculative read and write. And because the SpMT threads are extracted from a single thread, they usually share lots of data, thus there might be intense data coherence among the L1 caches. It would be very complicated to support data coherence and speculation together. This Paper proposes a shared write buffer among the SpMT cores. We are able to confine the speculative read and write in the SWB, thus the speculation will not interference with coherence, and the L1 cache design could be drastically simplified. Experiments show that the SWB can capture a big portion of inter-core data sharing, reduce cache coherence, and drastically improve data access performance of SpMT threads.

Research on Cache Timing Attack Against RSA with Sliding Window Exponentiation Algorithm

The vulnerabilities of the RSA cryptographic algorithm are analyzed, and it is not securely implemented. As the simultaneous multithreading could enable multiple execution threads to share the execution resources of a superscalar between the chipper process and the spy process, the shared access to memory caches provides an easily used high bandwidth covert channel between threads, allowing that a malicious thread can monitor the execution of another thread. This paper targets at RSA algorithm which is implemented with sliding window exponentiation algorithm via OpenSSL, the attacker can monitor the cryptographic thread by executing a spy thread, recording the timing characteristic during the RSA decryption when reading the Cache. The attacker can recover the original key via analyzing these timing measurements. Finally, the authors provide some countermeasures of how this attack could be mitigated or eliminated entirely.

Classical realizability and arithmetical formulæ

In this paper, we treat the specification problem in Krivine classical realizability (Krivine 2009Panoramas et synthèses27), in the case of arithmetical formulæ. In the continuity of previous works from Miquel and the first author (Guillermo 2008Jeux de réalisabilité en arithmétique classique, Ph.D. thesis, Université Paris 7; Guillermo and Miquel 2014Mathematical Structures in Computer Science, Epub ahead of print), we characterize the universal realizers of a formula as being the winning strategies for a game (defined according to the formula). In the first sections, we recall the definition of classical realizability, as well as a few technical results. In Section 5, we introduce in more details the specification problem and the intuition of the game-theoretic point of view we adopt later. We first present a game1, that we prove to be adequate and complete if the language contains no instructions ‘quote’ (Krivine 2003Theoretical Computer Science308259–276), using interaction constants to do substitution over execution threads. We then show that as soon as the language contain ‘Quote,’ the game is no more complete, and present a second game2that is both adequate and complete in the general case. In the last Section, we draw attention to a model-theoretic point of view and use our specification result to show that arithmetical formulæ are absolute for realizability models.

An Implementation of a Fast Threaded Nondeterministic LL(*) Parser Generator

Parsers are used in many applications such as compilers, NLP and other applications. Parsers that are developed by hand are a complex task and require a generator to automatically generate the parser. The generator reads a grammar and generates a fully working parser. This paper proposes separating the semantic actions’ execution from the parsing phase. The parser generates a queue of semantic actions attached with grammar rules to be visited in case of successful parsing. By this separation, the execution time of the parsing phase can be enhanced. More importantly, this will avoid the incorrect execution of semantic actions when dealing with non-deterministic grammars. Investigating an implementation for the parallelization of the parsing phase for non-deterministic rules is also another contribution of the paper. A previous theoretical work of this paper was made in [1]. The experimental work shows that working with single threaded backtracking with storage of intermediate results, as well as following the Fork/Join parallel execution model without intermediate storage perform in most cases better than working with raw threads execution or by predicting rules as in ANTLR V4. The generator assumes that the grammar is left-recursive free. General Terms Compiler, parsers and parser generator