Third-order Sigma-delta Modulator Research Articles

A Partially Feedback NSSAR Embedded Third-Order Delta–Sigma Modulator With Gain-Boosted Two-Stage FIAs

A Partially Feedback NSSAR Embedded Third-Order Delta–Sigma Modulator With Gain-Boosted Two-Stage FIAs

Design of a Sigma-Delta Analog-to-Digital Converter Cascade Decimation Filter

As the current mainstream high-precision ADC architecture, sigma-delta ADC is extensively employed in a wide range of domains and applications. This paper presents the design of a highly efficient cascaded digital decimation filter for sigma-delta ADCs, emphasizing the suppression of high folding band noise and the achievement of a flat passband. Additionally, this study addresses the critical balance between filter performance and power consumption. An inserting zero (IZ) filter is incorporated into a cascaded integrator comb (CIC) filter to enhance aliasing suppression. The IZ filter and compensation filter are optimized using the particle swarm optimization (PSO) algorithm to achieve greater noise attenuation and smaller passband ripple. The designed filter achieves a noise attenuation of 93.4 dB in the folding band and exhibits an overall passband ripple of 0.0477 dB within a bandwidth of 20 KHz. To decrease the power consumption in the filter design, polyphase decomposition has been applied. The filter structure is implemented on an FPGA, processing a 5-bit stream from a 64-times oversampling rate and third-order sigma-delta modulator. The signal-to-noise ratio (SNR) of the output signal reaches 91.7 dB. For ASIC design, the filter utilizes 180 nm CMOS technology with a power consumption of 0.217 mW and occupies a layout area of 0.72 mm2. The post-layout simulation result indicates that the SNR remains at 91.7 dB.

A fractional-N frequency synthesizer with phase synchronization and programmable phase control capability

A fractional-N frequency synthesizer (FS) with phase synchronization and programmable phase control capacity is proposed. The issue of phase inconsistency among multiple FSs caused by the shift of delta-sigma modulator (DSM) output sequence is solved by means of the dual DSM switching technique. Following the FS core, a resettable divider (R-DIV) is presented, which can not only expand the final output frequency range, but also eliminate the phase uncertainty incurred by uncontrollable initial states inherent in the ordinary dividers. By adding initial values to the first order accumulator in the third-order DSM, the output clock phase of the FS can be controlled accordingly. The simulation results show that from a supply voltage of 1.2 V, the frequency range of the FS is 0.4∼12 GHz, and the phase synchronization time is < 10 μs. The minimum phase shift step size of the programmable phase control is 5.625°, the RMS phase error is < 0.9°, and the power consumption is 113.7 mW.

Design and Analysis of a Buck–Boost DC–DC Converter with Delta-Sigma Modulator Controller

This paper presents a low-ripple and high-efficiency buck–boost DC–DC converter with delta-sigma modulator controller that converts 1.8 V to 1.2 V and 3.3 V. A current and voltage closed-loop controller has been designed to achieve better performance simultaneously such as lower settling-time, steady-state error and over shoot and under shoot. The converter is started in the current controller mode initially, when the output voltage approaches the desired value, the power stage is controlled with the voltage controller mode. PI compensator and a third-order delta-sigma modulator are utilized in the voltage mode. Also, the closed-loop stability of the designed converter has been analyzed with Lyapunov method using converter nonlinear model. This work has been simulated in MATLAB-SIMULINK environment. The performance results show that the maximum efficiency of the closed-loop DC–DC converter is 90% at 5[Formula: see text]MHz switching frequency, and the output voltage ripple is 0.5% and 0.6% for the buck and boost modes, respectively. Also, the simulation results demonstrate the closed-loop stability of the converter in the presence of 10% load variation.

Behavioral and Electrical Modeling of a 0.5-V Third-Order Continuous-Time Sigma-Delta Modulator with FIR DAC for Audio Applications

Most mobile and wearable devices present digital audio signal processing capabilities. Since the nature of audio signals is analog, there is a need to use analog-to-digital converters (ADCs) with high-resolution for a high signal-to-noise ratio audio acquisition. This paper presents the high-level modeling and design of a continuous-time third-order sigma-delta modulator (CT-SDM) with an FIR DAC for audio devices, using a supply voltage of 0.5 V. The design is divided in three steps and is carried out using the Delta-sigma toolbox and a discrete-time to continuous-time (DT-CT) transformation. First, the schematic implementation with verilogA models is done to estimate the first-integrator amplifier specifications for the modulator to provide 14 bits of ENOB. Following, a two-stage inverter-based amplifier is designed and used to verify the design strategy. Finally, a transistor-level implementation of OTAs and comparator is done to evaluate the CT-SDM performance. An in-depth analysis and discussion are presented to explain the achieved results with those transistor-level circuits.

A 440-μW, 109.8-dB DR, 106.5-dB SNDR Discrete-Time Zoom ADC With a 20-kHz BW

This article describes a discrete-time zoom analog-to-digital converter (ADC) intended for audio applications. It uses a coarse 5-bit SAR ADC in tandem with a fine third-order delta-sigma modulator (ΔΣM) to efficiently obtain a high dynamic range. To minimize its over-sampling ratio (OSR) and, thus, its digital power consumption, the modulator employs a 2-bit quantizer and a loop filter notch. In addition, an extra feed-forward path minimizes the leakage of the SAR ADC's quantization noise into the audio band. The prototype ADC occupies 0.27 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> in a 0.16-μm technology. It achieves 109.8-dB DR, 106.5-dB SNDR, and 107.5-dB SNR in a 20-kHz bandwidth while dissipating 440 μW. It also achieves state-of-the-art energy efficiency, as demonstrated by a Schreier FoM of 186.4 dB and an SNDR FoM of 183.6 dB.

100.5 dB SNDR Analog Front-End With a Resistor-Based Discrete-Time Delta-Sigma Modulator for Eliminating Switching Noise and Harmonics

This paper presents a high-resolution analog front-end (AFE) circuit operating in the 25 kHz signal bandwidth. The AFE consists of a capacitively-coupled chopper instrumentation amplifier (CCIA) and a third-order delta-sigma modulator (DSM). Signal distortion often occurs at the junction of CCIA and DSM, so the resistor-based discrete-time DSM (RB DT–DSM) is proposed to solve this problem. Both conventional DT–DSM and the proposed RB DT–DSM are designed and compared through simulations and chip measurements. When a conventional DT–DSM is used, a switched-capacitor integrator with a large capacitor and switch are connected to the CCIA output node, so large switching noise, significant charge injection, and a long settling time occur at the CCIA output, resulting in harmonic distortions. Therefore, CCIA requires more power consumption to reduce the settling time for conventional DT–DSM architectures. On the other hand, when the proposed RB DT–DSM is used, only a resistor and a small switch are connected to the CCIA output. Due to this novel interface technique, the switching noise is very small at the CCIA output, and the settling of the CCIA becomes fast. As a result, it is possible to effectively eliminate harmonic distortions while reducing the power requirement of the CCIA. Both the conventional and proposed AFE circuits were manufactured by a 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> complementary metal-oxide-semiconductor (CMOS) process. The conventional AFE shows a peak SNR of 101.1 dB and a peak SNDR of 91.2 dB. The proposed AFE with RB DT–DSM shows a peak SNR of 101.3 dB and a peak SNDR of 100.5 dB, which verifies the significant reduction in harmonic distortions.

Harmonic Distortion Optimization for Sigma-Delta Modulators Interface Circuit of TMR Sensors.

The tunneling magnetoresistance micro-sensors (TMR) developed by magnetic multilayer material has many advantages, such as high sensitivity, high frequency response, and good reliability. It is widely used in military and civil fields. This work presents a high-performance interface circuit for TMR sensors. Because of the nonlinearity of signal conversion between sensitive structure and interface circuit in feedback loop and forward path, large harmonic distortion occurs in output signal spectrum, which greatly leads to the reduction of SNDR (signal noise distortion rate). In this paper, we analyzed the main source of harmonic distortion in closed-loop detection circuit and establish an accurate harmonic distortion model in TMR micro-sensors system. Some factors are considered, including non-linear gain of operational amplifier unit, effective gain bandwidth, conversion speed, nonlinearity of analog transmission gate, and nonlinearity of polycrystalline capacitance in high-order sigma-delta system. We optimized the CMOS switch and first-stage integrator in the switched-capacitor circuit. The harmonic distortion parameter is optimally designed in the TMR sensors system, aiming at the mismatch of misalignment of front-end system, non-linearity of quantizer, non-linearity of capacitor, and non-linearity of analog switch. The digital output is attained by the interface circuit based on a low-noise front-end interface circuit and a third-order sigma-delta modulator. The digital interface circuit is implemented by 0.35μm CMOS (complementary metal oxide semiconductor) technology. The high-performance digital TMR sensors system is implemented by double chip integration and the active interface circuit area is about 3.2 × 2 mm. The TMR sensors system consumes 20 mW at a single 5 V supply voltage. The TMR sensors system can achieve a linearity of 0.3% at full scale range (±105 nT) and a resolution of 0.25 nT/Hz1/2(@1Hz).

Improving Power Efficiency for Active-&lt;italic&gt;RC&lt;/italic&gt; Delta-Sigma Modulators Using a Passive-&lt;italic&gt;RC&lt;/italic&gt; Low-Pass Filter in the Feedback

This brief presents a technique to improve the power efficiency of an active- RC 1-bit continuous-time Delta-Sigma modulator (DSM). A passive- RC low-pass filter (LPF) is used in feedback after the 1-bit digital-to-analog converter (DAC). The LPF smooths out the rail-to-rail sharp edges of the DAC output to reduce the signal-swing and slew-rate requirements of the first amplifier in DSM. The LPF is also utilized to contribute a pole to the loop response of the modulator. It does not require a compensation filter and reduces the order of the active part of the loop filter. A third-order DSM was designed in a 0.18- ${\mu }\text{m}$ CMOS process. Measurement results show that it can achieve 79.1-dB SNDR over 100-kHz bandwidth while consuming only 59.1 ${\mu }\text{W}$ .

A 5.35-mW 10-MHz Single-Opamp Third-Order CT &lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;$\Delta\Sigma$ &lt;/tex-math&gt; &lt;/inline-formula&gt; Modulator With CTC Amplifier and Adaptive Latch DAC Driver in 65-nm CMOS

This paper reports a continuous-time (CT) third-order delta-sigma modulator that features a single amplifier biquad (SAB) and a passive integrator to simplify the circuit to just one power hungry operation amplifier (opamp). Such setup not only relaxes the gain and bandwidth requirement of the opamp design but also enhances the overall modulator stability which enables a power-efficient loop filter implementation. We used an SAR architecture in the quantizer with an advanced feedback technique to alleviate its speed penalty. By incorporating the proposed CT complementary (CTC) opamp and an adaptive latch scheme in the DAC driver, the modulator attains a signal bandwidth of 10 MHz with 79.6-dB signal-to-noise and distortion ratio (SNDR) while only consuming 5.35 mW from 1.2- and 1.8-V power supplies. The prototype has a dynamic range of 84.5 dB and a Schreier FoM of 177.2 dB with an active area of 0.033 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

A 10-MHz Bandwidth Two-Path Third-Order &lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;$\Sigma\Delta$ &lt;/tex-math&gt; &lt;/inline-formula&gt; Modulator With Cross-Coupling Branches

This brief presents a two-path discrete-time third-order sigma-delta ( $\Sigma \Delta$ ) modulator with an extra zero in the noise transfer function (NTF) located at $z = -1$ , reducing the NTF coefficients of intermediate terms for optimal design. Applying polyphase decomposition of the NTF, the proposed $\Sigma \Delta$ modulator is implemented by a two-path architecture with cross-coupling branches. The 65-nm CMOS experimental chip running at a sampling rate of 340 MHz achieves a DR of 68.8 dB and a SNDR of 65.4 dB for a 10-MHz signal bandwidth, occupying an active area of 0.2257 mm2 and consuming 19.47 mW from a 1.2-V supply.

A Precision Capacitance-to-Digital Converter With 16.7-bit ENOB and 7.5-ppm/°C Thermal Drift

This paper presents a high-precision capacitance-to-digital converter (CDC) for displacement measurement in advanced industrial applications, based on a charge-balancing third-order delta–sigma modulator. To achieve high precision, this CDC employs a precision external resistive reference and a quartz-oscillator-based time reference instead of a reference capacitor. To minimize the error contribution of the CDC circuitry, various precision circuit techniques, such as chopping and auto-zeroing, are applied at both system and circuit level. Measurement results of the prototype realized in 0.35- $\mu \text{m}$ CMOS technology show that the CDC achieves an rms resolution of 42 aF across a capacitance range from 6 to 22 pF, corresponding to an effective number of bits (ENOB) of 16.7 bit. The conversion time for one measurement is 10.5 ms, during which the CDC consumes 230 $\mu \text{A}$ from a 3.3-V single supply. The measured thermal stability is within ±7.5 ppm/°C across a temperature range from 20 °C to 70 °C, which represents a significant improvement compared to the state of the art. After a two-point calibration, all ten measured samples from one batch show absolute accuracy below ±25 fF across the entire capacitance measurement range.

A Low-EMI Buck Converter Suitable for Wireless Sensor Networks With Spur-Reduction Techniques

This paper presents a low electromagnetic interference buck converter for wireless sensor networks with the spur-reduction techniques. The proposed buck converter uses the third-order delta–sigma modulator (DSM) with its noise-shaping characteristic to achieve low output noise. The DSM is designed with the chopper-stabilization techniques, which further reduces the impacts of low-frequency noises, such as flicker noise and offset voltage. The proposed buck converter also adopts fast transient path in order to get a fast transient response. The proposed buck converter has been fabricated with a TSMC 0.35- $\mu \text{m}$ CMOS 2P4M process. The area of the whole chip is 2.18 mm2. Compared with previous works, the noise floor of the proposed converter’s output is below −76 dBm, which is lower than others. The settling time of the proposed converter’s output is $\sim 20~\mu \text{s}$ with the load current skipping between 50 and 500 mA, that is faster than previous works, too. Moreover, the peak efficiency of the proposed converter is better and equals to 90%.

Design of Fully-Differential Switched-Capacitor Integrator for Sigma-Delta Modulator

This paper presents fully-differential switched-capacitor(SC) integrator for the third-order Sigma-Delta(SD) modulator. The proposed circuit allows rail-to-rail switching operation for the low voltage SC circuit, and it has better total harmonic distortion than the conventional circuit. This circuit provides an important block for the 2-1 cascaded SD modulator with the highresolution analog-to-digital conversion on audio codec in a communication transceiver. The switched-capacitor integrator is fabricated using 0.18μm doublepoly, triple-metal standard CMOS process with 1.8V supply voltage. The 1% settling time of the OTA consisting of SC integrator is measured to be 560ns with load capacitance of 16pF. The results showed excellent performance. The die size is 0.430×0.296㎟.

A True 0.4-V Delta–Sigma Modulator Using a Mixed DDA Integrator Without Clock Boosted Switches

This brief proposes a delta-sigma modulator that operates at extremely low voltage without using a clock boosting technique. To maintain the advantages of a discrete-time integrator in oversampled data converters, a mixed differential difference amplifier (DDA) integrator is developed that removes the input sampling switch in a switched-capacitor integrator. Conventionally, many low-voltage delta-sigma modulators have used high-voltage generating circuits to boost the clock voltage levels. A mixed DDA integrator with both a switched-resistor and a switched-capacitor technique is developed to implement a discrete-time integrator without clock boosted switches. The proposed mixed DDA integrator is demonstrated by a third-order delta-sigma modulator with a feedforward topology. The fabricated modulator shows a 68-dB signal-to-noise-plus-distortion ratio for a 20-kHz signal bandwidth with an oversampling ratio of 80. The chip consumes 140 μW of power at a true 0.4-V power supply, which is the lowest voltage without a clock boosting technique among the state-of-the-art modulators in this signal band.

Design of Third-Order Single-Loop Full Feed-Forward Sigma Delta Modulator

Sigma Delta modulator is widely used in ADC for kinds of micro inertial sensors, Sigma Delta ADC can be easily integrated with digital circuits. It possesses some performances of good linearity and high accuracy, while it has no such strict requirements for the match of device dimensions. In this paper, the design of third-order Sigma Delta modulator with a structure of single-loop full feed-forward is accomplished, meanwhile it uses local feedback for zero optimization to improve the shaping capacity of the modulator noise within the signal bandwidth. The OSR (over-sampling rate) of the modulator is 128 and the signal bandwidth is 10 kHz. By the system model building and simulation in the Simulink of MATALAB, the SNR is 96.3 dB and the ENOB is 15.71 bits. Then the modulator is implemented into transistor-level circuits with 0.5um process, by the simulation in Spectre of Cadence, the SNR is 88.5 dB and the ENOB is 14.41 bits. 搜

A 1.2-V 8.3-nJ CMOS Humidity Sensor for RFID Applications

This paper presents a fully integrated CMOS humidity sensor for a smart RFID sensor platform. The sensing element is a CMOS-compatible capacitive humidity sensor, which consists of top-metal finger-structure electrodes covered by a humidity-sensitive polyimide layer. Its humidity-sensitive capacitance is digitized by an energy-efficient capacitance-to-digital converter (CDC) based on a third-order delta-sigma modulator. This CDC employs current-efficient operational transconductance amplifiers based on current-starved cascoded inverters, whose limited output swing is accommodated by employing a feedforward loop-filter topology. A programmable offset capacitor is included to remove the sensor's baseline capacitance and thus reduce the required dynamic range. To reduce offset errors due to charge injection of the switches, the entire system is auto-zeroed. The proposed humidity sensor has been realized in a 0.16- μm CMOS technology. Measurement results show that the CDC performs a 12.5-bit capacitance-to-digital conversion in a measurement time of 0.8 ms, while consuming only 8.6 μA from a 1.2-V supply. This corresponds to a state-of-the-art figure-of-merit of 1.4 pJ/conversion-step. Combined with the co-integrated humidity sensing element, it provides a resolution of 0.05% RH in the range from 30% RH to 100% RH while consuming only 8.3 nJ per measurement, which is an order-of-magnitude less energy than the state-of-the-art.

A wide range sigma—delta fractional-N frequency synthesizer with adaptive frequency calibration

A wide range fractional-N frequency synthesizer in 0.18 μm RF CMOS technology is implemented. A switched-capacitors bank LC-tank VCO and an adaptive frequency calibration technique are used to expand the frequency range. A 16-bit third-order sigma—delta modulator with dither is used to randomize the fractional spur. The active area is 0.6 mm2. The experimental results show the proposed frequency synthesizer consumes 4.3 mA from a single 1.8 V supply voltage except for buffers. The frequency range is 1.44–2.11 GHz and the frequency resolution is less than 0.4 kHz. The phase noise is −94 dBc/Hz @ 100 kHz and −121 dBc/Hz @ 1 MHz at the output of the prescaler with a loop bandwidth of approximately 120 kHz. The performance meets the requirements for the multi-band and multi-mode transceiver applications.

A 2.8–3.2-GHz Fractional-$N$ Digital PLL With ADC-Assisted TDC and Inductively Coupled Fine-Tuning DCO

A 2.8–3.2-GHz fractional- <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$N$</tex> </formula> digital PLL, implemented in 0.18- <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$\mu \hbox{m}$</tex></formula> CMOS, is presented. The PLL architecture has the form of a classic delta-sigma fractional- <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$N$</tex></formula> PLL. A PFD generates up and down pulses from the reference and divided-down digitally controlled oscillator (DCO) clock. The time-to-digital converter (TDC) converts the width of up pulses to digital words. The quantization noise introduced by a third-order delta-sigma modulator through the multi-modulus divider is canceled at the TDC output. A resistively interpolated ADC is employed to boost TDC resolution by a factor of five. A dither-less DCO with an inductively coupled fine-tuned varactor bank improves tuning step-size by a factor of 16.6, to 20 kHz. With a 52-MHz reference clock, a 3.2-GHz output clock, and a loop-bandwidth of 950 kHz, this prototype achieves 230-fs rms jitter, integrated from a 1-kHz to 40-MHz offset, while drawing 17 mW from a 1.8-V supply. The in-band phase noise floor is <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$-\hbox{111.6 dBc/Hz}$</tex></formula> at a 500-kHz offset. The reference spur is <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$-\hbox{75 dBc}$</tex></formula> and the worst-case fractional- <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$N$</tex> </formula> spur, by sweeping the multiplication ratio near 61, is <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$-\hbox{55 dBc}$</tex></formula> . An FOM of <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$-\hbox{240.4 dB}$</tex></formula> is achieved, and this design occupies a core area of 0.62 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\hbox{mm}^{2}$</tex> </formula> .

Extending the Stable Input Range of a Single-Bit Sigma-Delta Modulator with a Saturation Element

This paper presents a simple compensation scheme for extending the stable input range of a single-bit sigma-delta (Σ-Δ) modulator that is normally stabilized in sliding mode. The proposed control scheme requires a saturation element that provides additional feedback to modify and stabilize the modulator loop filter when the modulator is going to lose stability due to large input level. The proposed compensation scheme is easy to implement and is only activated when the input level is exceedingly large, so it does not affect the performance of the modulator with its input in the normal range. A third-order sigma-delta modulator with an extended input range was designed and implemented to demonstrate the practicality of the proposed design. 