Thin Die Research Articles

Specialized Rubbertip and Holder Design for Thin Die Applications

Specialized Rubbertip and Holder Design for Thin Die Applications

Line Stressing Critical Processes Optimization of Scalable Package Passive Device for Successful Production Ramp-up

The technical paper presents a systematic and methodological approach to deal with a new product trend that will be successfully manufactured during assembly production ramp-up. The project is intended to determine the required process flow and machine platforms for high-density and high-complexity scalable device. Critical processes are shown and top reject contributors are addressed through systematic method by using statistical tools and in-depth engineering analysis.
 The Scalable Package Passive Device is one of the newest and latest developed device in the plant, which functions as a diode for mobile and computer applications. The device is considered high density as its 6” single wafer is equivalent to 400,000 units compared to conventional device consisting of only 1,000 units. Moreover, it is considered as a device with high complexity as state-of-the-art platforms are needed to satisfy its output process. Furthermore, the device has a very thin die and with the smallest total package dimension. The process of assembly manufacturing includes a step cutting method of wafers, compression molding, and in-strip testing, which are unlikely to be found on other semiconductor industries. Ultimately, complex errors and top reject contributor of identified critical processes are corrected and the target or required process capability index is effectively achieved.

A Methodical Approach in Critical Processes Optimization of New Scalable Package Semiconductor Device for ESD Applications

The technical paper presents a systematic approach to deal with a new product trend that will survive during assembly production ramp-up. The project was intended to determine the required process flow and platforms for high-density and high-complexity scalable device. Critical processes were shown and top reject contributor was addressed through methodological way by using statistical tools and in depth engineering analysis.The New Scalable Device is one of the newest and latest developed device in the plant, with main application as an Electrostatic Device (ESD) protection device.  The device is considered high density as its 6” single wafer is equivalent to 400,000 units compared to conventional device consisting of only 1,000 units.  Moreover, it is considered as a device with high complexity as state-of-the-art platforms were needed to satisfy its output process.  The device has a very thin die and with the smallest total package dimension. The process of assembly manufacturing includes a step cutting method of wafers, compression molding, and in-strip testing, which are unlikely to be found on other semiconductor industries. Compared to the conventional and universal approach, complex errors and top reject contributor of identified critical processes were corrected and required process capability index was ultimately achieved.

Applicability of Selective Laser Reflow for Thin Die Stacking

Abstract A 3-D packaging approach such as die stacking is an attractive way to package greater functionality and performance into a smaller footprint, often at a reduced overall product cost. Achieving such 3-D integration can however place significant demands on the manufacturing process, often requiring substantial production expense to bond multiple die in a sequential manner. One alternative, potentially offering significant throughput, is the use of selective laser reflow to bond stacked die. This process produces a localized heating of the stacked die sufficient to produce soldered interconnects at the bonding interface but with very short exposure times that minimize the heating of other parts of the assembly and decrease the overall duration of the bonding process. The use of a commercial infrared (IR) laser reflow instrument for the sequential attachment of thin die into a 3-D stack was considered. The bonding technology under study consists of an infrared laser coupled with a custom optics system that allows the laser beam to be shaped into a range of rectangular shapes and sizes. This allows for a single device or target area to be selectively heated and reflowed while other regions in the near vicinity are not. The target reflow area is exposed to a shaped laser beam for a combination of laser powers and exposure times according to the desired thermal profile. The top most materials absorb the IR energy of the incident laser and conduct that thermal energy down to the solder joints and into rest of the assembly. The rates of heat transfer realized depend significantly upon the sample geometry and material composition. Since this produces a highly accelerated reflow, typically 2–8 seconds, the entire process is highly transient in nature. This paper reports on the investigation into the utility of a selective area laser reflow process to sequentially bond thin die into a multi-chip stack. Thin silicon die (~60μm thick) were bonded to a 150μm thick laminate substrate using a selected area laser reflow process. The die interconnects were formed through the soldering of SnAg capped copper pedestals under the local laser heat. First level die were placed onto copper pads on the laminate and then bonded using the laser process. Subsequent die (2nd level) were placed on and bonded to gold plated nickel pad sites on the top of the first level die. At each step of the process the quality of the solder interconnects was examined using optical and electron microscopy. A range of laser profiles were utilized with several different thermal parameters: peak temperatures ranging from 235–255°C, time above liquidus between 1–3 seconds, and a fixed cooling rate of 40°C/s. Control samples of stacked die were assembled using conventional manufacturing techniques to enable direct comparisons of the interconnects and die bonding characteristics.

Si Distribution on Surface of Thin Walled Die casting by Using Al-25%Si Alloy

Si Distribution on Surface of Thin Walled Die casting by Using Al-25%Si Alloy

Challenges in Assembly implementation of ultra-thin profile flipchip package-on-package

Abstract The assembly and structural challenges associated with a low profile bare die flipchip package-on-package (PoP) are reviewed. The PoP was designed to accommodate a JEDEC 256 ball FBGA memory. This dual channel 32-bit LPDDR3 memory package has a unique signal crossing ball arrangement between the Data bus of one channel and the Control/Address (CAS) bus of the other. The ball arrangement presents some crossing challenges for PoP implementation of controller ICs. For timing reasons, the memory controller blocks are traditionally placed together in a central area of the base chip, and signals are routed to line up with the fixed LPDDR3 landing sites. For the dual channel case the routing requires crossing one CAS signal group over the other's data lines. To address this crossing in this product, a copper redistribution layer (RDL) was deployed at the bump stage to bring the appropriate LPDDR3 signals from the controller block to line up with the memory balls. The thick copper RDL/Cu-Pillar arrangement left a 10–13um of dielectric layer over the base die. Because the 0.4mm pitch and clearance requirements of the selected memory package, a very low profile flipchip die standoff was required. The dielectric layers and copper density in RDL had significant impact on the handling of these thinned wafers and die through the assembly processes. Though newer package offerings - like Amkor's Thru Mold Via (TMV) technology or Invensas' Bond Via Array (BVA could have been deployed, a Cu-pillar based bare die flipchip (FCBGA) using a very thin die was selected for its simplicity and lower cost. All package related reliability tests have been completed with success. The process optimization and trade-off needed to achieve success through assembly are discussed in this paper

Non-Conductive Film (NCF) Underfill: Materials, Performance, and Evolution to Next Generation Devices

As packaging technology continues to advance to smaller form factors, 3D chip stacking will become more of a requirement than an option and Non-Conductive Film (NCF) underfills will play a critical role in the assembly process. Capillary Underfills (CUF) have long been the standard method of protecting interconnected solder bumps from stress, moisture and contaminants. They are, however, becoming more problematic with the steady growth of fine pitch copper pillar interconnections. With CUF, there are difficulties related to cleaning flux residues. Handling thin die (<100 μm) before bonding has become increasingly difficult and CUF does not offer support because it is applied after the bonding is completed. There are also bleed issues associated with CUF resins that limit the die spacings that are possible with new designs. NCF underfills, applied as a film laminated to a wafer, offer significant advantages over CUF and other underfill technologies for fine pitch designs. Because NCF is applied via a lamination process to wafers prior to dicing, handling and dispensing of resins is eliminated from the assembly process. Additionally, the lamination of film materials allows for a precise, uniform placement of underfill. Since NCF is applied at the beginning of the assembly process, it is able to support thinned die after backgrinding. NCF's can be self-fluxing and the removal of flux residues is not necessary. Material flow can be precisely controlled during the lamination and bonding steps, thus allowing for tighter keep out zones and closer die spacings. There have been major advances in the development and mechanistic understanding of NCF technology over the past few years. A great deal of work was done in the first stages of the development which demonstrated the potential to achieve good interconnection and high reliability with low voiding on small test vehicles with larger pitch. The NCF approach has now evolved to multiple materials developed to accommodate varying design parameters. This paper will present the development and test results of initial NCF technology applied to a base test vehicle with 1,000 I/O copper pillars and the evolution to the next generation NCF materials for high I/O die assembly (36,000 I/O's). The optimization of the parameters critical to the development of a robust assembly process will be addressed. Specific interactions between the film properties, thermal profile for joining, and the force/bump ratio will be discussed in relation to solder joint formation.

Novel Backside Grinding and Laser Dicing Process for Cu Pillar Generated Low-k Wafer

One of the challenges in using very thin die, which is needed in thin package, is how to dice it cleanly without chipping, delamination of fragile low-k insulation material and contamination of bonding pads. A narrow scribe line is also highly preferable for high wafer area utilization. The authors developed a novel "grooving and stealth laser process" to satisfy all of these criteria. Grooves are formed on test pads in die sawing area by a grooving laser beam, and then a stealth laser beam is focused into the bulk silicon, causing defect regions in the bulk silicon. Dicing tape is expanded so that the wafer breaks into separated dice.

A Methodology for Chip - Package Interaction (CPI) Modeling in 3D IC Structures

Chip-Package Interaction (CPI) is a significant concern for modern electronic devices and this concern is magnified for 3D Stacked IC. Hard bumps, soft dielectrics, thin die and complex geometries of the stacked die require an ability to model and evaluate the interactions and risks. In packaged IC, dissimilar materials along with the thermal history during the assembly process results in significant residual stresses. These stresses can impact process yields, reliability and die electrical performance. Examples of these effects are ball cracking, ILD/ELK cracking or delamination and shifts in the behavior of sensitive devices such as transistors in analog circuits. Traditionally modeling and evaluation of these risks have been handled by different groups/companies (foundry, OSAT, Fabless Device Mfg) and have been hindered by the difficulty of using different tools and more importantly collaborating without revealing proprietary models and process information/recipes. In this paper we present a modeling flow which incorporates a seamless interface between the tools traditionally used for both package and silicon modeling. This is accomplished by utilizing Boundary Conditions (BC's) to act as a hand-off between the two simulation tools. A package level modeling approach is developed incorporating package assembly processes to predict residual stresses at the end of package assembly process. This package level simulator uses a nested sub-modeling approach for detailed extraction of stresses at different locations within BEOL layers of die, u-bumps, and C4 bumps from package level simulations. Additionally, it allows complete flexibility in selecting boundaries at chip-package interface and then the extraction of BC's necessary for die and transistor level simulations. These boundaries for Chip-Package Interaction are selected by the device manufacturer and the output from this simulation is fed into device level simulations. To provide flexibility for the user and to attain quick turnaround time, a web hosted interface is enabled to run package simulations online. The capabilities of this modeling approach are demonstrated by studying the impact of design and material parameters on stresses at various interconnect structures constituting a typical 3D IC stack package. An example of active silicon layer stress correlation from package level model and die-level model will be presented, thus validating this overall modeling flow.

Modeling in the Cloud: Web Hosted CPI Modeling for Fabless Design Houses and OSATs Method for Mechanical Stress Simulation across the Chip & Package Domains in 3D IC's

Chip-Package Interaction (CPI) is a significant concern for modern electronic devices and this concern is magnified for 3D Stacked IC. Hard bumps, soft dielectrics, thin die and complex geometries of the stacked die require ability to model and evaluate the interactions and risks. In packaged IC, dissimilar materials along with the thermal history during the assembly process results in significant residual stresses. These stresses can impact process yields, reliability and die electrical performance. Traditionally modeling and evaluation of these risks have been handled by different groups/companies (foundry, OSAT, Fabless Device Mfg) and have been hindered by the difficulty of using different tools and more importantly collaborating without revealing proprietary models and process information/recipes. In this paper we present a modeling flow which incorporates an interface between the tools traditionally used for both package and silicon modeling. This is accomplished by utilizing Boundary Conditions (BC's) to act as a hand-off between the two simulation tools. A package level modeling approach is developed incorporating package assembly processes to predict residual stresses at the end of package assembly process. It allows flexibility in selecting boundaries at chip-package interface and then the extraction of BC's necessary for die and transistor level simulations. These boundaries for Chip-Package Interaction are selected by the device manufacturer and the output from this simulation is fed into device level simulations. To provide flexibility for the user and to attain quick turnaround time, a web hosted interface is enabled to run package simulations online. Examples are presented to demonstrate the influence and impacts of materials, process recipes and chip/package design; including an example of the flow from package level through silicon electrical level modeling to silicon hardware measurements.

Design and Development of Fine Pitch Copper/Low-K Wafer Level Package

Copper (Cu)/low-dielectric constant (K) structures are desired choices for advanced integrated circuits (ICs) as the IC technology moving towards fine pitch, high speed, increased integration and high performance. Copper interconnects with low-k dielectric material improve the performance of ICs by reducing interconnect the RC delay, the cross talk between the adjacent metal lines and the power loss. However, the packaging of Cu/low-k IC device is a challenge for the packaging industry to integrate these devices without any failure during assembly and reliability. The current work presents, 1) the finite element model (FEM) based parametric study on Cu/low-K wafer level package (WLP) reliability and stresses on Cu/low-K layers, and 2) experimental validation of WLP reliability by fabricating the test chips. FEM modeling and simulation results have shown that high aspect ratio interconnects, thinner die, and thinner printed circuit board can reduce the stress in low-k layer and enhance the board level interconnect reliability. Test chip of 7 mm ? 7 mm size is designed with 128 input/output (I/O) off-chip interconnects at 300-?m pitch in two depopulated rows using redistribution layers (RDL). Test chips are fabricated on 200-mm-diameter wafer with blanket black diamond (BD) low-K layers structure. Two different Pb free solder interconnects, thick copper column of 100 ?m height with SnAg solder cap and SnAg solder bump of 150 ?m height with 5-?m-thick copper under bump metallurgy (UBM), are fabricated. The Cu/low-K test chips are assembled onto a two layer high glass transition temperature (Tg) FR-4 substrate using two different types of no-flow underfills (NFU) to build the test vehicles and assembled test vehicles are subjected to various JEDEC standard reliability tests, and related failure analysis is carried out. Cu/low-k WLP with copper column interconnects without no-flow underfill passed 1000 h high-temperature storage (HTS) test, and passed the JEDEC drop test with no-flow underfill. Thin die test vehicles of Cu column interconnects with no-flow underfill and extra solder shown better thermal cycling (TC) performance and the board level TC performance can be improved further using thicker RDL.

Process Control for Wet Etching for Silicon Wafer Thinning

Thin wafers have become a basic need for a wide variety of new microelectronic products. Thinner die are being required to fit into thinner packages. Wafers that have been thinned using a final wet etch process on the backside have less stress compared with standard mechanical backgrinding. Isotropic wet etching of silicon is typically done with a mixture of nitric and hydrofluoric acids along with the addition of chemicals to adjust for viscosity and surface wettability for single wafer spin processing. As the silicon is etched and incorporated in the etching solution the etch rate will decrease with time. This variation has been modeled. The focus of this paper is to compare the process control techniques for maintaining a consistent etch rate as a function of time and wafers processed. The models allow for either the time to be extended, chemicals to be replenished or a combination of these. Results will be presented including the cost of ownership for each scenario.

The effect of grinding and pelleting of wheat and maize on amino acids true ileal digestibility and endogenous losses in growing pigs

Abstract Two experiments were performed in order to test the effects of grinding and pelleting wheat (experiment 1) or maize (experiment 2) on amino acids (AA) standardized (SID) and true (TID) ileal digestibility. Basal ileal endogenous losses (IEL), used to calculate SID from apparent digestibility, were determined by feeding a protein-free diet. Total IEL required to calculate TID were estimated as the difference between total and dietary losses determined according to the isotope dilution technique using 15N-labeled crops. Wheat and maize were ground to compare two different mean particle sizes (d50 500 μm and 1000 μm). Then, a fraction of the 500-μm mash was further pelleted through two dies of different thicknesses (16 vs. 20 mm for wheat and 16 vs. 24 mm for maize), holes diameter 4 mm in both cases. Cereals were incorporated in 4 isoproteic diets either in mash form (fine vs. coarse mash) or in pelleted form (thin vs. thick die). In experiment 1, wheat was associated with rapeseed meal diets, while in experiment 2, maize was associated with soybean meal. The reduction of wheat particle size affected neither AA SID nor TID. In contrast, the pelleting treatment significantly improved protein and most AA SID and TID. In addition, total IEL of protein and several AA were significantly reduced when the thicker die was used. Numeric improvements of protein and AA SID were observed with reduction of maize particle size and this was associated with a significant decrease in total IEL so that TID was not modified. Further improvements of AA SID and TID occurred with pelleting of maize, without significant effect on IEL regardless of die thickness.

Thermal modeling and management in ultrathin chip stack technology

This paper presents a thermal modeling for power management of a new three-dimensional (3-D) thinned dies stacking process. Besides the high concentration of power dissipating sources, which is the direct consequence of the very interesting integration efficiency increase, this new ultra-compact packaging technology can suffer of the poor thermal conductivity (about 700 times smaller than silicon one) of the benzocyclobutene (BCB) used as both adhesive and planarization layers in each level of the stack. Thermal simulation was conducted using three-dimensional (3-D) FEM tool to analyze the specific behaviors in such stacked structure and to optimize the design rules. This study first describes the heat transfer limitation through the vertical path by examining particularly the case of the high dissipating sources under small area. First results of characterization in transient regime by means of dedicated test device mounted in single level structure are presented. For the design optimization, the thermal draining capabilities of a copper grid or full copper plate embedded in the intermediate layer of stacked structure are evaluated as a function of the technological parameters and the physical properties. It is shown an interest for the transverse heat extraction under the buffer devices dissipating most the power and generally localized in the peripheral zone, and for the temperature uniformization, by heat spreading mechanism, in the localized regions where the attachment of the thin die is altered. Finally, all conclusions of this analysis are used for the quantitative projections of the thermal performance of a first demonstrator based on a three-levels stacking structure for space application.