This paper is addresses the analysis of the super-junction (SJ) concept applied to LDMOS transistors in thin-SOI technology. Extensive numerical simulations have been carried out to investigate their suitability for low-voltage power applications. The static and dynamic performances of different SJLDMOS structures have been studied in comparison with a conventional RESURF LDMOS structure with the same SOI substrate. In order to improve the current-crowding effect at the body/drift region, the inclusion of a trench lateral gate in the SJ structure (TSJLDMOS) is proposed to further decrease the total on-state resistance (Ron) value maintaining the same voltage capability. The increment of the N+ source and N-drift diffusion area overlapping the gate terminal leads to a gate-related capacitance enhancement. Although very low Ron results can be obtained, the capacitance degradation limits the suitability of TSJLDMOS structure in RF power amplifiers.