The thin SOI TGLDMOS transistor: a suitable power structure for low voltage applications

Abstract

This paper is addressed to the analysis of the trench gate LDMOS transistor (TGLDMOS) in a thin SOI technology and to investigate its suitability for low voltage power applications. The static and dynamic performances have been extensively analyzed by means of numerical simulations and compared with a conventional thin SOI power LDMOS transistor. The specific on-state resistance of the analyzed TGLDMOS structure is lower than that of the LDMOS counterpart, but the structure design has to be optimized to minimize the added contributions to the parasitic capacitances. In this sense, a modified TGLDMOS is also proposed to reduce the gate–drain capacitance and to increase the frequency capability. The expected electrical performance improvements of both TGLDMOS and modified TGLDMOS power transistors corroborate their suitability for 80 V switching and amplifying applications.