Analysis of Trench Gate Power LDMOS Transistors in Thin SOI Technology

Abstract

The on-state performance of conventional thin SOI power LDMOS transistors can be further improved by implementing a wide trench gate partially filled with polysilicon, leading to asymmetric oxide characteristics. The on-state resistance of the analyzed TGLDMOS structure is lower than that of the LDMOS counterpart, but the structure design has to be optimized to minimize the added contributions to the parasitic capacitances. For this purpose, a modified TGLDMOS is proposed to reduce the gate-drain capacitance and to increase the cut-off frequency. The trench is modeled and simulated in this work with special emphasis on the gate-drain capacitance. An extensive simulation study has corroborated the expected electrical performance improvements of both TGLDMOS and modified TGLDMOS power transistors for 80 V switching and amplifying applications.