Thin Silicon-on-insulator Layers Research Articles

High-Voltage Electron Injection Enhanced TC-LIGBT on 1.5- $\mu \text{m}$ -Thin SOI Layer for Reducing the Forward Voltage Drop

In this paper, a new high-voltage electron injection enhanced tridimensional channel lateral insulated gate bipolar transistor (EIETC-LIGBT) on 1.5- $\mu \text{m}$ -thin silicon-on-insulator (SOI) layer is proposed to reduce the forward voltage drop. Based on the previous TC-LIGBT we have proposed, an extra floating p-layer is added at the emitter side of the proposed EIETC-LIGBT. The region locating between the separated p-body cells and the floating p-layer is the high doped n-type electron injection efficiency modulation (EIEM) region. Above the EIEM region, several virtual polygate structures connected to the emitter are fabricated between the separated p-body cells and the floating p-layer. The highly doped EIEM region can help the proposed structure to reduce the forward voltage drop by increasing the electron injection efficiency. The virtual gate structures are contributed to the forward-biased safe operating area of the proposed structure. By optimizing the doping of the EIEM region and the width of the virtual gate structures, an EIETC-LIGBT with the forward voltage drop of 3.4 V at $V_{\mathrm {{GE}}}= 10$ V and $J_{\mathrm {{CE}}}= 100$ A/cm $^{\mathrm {{2}}}$ can be achieved, which has an improvement of 17% compared with the previous TC-LIGBT structure on the same thin SOI layer without sacrificing the current capability.

TC-LIGBTs on the Thin SoI Layer for the High Voltage Monolithic ICs With High Current Density and Latch-Up Immunity

A new 700 V tridimensional channel-lateral insulated-gate bipolar transistor (TC-LIGBT) structure on 1.5-μm-thin silicon on insulator (SoI) layer is presented in detail in this paper. There are numerous separated p-body cells located in the emitter region of the investigated TC-LIGBT, which can increase the efficient channel width, enhance electron injection, and attain a large current capability. By optimizing the doping of the middle doped n-type region between the adjacent p-body cells, a large current density of 568 A/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> at VGE = 10 V, VCE = 20 V can be achieved, which has an improvement of 118% compared with the conventional SoI-LIGBT structure on the same thin SoI layer. To improve the latch-up capability, a highly doped p-buried layer has also been formed underneath the emitter region using 450-keV high-energy ion implantation. In this way, the proposed new TC-LIGBT can achieve almost the same latch-up immunity capability as with the conventional SoI-LIGBT structure.

Compact Modeling of SOI MOSFETs With Ultrathin Silicon and BOX Layers

The reported compact SOI-MOSFET model hiroshima university starc igfet model-silicon on thin buried oxide (HiSIM-SOTB) has been developed for devices with ultrathin silicon on insulator (SOI) and buried oxide (BOX) layers. The potential distribution determined by the Poisson equation is accurately solved with the Newton iteration method across the SOI layer and in the substrate on the backside of the BOX for source and drain side of the device. All charges including accumulation and inversion charges on both side of the BOX are explicitly considered in the Poisson equation. It is found that different from the double-gate MOSFET, the influence of the impurity concentration of the bulk substrate below the BOX must be also explicitly considered to capture all measured properties of the silicon on thin buried oxide (SOTB) MOSFET. A further modeling challenge of the thin SOI and BOX layers, which had to be overcome, is that charge neutrality is not independently preserved at the front-gate oxide or at BOX side, but only totally within the whole device. Additionally it is found that, due to the consistent potential- and charge-based model formulation, the developed HiSIM-SOTB model can reproduce not only TCAD and measured SOTB device data but is even capable to predict the effects of structural variations, including the limiting case of the double-gate MOSFET structure.

Electron mobility enhancement in nanoscale silicon-on-insulator diffusion layers with high doping concentration of greater than 1 × 1018 cm−3 and silicon-on-insulator thickness of less than 10 nm

Electron mobility in nanoscale silicon-on-insulator (SOI) layers with a doping concentration ranging from 2 × 1017 cm−3 to 1 × 1019 cm−3 is thoroughly studied. We observe that electron mobility in highly doped nanoscale extremely thin SOI (ETSOI) layers with thicknesses ranging from 5 to 11 nm is greater than electron mobility in bulk Si with the same doping concentration. Since no dopant ion exists in the oxides above and below ETSOI, the absence of ions close to the ETSOI layers effectively reduces the number of Coulomb centers that scatter carriers in the ETSOI layers. We show that the ratio of SOI thickness to the average distance between donor ions is critically important to understand the mobility enhancement in nanoscale ETSOI. It is demonstrated that mobility enhancement can be universally described as a function of the ratio described above. The findings of our study are indispensable in designing aggressively scaled SOI metal-oxide-semiconductor field-effect transistors.

Significance of the interface regarding magnetic properties of manganese nanosilicide in silicon

Magnetic properties of manganese (Mn) nanosilicide embedded in thin silicon-on-insulator (SOI) layers are investigated. Mn nanosilicide formed by Mn + ion implantation into a thin SOI layer followed by a thermal annealing at 600–900 °C shows soft ferromagnetism or superparamagnetism at 5 K. A monotonic decrease of the saturation magnetization is observed with increasing temperature for post implantation annealing and consequently with increasing mean particle size of nanosilicide. In addition, the magnetization is found to be enhanced when the Si surrounding the Mn nanosilicide is selectively removed. These results indicate that the magnetic moment indeed arises from the nanosilicide and is sensitive to the interface conditions.

A new measurement technique for the characterization of carrier lifetime in thin SOI MOSFETs

We demonstrated a new application of body current to quantitative characterization of carrier lifetime in thin silicon-on-insulator (SOI) films. Previously, we have characterized the energy distribution of trap density in fully depleted (FD) SOI metal oxide semiconductor field effect transistors (MOSFETs), and furthermore, we have demonstrated that recombination at SOI/buried oxide (BOX) interface can suppress kink effect. However, little is known about electronic properties of thin SOI layers. Hence, in this study, we proposed a new electric measurement technique for characterizing recombination lifetime in thin SOI layers from body currents of MOSFETs. We investigated the dependence of inverse hole lifetime 1/ τ h on substrate bias V sub. Furthermore, we considered that the converged value gives the lifetime of bulk recombination, τ bulk, while the variation of 1/ τ h gives the lifetime of surface recombination, τ surface. We also succeeded in reproducing the tendency of 1/ τ h– V sub curves by numerical 3D device simulation. Our approach could separate the effect of bulk recombination and that of surface recombination on SOI layers.

Contactless characterization of surface and interface band-bending in Silicon-On-Insulator (SOI) structures

The Kelvin-probe method is capable of determining electrical properties of the near-surface region of the SOI material as well as the BOX–substrate interface without any device preparation process and completely in a nondestructive manner. It is shown that a simple sandwich-type electrode configuration can be used for the contactless characterization of the SOI layer, when the capacitance between the vibrating electrode and the SOI surface is much smaller than the buried-oxide (BOX) and depletion-layer series capacitances. With the use of ultraviolet (UV) light source for the surface-photovoltage (SPV) measurement, the surface band-bending of very thin SOI layers can be characterized, while infrared (IR)-illumination is capable of searching deeper region.

Crystallographic defects in thermally oxidized wafer bonded silicon on insulator (SOI) substrates

The crystalline quality of wafer bonded (WB) silicon on insulator (SOI) structures thermal treated in dry oxygen ambients has been investigated by means of transmission electron microscopy and defect etching. The main crystallographic defects present in the SOI layers are dislocations, amorphous precipitates, and oxidation induced stacking faults (OISF). The evolution of the OISFs with time and temperature has also been investigated. The main feature observed is that the OISF in WB SOI structures undergo a retrogrowth process at temperatures around T = 1195°C for times of t = 2h. This result is very similar to that recently reported for oxygen implanted SOI (SIMOX) but considerably different from that observed in bulk silicon. The experimental data fits nicely a model recently proposed for the retrogrowth of OISF in thin SOI layers. This model considers that the self-interstitial supersaturation is considerably reduced compared to bulk silicon due to the relative fast point defect recombination inside the top silicon layer.

Method for Measuring Deep Levels in Thin Silicon‐on‐Insulator Layer Without Any Interface Effects

A method for accurate measurement of deep levels in a thin silicon‐on‐insulator (SOI) layer by the capacitance deep level transient spectroscopy (DLTS) is proposed. The proposed method uses a vertical capacitor structure consisting of a Schottky contact an n‐type SOI layer, a buried oxide (BOX) layer, a p‐type substrate silicon layer, and a back‐side ohmic contact With this structure, the high series resistance problems inherent in a horizontal SOI capacitor structure are reduced and the charge coupling problems inherent in a conventional vertical SOI capacitor structure are solved by biasing both interfaces of the BOX layer into the accumulation region. Also, the bulk properties of the SOI layer are decoupled from the effects of surface traps by the space‐charge region formed at the Schottky contact. For a thin SOI layer fabricated with medium dose oxygen ion implantation, two distinct deep levels are observed at the levels of 0.33 and 0.40 eV below the conduction bandedge with corresponding concentrations of and , respectively. From experimental data and comparison with other reported deep levels, it is concluded that the oxygen implantation induced crystalline defects are responsible for the source of these deep levels.

A pH-Controlled Chemical Mechanical Polishing Method for Thin Bonded Silicon-on-Insulator Wafers

A pH-controlled chemical mechanical polishing (CMP) method for fabricating largearea ultrathin silicon-on-insulator (SOI) layers with uniform thickness was developed. Using a polishing reagent with the pH and colloidal silica concentration lowered, together with grooves fabricated on the SOI layer to expose the insulating oxide, the polishing rate clearly decreased leaving a uniform 0.1-µ m-thick SOI layer. An SOI layer with superior thickness uniformity (±0.01 µ m) across 5-by-5-mm SOI-Si islands was obtained. The thickness uniformity across the wafers was decreased to ±0.07 µ m. In this technique, the end point for polishing was controlled to form thin SOI layers with uniform thickness.