Thin Silicon Channel Research Articles

Full-Length Single Protein Molecules Tracking and Counting in Thin Silicon Channels.

Emerging single-molecule protein sensing techniques are ushering in a transformative era in biomedical research. Nevertheless, challenges persist in realizing ultra-fast full-length protein sensing, including loss of molecular integrity due to protein fragmentation, biases introduced by antibodies affinity, identification of proteoforms, and low throughputs. Here, a single-molecule method for parallel protein separation and tracking is introduced, yielding multi-dimensional molecular properties used for their identification. Proteins are tagged by chemo-selective dual amino-acid specific labels and are electrophoretically separated by their mass/charge in custom-designed thin silicon channel with subwavelength height. This approach allows analysis of thousands of individual proteins within a few minutes by tracking their motion during the migration. The power of the method is demonstrated by quantifying a cytokine panel for host-response discrimination between viral and bacterial infections. Moreover, it is shown that two clinically-relevant splice isoforms of Vascular endothelial growth factor (VEGF) can be accurately quantified from human serum samples. Being non-destructive and compatible with full-length intact proteins, this method opens up ways for antibody-free single-protein molecule quantification.

(Invited) SiGe/SOI System: Mechanisms of Condensation and Strain Relaxation

Silicon-Germanium strain engineering has been used for more than two decades in silicon based devices and has contributed to the scaling down of a transistor’s size and to significant improvements in device performance. However, while conventional silicon-germanium based electronics has experienced rapid and steady growth, thanks to this continuous miniaturization of transistors, this trend cannot continue indefinitely. Industry has already moved to alternate methods such as FinFET devices, in which a thin silicon channel is placed vertically, and the FD-SOI (FD-SGOI) design consisting of a thin film Si(SiGe) channel placed horizontally. For nodes scaled down below 28 nm, low power operation will be inherently hindered by both the imperfect interface, non-uniformity of ultra-thin films and quantum confinement effects, which increase the effective bandgap. In these devices, despite the intense research activity on the strained SiGe ultra-thin body, which accounts for a large portion of such microelectronic devices (below the 45 nm node), we still fail to properly understand the mechanisms that limit hole and electron mobilities in SGOI layers. In addition, one of the main challenges for Si based devices remains the fabrication of efficient group-IV photon sources / photon detectors compatible with the microelectronic industry, which would usefully replace the integration of III-V heterostructures on Si. The major bottleneck is that group-IV semiconductor elements have indirect bandgaps, but with possibilities of being transformed to direct bandgaps using strain engineering strategies.In this presentation, we will review the formation mechanism of Ge-rich layers on SOI by condensation at different temperatures. TEM cross-section and GPA analysis of the heterostructures will be presented. We will also report the physical and optical properties of these heterostructures. Special attention is devoted to the influence of the SiGe thickness reduction (up to few MLs), where quantum confinement is prominent in the optical properties of the layers. Raman and PL results will be presented to better explain such confinement behavior. We show that novel SGOI substrates could represent a key strategy for the fabrication of future photonic devices.

(Invited) New Strategies to Produce Light Emitters with Si-based Nanostructures

Silicon-Germanium strain engineering has been used for more than two decades in silicon based devices and has contributed to the scaling down of a transistor’s size and to significant improvements in device performance. However, while conventional silicon-germanium based electronics has experienced rapid and steady growth, thanks to this continuous miniaturization of transistors, this trend cannot continue indefinitely. Industry has already moved to alternate methods such as FinFET devices, in which a thin silicon channel is placed vertically, and the FD-SOI (FD-SGOI) design consisting of a thin film Si(SiGe) channel placed horizontally. For nodes scaled down below 28 nm, low power operation will be inherently hindered by both the imperfect interface, non-uniformity of ultra-thin films and quantum confinement effects, which increase the effective bandgap. In these devices, despite the intense research activity on the strained SiGe ultra-thin body, which accounts for a large portion of such microelectronic devices (below the 45 nm node), we still fail to properly understand the mechanisms that limit hole and electron mobilities in SGOI layers. In addition, one of the main challenges for Si based devices remains the fabrication of efficient group-IV photon sources / photon detectors compatible with the microelectronic industry, which would usefully replace the integration of III-V heterostructures on Si. The major bottleneck is that group-IV semiconductor elements have indirect bandgaps, but with possibilities of being transformed to direct bandgaps using strain engineering strategies.In this presentation, we will review the formation mechanism of Ge-rich layers on SOI by condensation at different temperatures. TEM cross-section and GPA analysis of the heterostructures will be presented. We will also report the physical and optical properties of these heterostructures. Special attention is devoted to the influence of the SiGe thickness reduction (up to few MLs), where quantum confinement is prominent in the optical properties of the layers. Raman and PL results will be presented to better explain such confinement behavior. We show that novel SGOI substrates could represent a key strategy for the fabrication of future photonic devices.

Low Power FDSOI Technology and Devices for RF Applications

: We report RF Characteristics in a Low Power High Performance Ultra-thin Body and Box (UTBB) FDSOI technology. The technology features Si-Channel nFETs and SiGe-Channel pFETS, a gate first HiKMG stack with a gate length (LG) of 20nm, BOX thickness (TBOX) of 20nm and is similar to that described previously[1]. The use of the backgate gate is shown to dynamically change the operating range and expand the dynamic range for RF. Competitive f T s are reported for nFETs. The thin body architecture demonstrates high self gain. The technology is shown to be well optimized for applications like IoT where low power and RF performance are a premium. UTBB FDSOI technology offers a superior technology for IoT because of the low power performance of the technology and RF performance. A TEM micrograph of the nFET silicon channel and pFET SiGe channel is sown in Figure 1. The high K metal Gate, thin channel silicon and SiGe channel, and raised source drains architecture can be seen clearly seen in the tem Micrographs. The FDSOI transistor has a back gate electrode which provides a unique capability to shift the threshold voltage and operating point of the transistor. This capability is shown in Fig. 2 and Fig. 3 which is a linear plot of Id versus Vgs for Vbg = -2, 0, and 2 Volt bias for the nFET and pFET respectively. The Drain current is well behaved and is shown to shift as the back bias changes the threshold voltage. The digital low power performance of the technology is derived by the absence of drain to source leakage path and a steep subthreshold slope. The thin silicon channel and SiGe channel of 7nm prevents a leakage path and provides a fully depleted channel with superior electrostatics The technology Idsat current reaches 900μA/μm and 670μA/μm for NFET and PFET respectively, at off current (Ioff) of 100nA/μm and Vdd of 0.8V. The Log Id vs Vgs plots for the nFET and pFET are shown in Fig. 4 at a gate length of 20nm. The subthreshold slope of 85 mV/decade demonstrates the steep subthreshold that enables a low threshold voltage to be maintained with low leakage. The output characteristic for nFET Lg=30nm is shown in Fig. 5. The flat shape of the curve also indicates both nFET has low gDs. Out conductance curves (not shown here) show no roll-off at high Vd indicating little if any self heating. In this FDSOI technology the nFET tansconductance reaches gM ~ 1.8mS/um at Lg=20nm and the pFET transconductance reaches gMsat ~ 1.2.mS/um. The gMsat operating point may be adjusted with back gate bias as is shown in Fig. 6 for the nFET with a back gate bias with -2, 0, and 2 volts. The ratio of gMsat/gDS is the self gain wich is enhanced in fully depleted FDSOI technology. The self gain for the nFET is shown in Figure 7 with a back gate bias with -2, 0, and 2 volts. RF Performance is extremely important for IoT and other applications. The RF simulated RF performance of the nFET achieves a peak f T of over 300 GHz as is shown in Figure 8 which plots f T vs Vgs for Vbg = -2, 0, and 2 Volts. Note how the operating point can be moved around just as in the gMsat figure by applying the appropriate back gate bias. This expanded dynamic range is also true for the pFET operation. These are the first FDSOI RF characterization results published on a 20nm Lgate HiKMG process.

Subthreshold behavior models for short-channel junctionless tri-material cylindrical surrounding-gate MOSFET

A novel junctionless tri-material cylindrical surrounding-gate (JLTMCSG) MOSFET is presented in this paper. The subthreshold behavior of JLTMCSG MOSFET is investigated by developing physical based analytical models for channel electrostatic potential, horizontal electric field, and subthreshold current. It is revealed that JLTMCSG MOSFET can effectively suppress DIBL and simultaneously improve carrier transport efficiency. It is also found that subthreshold current for JLTMCSG MOSFET can be significantly reduced by adopting both a small oxide thickness and a thin silicon channel. The accuracy of analytical model is verified by its good agreement with the three-dimensional numerical device simulator ISE.

A two-dimensional analytical subthreshold behavior model for junctionless dual-material cylindrical surrounding-gate MOSFETs

A two-dimensional analytical subthreshold behavior model for junctionless dual-material cylindrical surrounding-gate (JLDMCSG) metal-oxide-semiconductor field-effect transistors (MOSFETs) is proposed. It is derived by solving the two-dimensional Poisson's equation in two continuous cylindrical regions with any simplifying assumption. Using this analytical model, the subthreshold characteristics of JLDMCSG MOSFETs are investigated in terms of channel electrostatic potential, horizontal electric field, and subthreshold current. Compared to junctionless single-material cylindrical surrounding-gate MOSFETs, JLDMCSG MOSFETs can effectively suppress short-channel effects and simultaneously improve carrier transport efficiency. It is found that the subthreshold current of JLDMCSG MOSFETs can be significantly reduced by adopting both a thin oxide and thin silicon channel. The accuracy of the analytical model is verified by its good agreement with the three-dimensional numerical simulator ISE TCAD.

Dielectric constants of atomically thin silicon channels with double gate

Dielectric constants of Si (111) nanofilms with the double gate are studied in the full inversion regime by using the first-principles calculation. The calculations show that the dielectric constants are significantly smaller than that of the bulk. Further, the dielectric constants depend on the conduction type as well as on the film thickness. They also oscillate with a 2-bilayer-thickness for the p-channel case as the film thickness decreases. The suppressed dielectric constants are found in the channel center as well as in the channel surface. These findings open the way to artificial control of the dielectric constant in semiconductor nanostructures.

Mobility extraction in SOI MOSFETs with sub 1 nm body thickness

In this work we discuss limitations of the split-CV method when it is used for extracting carrier mobilities in devices with thin silicon channels like FinFETs, ultra thin body silicon-on-insulator (UTB-SOI) transistors and nanowire MOSFETs. We show that the high series resistance may cause frequency dispersion during the split-CV measurements, which leads to underestimating the inversion charge density and hence overestimating mobility. We demonstrate this effect by comparing UTB-SOI transistors with both recessed-gate UTB-SOI devices and thicker conventional SOI MOSFETs. In addition, the intrinsic high series access resistance in UTB-SOI MOSFETs can potentially lead to an overestimation of the effective internal source/drain voltage, which in turn results in a severe underestimation of the carrier mobility. A specific MOSFET test structure that includes additional 4-point probe channel contacts is demonstrated to circumvent this problem. Finally, we accurately extract mobility in UTB-SOI transistors down to 0.9 nm silicon film thickness (four atomic layers) by utilizing the 4-point probe method and carefully choosing adequate frequencies for the split-CV measurements. It is found that in such thin silicon film thicknesses quantum mechanical effects shift the threshold voltage and degrade mobility.

First-principles study on inversion layer properties of double-gate atomically thin silicon channels

The inversion layer properties of double-gate atomically thin silicon channels are studied based on the first-principles enforced Fermi energy difference method. The calculated results indicate that the atomic-scale thickness of the channel significantly affects the inversion layer capacitance as well as the inversion layer carrier properties. They also indicate that the first-principles approach is essential and practical for studying the device physics of the field effect transistors with nanometer-scale channels.

Strained-Si Channel Super-Self-Aligned Back-Gate/Double-Gate Planar Transistors

We present a reproducible approach to the fabrication of super-self-aligned back-gate/double-gate n-channel and p-channel transistors with thin silicon channels and thick source/drain polysilicon regions. The device structure provides capability for scalable control of channel electrostatics, threshold variability without sacrificing source/drain series resistance, and capability of introducing strain to improve carrier transport. The separate device, circuit, and functional level back-gate access that is available through bottom interconnection also provides capability for adaptive power control and novel circuit design. Both n-channel and p-channel devices are demonstrated with the threshold tuning capability

Pushing CMOS beyond the roadmap

Today, the 90 nm generation is in production and in spite of many roadblocks, the latest ITRS 04 expects that CMOS can be scaled down to the 22 nm node and beyond. However, for conventional bulk CMOS serious challenges are evident and new transistors with better electrostatic channel control, lower off-currents and higher on-currents will be needed. Among them, multi-gate devices with very thin silicon channels are most promising. Several architectures like FinFET, Wafer Bonded Double Gate and SON Gate All Around have been demonstrated with good electrical characteristics at gate lengths of 25–10 nm. Under certain assumptions for the SD regions, quantum mechanical simulations predict that silicon MOSFETs can be functional down to 2 nm gate length. Multi-gate transistors have also been implemented in high density Flash memory cells down to 20 nm. Large V t shifts suitable for multi-level storage were achieved. Therefore, it seems very realistic that the device roadmap will not end at the 22 nm node. Assuming that manufacturing and cost issues can be fulfilled, CMOS will continue to dominate in the nanoelectronics era.

Mechanical and Electrical Analysis of Strained Liner Effect in 35 nm Fully Depleted Silicon-on-Insulator Devices with Ultra Thin Silicon Channels

We study the effects of a strained contact etch stop layer (CESL) on fully depleted (FD) silicon-on-insulator (SOI) devices with ultra thin silicon channels. As expected from extensive simulation analysis, the electrical results demonstrate that in spite of the raised source/drain architecture, the stress is effectively transferred from the liner into the underlying channel. Using a tensile liner for the n-type metal–oxide–semiconductor field effect transistor (nMOS) and a compressive liner for the p-type metal–oxide–semiconductor field effect transistor (pMOS), transistor performance enhancements of 10% and 17%, respectively, were obtained. Moreover, with a tensile (/compressive) liner, tensile (/compressive) edge effects become dominant for short devices whereas the stress becomes less tensile (/compressive) for longer devices. Indeed, the balance between these two contributions and the strain level in the channel are highly dependent on geometrical parameters (W, Lgate).

Super-self-aligned back-gate∕double-gate planar transistors: Novel fabrication approach

This work presents a reproducible, super-self-aligned approach for fabricating back-gate∕double-gate transistors with a thin silicon channel and thick doped source∕drain polysilicon access regions. Such a device structure can lead to ultimate electrostatic control of the channel without sacrificing source∕drain series resistance in a deeply scaled field effect transistor. The approach consists of a unique combination of silicon complementary-metal-oxide-semiconductor front-end processing techniques, along with wafer bonding, sidewall spacer formation (in oxide and nitride), solid-state junction diffusion, and multistage chemical mechanical polishing for wafer-level planarization. The authors further demonstrate the formation of a reliable contact at the source∕drain junction interface between doped polysilicon and the undoped silicon channel. In the design, through oxidation, the authors are able to introduce strain in the structure, as well as buried interconnects in a plane below the device. Both n-chan...

A Nanoscale Memory and Transistor Using Backside Trapping

We report results on a new structure that provides a scalable memory cell and a scalable transistor simultaneously in the same structure. The operational distinction is achieved through a difference in the bias range. The device employs a modified silicon-on-insulator substrate where charge is stored in a defected region underneath a thin single-crystal silicon layer employed for the formation of the transistor channel. At low voltages (below 1.5 V), the device operates as a transistor making use of the front silicon interface (preferred form), or the back interface, or both. The memory operation is obtained by use of high voltages, which allow injection of charge into the defected region in a stack of insulating films underneath the thin silicon channel, as well as the removal of the charge. The transistors are scalable because of the thin silicon technology and the memories are highly scalable because they allow efficient coupling between the carriers and storage region. The structure provides for a very useful decoupling of the memory read and transistor operation from the memory electrical storage operation. The experimental operation of the devices is described.