Mechanical and Electrical Analysis of Strained Liner Effect in 35 nm Fully Depleted Silicon-on-Insulator Devices with Ultra Thin Silicon Channels

Abstract

We study the effects of a strained contact etch stop layer (CESL) on fully depleted (FD) silicon-on-insulator (SOI) devices with ultra thin silicon channels. As expected from extensive simulation analysis, the electrical results demonstrate that in spite of the raised source/drain architecture, the stress is effectively transferred from the liner into the underlying channel. Using a tensile liner for the n-type metal–oxide–semiconductor field effect transistor (nMOS) and a compressive liner for the p-type metal–oxide–semiconductor field effect transistor (pMOS), transistor performance enhancements of 10% and 17%, respectively, were obtained. Moreover, with a tensile (/compressive) liner, tensile (/compressive) edge effects become dominant for short devices whereas the stress becomes less tensile (/compressive) for longer devices. Indeed, the balance between these two contributions and the strain level in the channel are highly dependent on geometrical parameters (W, Lgate).