Model For Thin-film Transistors Research Articles

Multi-project wafers for flexible thin-film electronics by independent foundries

Flexible and large-area electronics rely on thin-film transistors (TFTs) to make displays1–3, large-area image sensors4–6, microprocessors7–11, wearable healthcare patches12–15, digital microfluidics16,17 and more. Although silicon-based complementary metal–oxide–semiconductor (CMOS) chips are manufactured using several dies on a single wafer and the multi-project wafer concept enables the aggregation of various CMOS chip designs within the same die, TFT fabrication is currently lacking a fully verified, universal design approach. This increases the cost and complexity of manufacturing TFT-based flexible electronics, slowing down their integration into more mature applications and limiting the design complexity achievable by foundries. Here we show a stable and high-yield TFT platform for the fabless manufacturing of two mainstream TFT technologies, wafer-based amorphous indium–gallium–zinc oxide and panel-based low-temperature polycrystalline silicon, two key TFT technologies applicable to flexible substrates. We have designed the iconic 6502 microprocessor in both technologies as a use case to demonstrate and expand the multi-project wafer approach. Enabling the foundry model for TFTs, as an analogy of silicon CMOS technologies, can accelerate the growth and development of applications and technologies based on these devices.

Compact modeling of hysteresis in organic thin-film transistors

In this work, we propose a model that describes the temporal evolution of the threshold voltage and trapped charge density in Thin-Film Transistors (TFTs) under dynamic conditions, paving the way for the characterization and modeling of memory transistors. The model is expressed as a first-order differential equation for the trapped charge density, which is controlled by a time constant and an independent term proportional to the drain current. The time-dependent threshold voltage is introduced in a previously developed compact model for TFTs with special consideration to the contact effects. The combination of both models and the use of an evolutionary parameter extraction procedure allow for reproducing the experimental dynamic behavior of TFTs. The results of the model and the evolutionary procedure have been validated with published experimental data of pentacene-based transistors. The procedure is able to simultaneously reproduce three kinds of experiments with different initialization routines and constraints in each of them: output and transfer characteristics with hysteresis and current transients characteristics.

Adaptation and comparative analysis of HSPICE level‐61 and level‐62 model for a‐IGZO thin film transistors

AbstractThis paper presents a Computer‐aided design (CAD) model for a‐IGZO thin film transistors (TFTs) by adapting SPICE level‐61 RPI a‐Si: H (Hydrogenated Amorphous Silicon) TFT model and level‐62 RPI Poly‐Si (Poly Silicon) TFT model. This work provides a complete understanding of SPICE level‐61 and 62 model parameters, which must be tuned for a‐IGZO TFT simulation. The adapted SPICE models of level‐61 and level‐62 could model all regions of operation of the TFT, that is, above‐threshold and below‐threshold regions. Adapted RPI poly‐Si model also shows the kink effect in ZnO thin film transistors (TFTs) due to the recombination of electron–hole pairs in the channel via boundary trap states present in the poly‐Si TFTs thereby increasing the drain current in the transistors above pinch‐off region. The extracted performance parameters of the adapted models were found to be contiguous with experimental results. The maximum deviation in the subthreshold slope is approximately 5 mV/decade for level‐61 a‐Si TFT, and for level‐62 poly‐Si TFT, deviation in the subthreshold slope is even less, that is, 0.2 mV/decade. The experimental and simulated characteristics, extracted on‐to‐off ratio, negative bias reverse saturation current, and threshold voltage were almost similar. However, an average deviation of 2.4% and 2.27% was observed in the output characteristics of the adapted level‐61 and level‐62 models, respectively.

43.2: Parasitic Capacitance Model for BGTC TFTs and Verification Using C‐V Measurements from Devices with Various Channel Dimensions

A model of the accumulation and depletion capacitance for a bottom gate top contact (BGTC) thin film transistors (TFT) with an etch stop layer (ESL) was presented. The model, which includes the parasitic capacitance due to device layout, was verified by comparison of measured data and modeled data for TFTs of various dimensions. Good agreement was seen between measured and modeled data, where the model underestimated the capacitance by 2% to 7%, depending on the device dimensions. The impact of the parasitic capacitance on estimates of the Debye length (λD ) are discussed and it is demonstrated that the relative error in the λD estimates is directly proportional to the ratio of the parasitic capacitance over the measured capacitance (CPAR/CM). The relative error was shown to increase as the ratio increases, leading to a larger underestimation of the λD. It was concluded that the parasitic capacitance to measured capacitance should be minimized for devices that are used for extraction of physical parameters from C‐V data. This is especially important in the case where the λD is a critical parameter in the optimization of TFT performance.

Editors’ Choice—Thin Film Transistor Response in the THz Range

Novel metal oxide materials such as InGaZnO (IGZO), ZnO, SnO, and In2O3 and improved fabrication processes dramatically enhanced the achieved and projected thin film transistor (TFT) performance. The record values of the effective field-effect mobility of Metal Oxide TFT (MOTFT) materials have approached 150 cm2/Vs. We report on an improved compact TFT model based on three models: the RPI TFT model, the unified charge control model (UCCM), and the multi-segment TFT compact model. This improved model accounts for a non-exponential slope in the subthreshold regime by introducing a varying subthreshold slope and accounts for non-trivial capacitance dependence on the gate bias, and parasitic impedances. The analysis of the TFT response using this model and the analytical calculations showed that TFTs could have a significant response to impinging THz and sub-THz radiation. Using a complementary inverter and the phase-matched THz signal feeding significantly improves the detection sensitivity.

A Compact Amorphous In-Ga-Zn-Oxide Thin Film Transistor Pixel Circuit With Two Capacitors for Active Matrix Micro Light-Emitting Diode Displays

In this paper, we propose a novel amorphous In-Ga-Zn-oxide (a-IGZO) thin film transistor (TFT) pixel circuit for pulse width modulation (PWM) driving active matrix micro light-emitting diode (μLED) displays. The proposed pixel circuit compensates for wavelength shifts according to gray level and threshold voltage (VTH) variation of TFTs with only two capacitors. This compact operation can be achieved by simultaneous compensation for VTH along with data input in the constant current generation (CCG) circuit and the PWM circuit, which consist the pixel. Since the VTH variation in TFTs is compensated, the proposed pixel circuit can supply a uniform and stable current to the μLED throughout all gray levels. The compensation accuracy was verified by HSPICE with an oxide TFT model based on the measurement data. In addition, we analyzed the optimization method to improve the PWM driving by controlling the electrical properties of TFT, and verified this approach by simulation.

(Invited) Improved Thin Film Transistor Model Predicts TFT Operation in the THz Range

Novel Thin-film-transistor (TFT) TFT materials such as ZnO, InGaZnO, AMO-CNT, and organic materials dramatically improved the achieved and projected TFT performance. The low field mobility of oxide materials has reached values comparable to those for short-channel Si CMOS. The effects related to electron inertia and electron density oscillations in field effect transistors channels (FETs) diminish the role of the low field mobility as a figure of merit in short channel devices making the performance gap between TFTs and Si CMOS smaller enabling high frequency TFT applications even reaching sub-THz and THz frequencies (for the operating regimes using the rectification of the plasma oscillations. We report on an improved compact model based on the RPI TFT model [1] and using the Unified Charge Control Model (UCCM). [2, 3] This model accounts for a non-exponential slope in the subthreshold regime by introducing a varying subthreshold slope and accounts for non-trivial capacitance dependence on the gate bias. It also accommodates the inclusion of the parasitics related to the gate impedance. These new features allowed us to obtain an excellent agreement with the measured I-V/C-V characteristics for both long and short n-channel and p-channel TFTs. The application of this new TFT model to the analysis of the TFT response requires accounting for non-local potential distribution in the device channel. This is achieved by using a multi-segment nonlinear transmission line model of the TFT channel reproducing the approach that has been previously used for the THz SPICE/ADS Si CMOS model implementation. As a possible application example, we simulated a TFT complementary inverter. Our simulations showed that using the phase-matched THz signal feeding should yield a very sensitive detection of THz radiation impinging on a short channel TFT. These results show that the TFT RFID and other applications could be extended into the THz range of frequencies.

(Invited) Improved Thin Film Transistor Model Predicts TFT Operation in the THz Range

Novel materials such as ZnO, InGaZnO, AMO-CNT, and organic materials and improved fabrication processes dramatically enhanced the achieved and projected thin film transistor (TFT) performance. The effective field-effect mobility of metal oxide TFT materials has reached values comparable to those for short-channel Si CMOS. We report on an improved compact model based on the RPI TFT model, the unified charge control model (UCCM), and the multi-segment TFT compact model. This improved model accounts for a non-exponential slope in the subthreshold regime by introducing a varying subthreshold slope and accounts for non-trivial capacitance dependence on the gate bias. The application of this new TFT model to the analysis of the TFT response showed that a TFT complementary inverter using the phase-matched THz signal feeding should yield a very sensitive detection of THz radiation impinging on a short channel TFT.

A Threshold Voltage Model for AOS TFTs Considering a Wide Range of Tail-State Density and Degeneration

There have been significant differences in principle electrical parameters between amorphous oxide semiconductor (AOS) thin-film transistors (TFTs) and silicon-based devices for their distinct conduction mechanisms. Additionally, threshold voltage is one of the key parameters in device characterization and modeling. In this work, a threshold voltage model is developed for AOS TFTs considering the various density of exponential tail states below the conduction band, including degenerate conduction. The threshold condition is defined where the density ratio of free carriers to the trapped carriers reaches a critical value depending on the distribution parameters of tail states. The resulting threshold voltage expression is fully analytical and is of clear physical meaning, with simple parameter extraction methods. Numerical and experimental verifications show that this model provides appropriate values of threshold voltage for devices with different sub-gap tail states, which could be a useful method for identifying the threshold voltage of a large variety of AOS TFTs.

Extraction of SnO Subbandgap Defect Density by Numerical Modeling of p-Type TFTs

Recently, p-type tin monoxide (SnO) thin-film transistors (TFTs) have gained interest for all-oxide complementary metal–oxide semiconductor (CMOS) circuits for flexible electronics and back-end-of-line integration with Si. However, most SnO TFTs demonstrated so far exhibit a low on– off-current ratio and limited field effect mobility. To understand and improve SnO TFT performance, it is necessary to quantitatively characterize the subbandgap defects in SnO and at its dielectric interface. In this work, we establish numerical models which provide this understanding. By concurrent fitting of simulated <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}_{\text{D}}$ </tex-math></inline-formula> – <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text{GS}}$ </tex-math></inline-formula> and effective mobility versus <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text{GS}}$ </tex-math></inline-formula> to experimentally measured data, we can accurately extract SnO defect state profiles. Using the extracted simulation models, we then identify ways to improve SnO TFT performance. Specifically, a reduction in the density of shallow, bulk Gaussian acceptor states, is necessary to reduce the off-current, while reducing the contact resistance and interface donor-like tail state density can improve the SnO field effect mobility.

Modeling the Short-Channel Effects in Coplanar Organic Thin-Film Transistors

We have developed models for three different short-channel effects [subthreshold-swing degradation, threshold-voltage roll-off, and drain-induced barrier lowering (DIBL)] in coplanar organic thin-film transistors (TFTs) and verified them against the measured current–voltage characteristics of TFTs having channel lengths as small as <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.5 \mu \text{m}$ </tex-math></inline-formula> . To derive the models, the Schwarz–Christoffel transformation was applied to obtain a complex mapping function that links the coplanar device geometry to an equivalent geometry in a different coordinate system in order to solve Laplace’s equation of the 2-D potential problem. The solution to this potential problem serves as the basis for the definition of the short-channel models, which can be incorporated into any compact dc models for coplanar TFTs that use the TFTs’ threshold voltage and subthreshold swing as input parameters. To verify the model, the channel-length-dependent effects were extracted from technology computer-aided design (TCAD) simulations (transfer characteristics and surface-potential profile) and from measurements performed on organic p-channel TFTs fabricated using high-resolution stencil lithography.

Multi-Segment TFT Compact Model for THz Applications.

We present an update of the Rensselaer Polytechnic Institute (RPI) thin-film transistor (TFT) compact model. The updated model implemented in Simulation Program with Integrated Circuit Emphasis (SPICE) accounts for the gate voltage-dependent channel layer thickness, enables the accurate description of the direct current (DC) characteristics, and uses channel segmentation to allow for terahertz (THz) frequency simulations. The model introduces two subthreshold ideality factors to describe the control of the gate voltage on the channel layer and its effect on the drain-to-source current and the channel capacitance. The calculated field distribution in the channel is used to evaluate the channel segment parameters including the segment impedance, kinetic inductance, and gate-to-segment capacitances. Our approach reproduces the conventional RPI TFT model at low frequencies, fits the measured current–voltage characteristics with sufficient accuracy, and extends the RPI TFT model applications into the THz frequency range. Our calculations show that a single TFT or complementary TFTs could efficiently detect the sub-terahertz and terahertz radiation.

An Empirical Modeling of Gate Voltage-Dependent Behaviors of Amorphous Oxide Semiconductor Thin-Film Transistors including Consideration of Contact Resistance and Disorder Effects at Room Temperature.

In this paper, we present an empirical modeling procedure to capture gate bias dependency of amorphous oxide semiconductor (AOS) thin-film transistors (TFTs) while considering contact resistance and disorder effects at room temperature. From the measured transfer characteristics of a pair of TFTs where the channel layer is an amorphous In-Ga-Zn-O (IGZO) AOS, the gate voltage-dependent contact resistance is retrieved with a respective expression derived from the current–voltage relation, which follows a power law as a function of a gate voltage. This additionally allows the accurate extraction of intrinsic channel conductance, in which a disorder effect in the IGZO channel layer is embedded. From the intrinsic channel conductance, the characteristic energy of the band tail states, which represents the degree of channel disorder, can be deduced using the proposed modeling. Finally, the obtained results are also useful for development of an accurate compact TFT model, for which a gate bias-dependent contact resistance and disorder effects are essential.

Surface-potential-based drain current model for two-dimensional organic TFTs using the multiple trapping and release conduction theory

A new analytical surface-potential-based drain current model is presented for the organic thin-film transistors (TFTs) when carriers are confined in two dimensions. Following the carrier multiple trapping and release (MTR) conduction theory, i.e., the assumption that the trapped carrier concentration is much higher than the free carrier concentration, the model is developed. The presented model can account for the linear regime and saturation regime by a single formulation. The calculated results of the presented model are verified by the available experimental drain current considering the temperature characteristics. Comparing with the previous model using the variable range hopping and percolation (VRH) conduction theory, although the presented model and the previous model are similar in mathematics, the presented model is more efficient to estimate the density of trap states for the organic TFTs.

Numerical Analysis of Oxygen-Related Defects in Amorphous In-W-O Nanosheet Thin-Film Transistor.

The integration of 4 nm thick amorphous indium tungsten oxide (a-IWO) and a hafnium oxide (HfO2) high-κ gate dielectric has been demonstrated previously as one of promising amorphous oxide semiconductor (AOS) thin-film transistors (TFTs). In this study, the more positive threshold voltage shift (∆VTH) and reduced ION were observed when increasing the oxygen ratio during a-IWO deposition. Through simple material measurements and Technology Computer Aided Design (TCAD) analysis, the distinct correlation between different chemical species and the corresponding bulk and interface density of states (DOS) parameters were systematically deduced, validating the proposed physical mechanisms with a quantum model for a-IWO nanosheet TFT. The effects of oxygen flow on oxygen interstitial (Oi) defects were numerically proved for modulating bulk dopant concentration Nd and interface density of Gaussian acceptor trap NGA at the front channel, significantly dominating the transfer characteristics of a-IWO TFT. Furthermore, based on the studies of density functional theory (DFT) for the correlation between formation energy Ef of Oi defect and Fermi level (EF) position, we propose a numerical methodology for monitoring the possible concentration distribution of Oi as a function of a bias condition for AOS TFTs.

Gate Voltage Pulse Rising Edge Dependent Dynamic Hot Carrier Degradation in Poly-Si Thin-Film Transistors

Dynamic degradation becomes a critical issue for thin-film transistors (TFTs) used in emerging new displays driven by high frequency gate voltage ${V}_{\text {G}}$ pulses. In this study, ${V}_{\text {G}}$ pulse rising edge dependent dynamic hot carrier degradation of poly-Si TFTs is investigated. It is demonstrated that rising edge of ${V}_{\text {G}}$ pulses which swing within the OFF-state of TFTs causes the degradation, while that of normal ${V}_{\text {G}}$ pulses which switch between the ON and OFF states across the flat band voltage ${V}_{\text {FB}}$ of TFTs does not. Based on transient TCAD simulation, the underlying mechanism of rising edge dependent degradation is proposed, which is based on the non-equilibrium PN junction degradation model previously proposed to explain ${V}_{\text {G}}$ pulse falling edge dependent degradation of poly-Si TFTs. Hence, the dynamic degradation model of poly-Si TFTs related to both rising and falling edge of the ${V}_{\text {G}}$ pulses can be unified now, which is applicable to fast gate pulses with steep rising and/or falling edges in sub- $\mu \text{s}$ level.

(Invited) Versatile Compact Model and Evolutionary Parameter Extraction Method for Organic Thin-Film Transistors

Contact effects in thin-film transistors (TFTs), such as organic (OTFTs) and 2D field-effect transistors (2D-FETs), remain an important problem to be solved. The correct physio-chemical modeling of the contact regions in TFTs is necessary in order to incorporate these effects into transistor compact models [1,2]. Regarding OTFTs, much effort has been made to include contact effects into compact models, since the existence of a standard compact model, which effectively brings together the device- and system-level development, would place the OFET technology at a higher technological level [3].In this work, we present a versatile contact model, which is incorporated into a well-known generic analytical model for the current-voltage (I-V) characteristics of OTFTs, valid for all the operation regions of the transistor, including the subthreshold region [4,5]. The resulting model is complemented with an evolutionary procedure to extract the parameters that best fit experimental current-voltage characteristics [6]. Our motivation is that the combined compact model and parameter extraction method fulfils the conditions for this long expected standard compact model.The versatility of our proposal is based on the following pillars: (i) the contact model must reproduce linear, space-charge-limited and Schottky-barrier contacts [7]; and (ii) the contact model must be applied both, in transistors in which the source contact region is dominant (observed in many OTFTs), and in transistors in which drain and source contacts contribute in a similar way (mainly observed in some staggered OTFTs and 2D-FETs).In this work, we give details of how the compact model, including the contact effects, has been built from its origins [8] up to now. We also describe how the evolutionary procedure is adapted to extract the model parameters of different OTFTs, in which only the source contact, or both source and drain contact effects, limit the device performance [6, 7, 9].Finally, the compact model including contact effects and the extraction procedure mentioned above are tested successfully with coplanar and staggered OTFTs (with and without negligible drain contact effects). Our numerical calculations reproduce quite well the experimental electrical characteristics and the model parameters are extracted. The comparison of our results with other methods designed for specific TFTs confirms the validity of our standard compact model for TFTs with contact effects. Acknowledgments This work was partially financed by the Consejería de Economía y Conocimiento de la Junta de Andalucía, the Spanish “Ministerio de Ciencia, Innovación y Universidades”, and the European Regional Development Funds (ERDF), under projects A-TIC-117-UGR18 and PGC2018-098813-B-C31.

Compact modeling of metal-oxide TFTs based on artificial neural network and improved particle swarm optimization

The application of artificial neural network (ANN) can give a very accurate and fast model for semiconductor devices used in circuit simulations. In this paper, we have applied multi-layer perceptron (MLP) neural network based on limited memory Broyden–Fletcher–Goldfarb–Shanno (L-BFGS) method to model the flexible metal-oxide thin-film transistors (TFTs). An improved particle swarm optimization (PSO) is employed to find suitable initial parameters for the ANN model, which consists of a centroid opposition-based learning algorithm and a mutation strategy based on Euclidean distance to enhance the searching ability further. This hybrid modeling routine can improve the accuracy of predictions of both the I–V and small signal parameters ( $$g_d$$ , $$g_m$$ , etc.) characteristics, which are in good agreement with experimental data and fully demonstrate the validity of the proposed model. Furthermore, the model is implemented into a simulator with Verilog-A. The circuit-level tests of TFT show that the ANN compact model with PSO enables accurate performance estimation of metal-oxide TFT circuits.

A unipolar thin‐film transistor‐based amplifier with enhanced DC offset suppression

This letter proposes a unipolar thin-film transistor (TFT)-based amplifier design that can provide enhanced DC offset suppression. The amplifier consists of an input AC coupling network and a capacitor bootstrap amplifier. By making the first pole of the input AC-coupling network coincide with that of the capacitor bootstrap amplifier, a DC offset suppression capability of 40 dB/dec, which is 2× higher than that of the prior arts, can be obtained. An implementation is also proposed and a Rensselaer Polytechnic Institute (RPI) TFT model whose parameters are turned to fit the measured data of our metal-oxide TFT is used to simulate the circuit. Simulation results show that the implementation has 31 dB midband gain, 0.5 Hz–5 kHz bandwidth, 300 μW power consumptions, and the expected 40 dB/dec DC offset suppression. This design is suitable for applications that need to block large DC interference, such as sensor readout amplifiers.

New Degradation Model of LTPs TFT Aged Off-State Bias Stress on Flexible Substrate

We conducted experimental and quantitative studies on the effects of off-state bias stress of the p-type polycrystalline silicon thin film transistors (TFTs) on flexible substrate and presented a new degradation model using TCAD simulation. In the off-state bias stress condition, the gate induced drain leakage (GIDL) current is determined by the gate and drain voltage (Vgd) and gate bias stress above a certain bias is accompanied by a change in Vth. To understand and model the underlying mechanism of these results, we developed a spatial probability analysis model with mapping of physical quantity (SPAM). The spatial distribution the E-field and the electron concentration are considered as degradation factors, and are used in the equations for defect creation (DC) and charge trapping (CT) TCAD model. We had to implement different forms of aging model in the two regions: 1) CT in poly-Si/SiOX interface, and 2) DC in the channel bulk (especially, the grain boundary). Finally, our new degradation model allows us to analyze how the GIDL current decreases with various aging conditions and provides a quantitative relationship between the amount of charge trapping and the amount of defect creationI. Fixed negative charge (-) of interface of poly-Si/SiOx(ε(x,y) > εC,f and n(x,y)> nC,f)Qfix (-) (x,y)=αf *[{ε(x,y)-εC,f}/εm,f ]γf_field *[log{n(x,y)/nC,f }]γfn II. Ionized defect density of channel bulk (Grain and GB)(ε(x,y,z) > εC,tA ) NtA (-) =gtA (ε)*exp[-{(EtA-EGA)/WGA}2 ]gtA (ε)= αtA*[{ε(x,y,z)-εC,tA}/εm,tAm ]γtA Figure 1