Device Performance Of Thin-film Transistors Research Articles

Electrical performance of La-doped In2O3 thin-film transistors prepared using a solution method for low-voltage driving.

In this paper, La-doped In2O3 thin-film transistors (TFTs) were prepared by using a solution method, and the effects of La doping on the structure, surface morphology, optics, and performance of In2O3 thin films and TFTs were systematically investigated. The oxygen defects concentration decreased from 27.54% to 17.93% when La doping was increased to 10 mol%, and La served as a carrier suppressor, effectively passivating defects such as oxygen defects. In fact, the trap density at the dielectric/channel interface and within the active layer can be effectively reduced using this approach. With the increase of La concentration, the mobility of LaInO TFTs decreases gradually; the threshold voltage is shifted in the positive direction, and the TFT devices are operated in the enhanced mode. The TFT device achieved a subthreshold swing (SS) as low as 0.84 V dec-1, a mobility (μ) of 14.22 cm2 V-1 s-1, a threshold voltage (VTH) of 2.16 V, and a current switching ratio of Ion/Ioff of 105 at a low operating voltage of 1 V. Therefore, regulating the doping concentration of La can greatly enhance the performance of TFT devices, which promotes the application of such devices in high-performance, large-scale, and low-power electronic systems.

Influence of Excess Conjugated Wrapping Polymer in Semiconducting Single-Walled Carbon Nanotube Dispersions

Single-walled carbon nanotubes (SWNTs) are promising nanomaterials for incorporation into organic electronic devices (OEDs), with the potential to fabricate flexible devices while exploiting inexpensive solution-processing techniques. As-synthesized SWNTs are insoluble and comprised of a mixture of metallic and semiconducting SWNTs (sc-SWNTs), necessitating dispersal and purification before integration into OEDs. Refinement of conjugated polymer extraction techniques has allowed for the isolation of sc-SWNTs from metallic in a reproducible and scalable manner. The availability of highly-pure sc-SWNT materials has facilitated the production of thin-film transistors (TFTs) with very high charge carrier mobilities, outperforming organic small molecule and polymer semiconductors. However, the realization of commercial OED applications of polymer-sorted sc-SWNTs have not yet been achieved, partially due to the prohibitive time and materials costs associated with purifying sc-SWNTs.Current protocols for dispersing sc-SWNTs with conjugated polymers involve three broad steps: (1) dispersion of bulk SWNT material, (2) removal of non-dispersed carbonaceous materials, and (3) removal of excess polymer through filtration or centrifugation. The final step of removal of excess polymer is time-consuming and wasteful, but viewed as necessary for preparing high-performing TFTs, as the conjugated polymer has much lower performance compared to SWNTs.In this study we performed the first systematic investigation of the effect of excess polymer on SWNT TFT performance. Three SWNT concentrations were investigated, with varying ratios of excess polymer added to each. TFT device performance was monitored using several metrics, including: mobility, threshold voltage, on/off ratios and hysteresis. Characterization of large numbers of replicate TFT devices determined that below a threshold amount of excess polymer the presence of excess polymer did not have a negative impact on device performance. Detailed analysis of the sc-SWNT films through Raman spectroscopy and atomic force microscopy (AFM) confirmed that a simple rinsing step was sufficient to remove all the unbound conjugated polymer from the substrate surface without affecting the sc-SWNT network. The volume of solvent required for the rinsing step was substantially lower than that required for filtration or centrifugation steps. Furthermore, at higher SWNT concentrations the excess polymer prevented nanotube bundling, resulting in moderate improvements in both mobility and on/off ratios. Our results were reproducible for two different conjugated polymer sc-SWNT systems, demonstrating the versatility of this procedure.

Fabrication and Properties of InGaZnO Thin-Film Transistors Based on a Sol-Gel Method with Different Electrode Patterns.

The preparation of thin-film transistors (TFTs) with InGaZnO (IGZO) channels using sol-gel technology has the advantages of simplicity in terms of process and weak substrate selectivity. We prepared a series of TFT devices with a top contact and bottom gate structure, in which the top contact was divided into rectangular and circular structures of drain/source electrodes. The field-effect performance of TFT devices with circular pattern drain/source electrodes was better than that with a traditional rectangular structure on both substrates. The uniform distribution of the potential in the circular electrode structure was more conducive to the regulation of carriers under the same channel length at different applied voltages. In addition, with the development of transparent substrate devices, we also constructed a hafnium oxide (HfO2) insulation layer and an IGZO active layer on an indium tin oxide conductive substrate, and explored the effect of circular drain/source electrodes on field-effect properties of the semitransparent TFT device. The IGZO deposited on the HfO2 dielectric layer by spin-coating can effectively reduce the surface roughness of the HfO2 layer and optimize the scattering of carriers at the interface in TFT devices.

P‐1.11: High‐mobility ZnO thin‐film transistors with HfO2/Al2O3 bilayer dielectric

We investigate high‐performance ZnO thin‐film transistors (TFTs) with a HfO2/Al2O3 bilayer high‐κ gate dielectric. The effects of atomic layer deposition process temperature (80, 100, 120, and 140 °C) of Al2O3 dielectric layer on device performance of ZnO TFTs are examined. When the process temperature is at 100 °C, the devices show the best electrical properties, such as a field‐effect mobility of 34.12 cm2/Vs, a subthreshold swing of 105.70 mV/decade, and an on‐off current ratio over 108. Besides, of all the devices, TFTs with 100 °C‐Al2O3 show the best stability with 0.2 and –0.1 V threshold voltage shift under positive and negative gate‐bias stress, which may probably due to the high‐quality interface between the active layer and dielectric layer. This work presents great potential of the ZnO TFTs in applications of advanced displays.

P‐10.2: Head Groups influences in Self‐Assembled Monolayer Passivation For Flexible InSnZnO Thin‐Film Transistors†

P‐10.2: Head Groups influences in Self‐Assembled Monolayer Passivation For Flexible InSnZnO Thin‐Film Transistors†

Effects of Channel Thickness on Electrical Performance and Stability of High-Performance InSnO Thin-Film Transistors

InSnO (ITO) thin-film transistors (TFTs) attract much attention in fields of displays and low-cost integrated circuits (IC). In the present work, we demonstrate the high-performance, robust ITO TFTs that fabricated at process temperature no higher than 100 °C. The influences of channel thickness (tITO, respectively, 6, 9, 12, and 15 nm) on device performance and positive bias stress (PBS) stability of the ITO TFTs are examined. We found that content of oxygen defects positively correlates with tITO, leading to increases of both trap states as well as carrier concentration and synthetically determining electrical properties of the ITO TFTs. Interestingly, the ITO TFTs with a tITO of 9 nm exhibit the best performance and PBS stability, and typical electrical properties include a field-effect mobility (µFE) of 37.69 cm2/Vs, a Von of −2.3 V, a SS of 167.49 mV/decade, and an on–off current ratio over 107. This work paves the way for practical application of the ITO TFTs.

Dimensional structure regulation of organic–inorganic hybrid perovskite and its application in thin film transistors

The effects of dimensional structure on the properties of lead iodide perovskite (C8H9NH3)2(CH3NH3) n−1Pb n I3n+1 were investigated. Furthermore, perovskite thin films with different dimensionalities were applied as the channel layer of thin film transistors (TFT). The electrical performance and stability of TFT devices were significantly improved through the regulation of dimensional microstructure of the perovskites. As a result, the quasi-2D (n = 6) perovskite TFTs achieved a field-effect mobility (μ FE) of 3.90 cm2 V−1 s−1, with 104 on-off current ratio and −1.85 V threshold voltage, which can be maintained well after 4 days without degradation at 30% ambient humidity. Moreover, the electrical performance of the TFTs based on Pure-2D and Quasi-2D perovskite also exhibited a good bias stability.

Hybrid Gate Dielectric of MoS2 Transistors for Enhanced Photo‐Electronic Stability

AbstractMoS2 thin‐film transistors (TFTs) have been widely studied for use as driving TFTs of active‐matrix displays considering their outstanding electrical advantages such as high mobility and high on/off current ratio. However, due to the atomically thin nature of MoS2, the device performance of MoS2 TFTs suffers from trap sites at the interface. In this study, a hybrid gate dielectric based on an interface engineering strategy using poly(1,3,5‐trivinyl‐1,3,5‐trimethyl cyclotrisiloxane) (pV3D3) via initiated chemical vapor deposition is investigated to enhance the negative bias illumination stress (NBIS) stability of MoS2 TFTs. Compared to a single oxide dielectric layer (Al2O3), a hybrid dielectric layer (pV3D3/Al2O3) exhibits decreased threshold voltage shift under NBIS by reducing functional groups, such as hydroxyl (OH−) group, which act as charge trapping sites at the interface between the MoS2 channel and the gate dielectric. It is confirmed by quantitative analysis using the stretched‐exponential model. Tau (τ), one of the modeling parameters in the stretched‐exponential model, decreases from 210 to 120 s, indicating the improvement in stability. Furthermore, in a low‐frequency noise (1/f) measurement, hybrid‐dielectric‐based TFTs show an order of magnitude lower noise power spectral density (SID/ID2) than single‐oxide‐dielectric‐based TFTs.

Sn Doping Effects in Solid-Phase Crystallized Ge Thin-Film Transistors

Introduction Low-temperature synthesis of high carrier mobility thin films on insulating substrates is actively being conducted to dramatically improve the device performance of thin-film transistors (TFTs). Ge is one of the candidates for next-generation TFTs because of its high carrier mobility and good compatibility with Si. We recently reported that the densification of amorphous (a-) Ge precursor in solid-phase crystallization (SPC) significantly enlarged the grain size of polycrystalline (poly-) Ge and improved Hall effect hole mobility μ Hall [1]. The TFT using this Ge layer exhibited both high field effect mobility μ FE (170 cm2/Vs) and on/off current ratio I on/I off (~102) without minimizing the channel region (< 1 μm) [2]. The key technology was thinning the 100 nm thick Ge film with a large grain size (3.7 μm) enough to fully deplete the channel. Very recently, we further improved μ Hall by combining the precursor densification method with Sn incorporation in SPC [3,4]. In this study, we fabricate TFT using SPC-GeSn and further improve its performance. Experimental Procedure The a-Ge1−x Sn x (0 ≤ x ≤ 4.5%) precursors were deposited on SiO2 glass substrates using the Knudsen cell of a molecular beam deposition system (base pressure of 5 × 10−7 Pa). The deposition rate of Ge was fixed at 1.0 nm/min at room temperature, whereas that of Sn was adjusted to obtain the targeted GeSn composition. The deposition time was 100 min. The precursors were densified by heating the substrate at 125 °C during deposition [1,3,4]. The samples were then loaded into a conventional tube furnace in an N2 atmosphere annealed at 450 °C for 5 h to induce SPC. The grown layers were analyzed by the electron backscattering diffraction (EBSD) measurement and Hall effect measurement (van der Pauw method).We fabricated accumulation-mode metal source/drain (S/D) p-channel TFTs using SPC-GeSn. Pt and TiN were sequentially formed as a metal S/D and a capping layer, respectively. The PtGe/Ge contacts have low hole barrier height and are suitable for p-channel Ge-TFTs. We used Al/SiO2/Al2O3/SiO2/GeO2 for the gate stack with the equivalent oxide thickness of 17.7 nm. The channel width and length (W/L) were 55 and 5–10 μm, respectively. Here, all process including SPC were conducted below 450 °C. Results and Discussion First, we discuss the crystalline quality and electrical properties of the SPC-GeSn layer. Figure 1(a) shows that the crystal grain size dramatically varies with initial Sn concentration x and maximized at x = 1.6%. These results are roughly consistent with the solid solubility of Sn in Ge of approximately 1%–2%. We thinned x = 1.6% sample with the maximum grain size using chemical-mechanical polishing (CMP) to fabricate TFT for full depletion in poly-GeSn layer. As a reference, we also thinned x = 0% sample. Figure 1(b) shows that hole concentration p is constant in-depth direction although hole mobility μ Hall decreases by thinning. The Sn doping in Ge provides lower p.Finally, we discuss the TFT characteristics fabricated on the thinned SPC samples (55 nm for Ge and 50 nm for GeSn). Figure 2(a) shows that the typical p-channel transistor operation, i.e., drain current I D increases with increasing gate voltage V G. Figure 2(b) shows Sn doping reduces the off current I off significantly under keeping the on current I on. This reflects the electrical properties of the GeSn film obtained by the Hall effect measurement (Fig.1 (b)). Figure 3 summarizes the relationship between μ FE and I on/I off for different channel length (L = 5, 10, and 15 μm) in the same substrate. The experimental data show a clear increase in variability as the channel length decreases, which is in good agreement with the trends of poly-Si-TFTs. This is the first result showing such variability reflecting grain boundary at poly-Ge and GeSn. Furthermore, Sn doping improves I on/I off by roughly an order of magnitude although μ FE is almost identical. These results thus demonstrate the usefulness of Sn doping of polycrystalline Ge in TFT application. The current TFT performance will be further improved by the optimization of Sn concentration, film thickness, and channel dimensions (W/L). Reference [1] K. Toko, K. Moto et al., Sci. Rep. 7, 16981 (2017).[2] K. Moto et al., Appl. Phys. Lett. 114, 212107 (2019).[3] K. Moto et al., Sci. Rep. 8, 14832 (2018).[4] K. Moto et al., Appl. Phys. Lett. 114, 112110 (2019). Figure 1

Two‐Step Plasma Treatment Designed for High‐Performance Flexible Amorphous ZnAlSnO Thin‐Film Transistors Replacing Thermal Annealing

AbstractA two‐step plasma treatment is designed as a post‐process treatment for active layers of flexible thin‐film transistors (TFTs) instead of thermal post‐annealing. Amorphous zinc‐aluminum‐tin‐oxide (ZATO) is used for active layers of flexible TFTs, which highlights the influence of the two‐step plasma treatment on ZATO films and the corresponding TFT devices, because the device performance of ZATO TFTs exhibits significant improvement only after the active layers are annealed at high temperature. The effects of various plasma‐treatment of the ZATO active layer on the device performance are studied in detail. The two‐step plasma treatment can ameliorate the amorphous film and improve the corresponding device performance. The flexible TFT device with ZATO active layer processed by the two‐step plasma treatment exhibits an Ion/Ioff current ratio of 1.15 × 108, a positive threshold voltage of 3.77 V, a field‐effect mobility of 13.2 cm2 V−1 s−1, and a subthreshold swing of 0.5 V per decade. Meanwhile, a correlation is found that the effect of the two‐step plasma treatment as post‐process treatment of amorphous ZATO films is almost equivalent to 500 °C annealing, by comparing the electrical properties of TFTs with ZATO active layers annealed at different temperature. The two‐step plasma treatment may replace high‐temperature annealing in the thermosensitive process.

Proton Conducting Perhydropolysilazane-Derived Gate Dielectric for Solution-Processed Metal Oxide-Based Thin-Film Transistors.

Perhydropolysilazane (PHPS), an inorganic polymer composed of Si-N and Si-H, has attracted much attention as a precursor for gate dielectrics of thin-film transistors (TFTs) due to its facile processing even at a relatively low temperature. However, an in-depth understanding of the tunable dielectric behavior of PHPS-derived dielectrics and their effects on TFT device performance is still lacking. In this study, the PHPS-derived dielectric films formed at different annealing temperatures have been used as the gate dielectric layer for solution-processed indium zinc oxide (IZO) TFTs. Notably, the IZO TFTs fabricated on PHPS annealed at 350 °C exhibit mobility as high as 118 cm2 V-1 s-1, which is about 50 times the IZO TFTs made on typical SiO2 dielectrics. The outstanding electrical performance is possible because of the exceptional capacitance of PHPS-derived dielectric caused by the limited hydrolysis reaction of PHPS at a low processing temperature (<400 °C). According to our analysis, the exceptional dielectric behavior is originated from the electric double layer formed by mobile of protons in the low temperature-annealed PHPS dielectrics. Furthermore, proton conduction through the PHPS dielectric occurs through a three-dimensional pathway by a hopping mechanism, which allows uniform polarization of the dielectric even at room temperature, leading to amplified performance of the IZO TFTs.

The Effect of Crystalline Aluminum Oxide on Device Performance of Solution-Processed Indium-Gallium-Zinc-Oxide Thin-Film Transistors Operating at Low Voltage.

High dielectric constant (high-k) materials have been extensively investigated for low-voltage operating electronics. In recent years, solution-processed high-k dielectrics have been of technological interests in low fabrication cost, large area process and good film quality, compared to the vacuum-process technology. In this paper, we demonstrate solution-processed aluminum oxide (Al2O3) dielectrics for high performance solution-processed indium-gallium-zinc-oxide (IGZO) thin-film transistors (TFTs) operating at low voltage. The material and electrical properties of Al2O3 dielectrics fabricated at different post-annealing temperatures were analyzed by atomic force microscopy, scanning electron microscopy, X-ray diffraction and capacitance-voltage measurements. We also investigate the effect of crystalline Al2O3 dielectrics on the device performance of solution-processed IGZO TFTs. It is concluded that improved interfacial characteristics of crystalline Al2O3 dielectrics enhance the device performance of solution-processed IGZO TFTs operating at 3 V.

Solution-Processed Hybrid Ambipolar Thin-Film Transistors Fabricated at Low Temperature

We demonstrate solution-processed hybrid ambipolar thin-film transistors (TFTs) employing a stack structure composed of indium–gallium–zinc-oxide (IGZO) and single-wall carbon nanotube (SWCNT) as an active channel fabricated at low temperature. With an optimized deep-ultraviolet (DUV) photo annealing process for sol–gel based IGZO thin film on SWCNT random networks, the ambipolar transport of both electrons and holes with good electrical characteristics was realized. We also investigate the effect of DUV photo annealing on the material characteristics of solution-processed hybrid stack films and on the device performance of solution-processed hybrid ambipolar TFTs compared to those of samples thermally annealed at 500 °C, which is required for solution-processed high-quality IGZO thin films. The Raman spectra show that DUV photo annealing ensures hole transport in SWCNT random networks of a hybrid stack film, where the intensity of the 2D peak to the G peak was not changed compared to that of pristine SWCNT random networks. We believe that these analytical investigations reveal that DUV photo annealing is a promising method by which to realize hybrid ambipolar SWCNT/IGZO TFTs fabricated at low temperature.

Low-Voltage Operating Single-Wall Carbon Nanotube Thin-Film Transistors Using High Work Function Contacts on Flexible Substrates.

There have been constant attempts as regards high-performance thin-film transistors (TFTs) by improving the charge injection between the source/drain electrode (S/D) and the channel. In this paper, we investigate the effect of the electric contact on the device performance of single-wall carbon nanotube (SWCNT) TFTs employing the suitable work function material. In order to realize the electric contacts for the dominant hole injection between the S/D and the SWCNT active channel, a high work function material of molybdenum trioxide (MoOx) fabricated by an optimized process are utilized. The contact resistance is extracted by plotting the width-normalized resistance of SWCNTTFT with Pd and MoOx contacts as a function of channel length. We also demonstrate low-voltage operating SWCNT TFTs on flexible polyimide substrates with the reduced electric contacts. Without a buffer film which has been widely used to improve the device performance of TFT on a flexible substrate, high-performance low-voltage operating SWCNT-TFTs were achieved.

Improved Structural and Electrical Properties of ZnO-Based Thin Film Transistors by Using Pulsed KrF Excimer Laser Irradiation

We report on the characteristics of ZnO-based thin film transistors (TFT) fabricated by radio frequency magnetron sputtering. The surface of the ZnO channel layers were treated by pulsed KrF excimer laser irradiation (ELI) to improve the structural and electrical properties. The ZnO TFT device is of bottom gate type, which consists of SiO2 as a gate insulator and indium tin oxide as a gate deposited onto Corning glass substrates. The root-mean-square surface roughness and structural property of ZnO channel layer was significantly improved by the ELI treatment. The laser-treated ZnO TFT exhibited a saturation mobility of 19.27 cm2/V s, an on/off ratio greater than 105, the off current of less than 10−7 A, and a threshold voltage of 1.1 V. These results revealed the significant improvement of device characteristics and demonstrated that the pulsed KrF ELI treatment is an effective way to improve the ZnO TFT device performance.

Comparative Study on Hydrogen Behavior in InGaZnO Thin Film Transistors with a SiO2/SiNx/SiO2 Buffer on Polyimide and Glass Substrates

Previous studies have reported on the mechanical robustness and chemical stability of flexible amorphous indium gallium zinc oxide (a-IGZO) thin-film transistors (TFTs) on plastic substrates both in flat and curved states. In this study, we investigate how the polyimide (PI) substrate affects hydrogen concentration in the a-IGZO layer, which subsequently influences the device performance and stability under bias-temperature-stress. Hydrogen increases the carrier concentration in the active layer, but it also electrically deactivates intrinsic defects depending on its concentration. The influence of hydrogen varies between the TFTs fabricated on a glass substrate to those on a PI substrate. Hydrogen concentration is 5% lower in devices on a PI substrate after annealing, which increases the hysteresis characteristics from 0.22 to 0.55 V and also the threshold voltage shift under positive bias temperature stress by 2 × compared to the devices on a glass substrate. Hence, the analysis and control of hydrogen flux is crucial to maintaining good device performance and stability of a-IGZO TFTs.

New conjugated regular terpolymers based on diketopyrrolopyrrole-benzodithiophene and their application to thin film transistors and polymer solar cells

Conjugated binary copolymers containing an electron donor (D) and acceptor (A) in the repeating unit have been extensively studied due to their excellent charge transport properties. Moreover, conjugated terpolymers containing a third monomer in addition to the two D and A monomers have been recognized to exhibit finely tuned properties relative to the binary D-A copolymer. Diketopyrrolopyrrole (DPP)–based conjugated regular terpolymers (CRTs) containing two different electron donor monomers were synthesized herein to exploit the advantages of the terpolymer. Two terpolymers were synthesized by using bithiophene and pyrene as third monomers. Compared to the reference copolymer, poly[3-(5-(benzo[1,2-b:4,5-b']dithiophen-2-yl)thiophen-2-yl)-2,5-bis(2-decyltetradecyl)-6-(thiophen-2-yl)-2,5-dihydropyrrolo[3,4-c]pyrrole-1,4-dione] (PDPPBDT), the new terpolymers exhibited distinct physical properties, absorption properties, and electronic energy levels. The terpolymers were employed in thin film transistors (TFTs) and polymer solar cells (PSCs) and the device performance was studied. The highest mobility achieved for the TFT devices was close to 1.0 cm2 V−1 s−1 and was obtained with the PDPPBTBDT terpolymer film as the active layer, whereas the mobilities of the TFTs employing the PDPPPYBDT and PDPPBDT polymers were relatively low. In contrast with the TFT device results, the PSC fabricated with PDPPPYBDT:PC71BM showed the highest power conversion efficiency (PCE) of 4.46% due to the relatively high Voc and Jsc. The results of this study confirmed that the use of a regular terpolymer structure permits fine adjustment of the light absorption range, the molecular energy levels, and the film morphology of the polymer, in turn influencing the device performance of TFTs or PSCs.

A comparative study of n-channel low temperature poly-Si thin-film transistors with a body terminal or a lightly-doped-drain structure

Hot-carrier (HC) induced degradation is a critical reliability issue of n-channel low temperature poly-Si thin-film transistors (TFTs) in TFT-based circuits. In this work, a kind of four-terminal TFT, which has an additional p+-doped lateral body terminal connecting to the floating channel, is systematically compared to conventional n-channel TFT and lightly-doped-drain (LDD) TFT. We demonstrate that the four-terminal TFT can provide similar advantages to that of the LDD TFT such as kink current suppression and DC HC degradation immunity, much superior immunity to the dynamic HC degradation, but without any tradeoffs in device performance and process complexity of the LDD TFT. It has high performance, as well as excellent reliability under both DC and AC conditions.

Efficient Defect Engineering for Solution Combustion Processed In-Zn-O thin films for high performance transistors

The oxygen related defects in the solution combustion-processed InZnO vitally affect the field-effect mobility and on-off characteristics in thin film transistors (TFTs). We use photoelectron spectroscopy to reveal that these defects can be well controlled by adjusting the atmosphere and flow rate during the combustion reaction, but are hardly affected by further post-annealing after the reaction. In device performance, the threshold voltage of the InZnO-TFTs was regulated in a wide range from 3.5 V to 11.0 V. To compromise the high field-effect mobility and good subthreshold properties, we fabricate the TFTs with double active layers of InZnO to achieve vertical gradience in defect distribution. The resulting TFT exhibits much higher field-effect mobility as 17.5 cm2 · V−1 · s−1, a low reversed sub-threshold slope as 0.35 V/decade, and a high on-off ratio as 107. The presented understandings and methods on defect engineering are efficient in improving the device performance of TFTs made from the combustion reaction process.

Application of Flash Lamp Annealing on Nitrogen-Doped Amorphous Indium-Gallium-Zinc-Oxide Thin Film Transistors

Amorphous nitrogenated indium-gallium-zinc oxide (a-IGZO:N) thin films were deposited on highly doped silicon (n+Si) wafer substrates and heat-treated by millisecond flash lamp annealing (FLA) at different preheating temperatures to enhance the electrical characteristics of oxynitride thin film transistors (TFTs). A one-dimensional conduction/radiation heat transfer simulation was conducted to predict the temperature fields in the Si substrate, which indicated that the film temperatures during FLA instantaneously rose above 700°C. The electrical characteristics of the a-IGZO:N TFTs were compared with those produced by conventional furnace annealing of one hour. As a result of the FLA process, a remarkable improvement in the TFT device performance was observed in terms of the electrical output characteristics and transfer curves of the a-IGZO:N TFTs. Morphological analyses were conducted using X-ray diffraction, atomic force microscopy, and field emission scanning electron microscopy, indicating the possibility of partial crystallization of the a-IGZO:N channel layers under high-temperature annealing conditions, but the best TFT performance was found for the amorphous phase of IGZO:N.