Characteristics Of Thin-film Transistors Research Articles

Electrical Characteristics of Solution-Based Thin-Film Transistors with a Zinc-Tin Oxide/Carbon Nanotube Stacked Nanocomposite Active Layer.

A stacked nanocomposite zinc-tin oxide/single-walled carbon nanotubes (ZTO/SWNTs) active layer was fabricated for thin-film transistors (TFTs) as an alternative to the conventional single-layer structure of mixed ZTO and SWNTs. The stacked nanocomposite of the solution-processed TFTs was prepared using UV/O3 treatment and multiple annealing steps for each layer. The electrical properties of the stacked device were superior to those of the single-layer TFT. The ZTO/SWNT TFT, fabricated using a stacked structure with ZTO on the top and SWNT at the bottom layer, showed a significant improvement in the field-effect mobility of 15.37 cm2/V·s (factor of three increase) and an Ion/Ioff current ratio of 8.83 × 108 with improved hysteresis. This outcome was attributed to the surface treatment and multiple annealing of the selected active layer, resulting in improved contact and a dense structure. This was also attributed to the controlled dispersion of SWNT, as electron migration paths without dispersants. This study suggests the potential expansion of applications, such as flexible electronics and low-cost fabrication of TFTs.

Machine Learning Strategy for Optimizing Multiple Electrical Characteristics in Dual-Layer Oxide Thin Film Transistors.

A machine learning (ML) strategy is suggested to optimize dual-layer oxide thin film transistor (TFTs) performance. In this study, Bayesian optimization (BO), an algorithm recognized for its efficiency in optimizing material design, is applied to guide the design of a channel layer composed of IZO and IGZO. The sputtering fabrication process, which has attracted attention as an oxide semiconductor channel layer deposition method, is fine-tuned using ML to enhance multiple electrical characteristics of transistors: field-effect mobility, threshold voltage, and subthreshold swing. Using BO, the sputtering conditions─plasma power, pressure, and gas ratio, which intricately influence device performance─were modified using 19 data sets of 84 scenarios. It reveals that the modulated process conditions improve field-effect mobility up to 46.7 cm2V-1s-1, achieving more than double the performance of conventional IGZO TFTs. Furthermore, it was observed that threshold voltage is optimized to zero voltage, and the subthreshold swing is considerably improved, contributing to reduced power consumption. This study demonstrates that leveraging ML to optimize TFTs design not only accelerates the design process but also improves device performance dramatically. Overall, this ML strategy manages complex correlations among process parameters, properties, and performance and sets a precedent for the expeditious optimization of semiconductor devices.

Flexible bezel‐less thin‐film transistor backplane with through‐plastic‐vias for seamless tiling

AbstractTiling with a variety of panel units is a promising approach to customizing displays in terms of size, shape, and aspect ratio. However, tiled displays with conventional panel units have a major drawback in that they suffer from noticeable seams due to the bezels of the panel units. Here, we demonstrate a flexible bezel‐less thin‐film transistor (TFT) backplane for seamless tiling. By using through‐plastic‐vias (TPVs) that penetrate an ultrathin polyimide (PI) film substrate, a bezel‐less backplane with an ultra‐narrow bezel width of 8 μm was realized, in which oxide TFTs in pixel circuits on the backplane are driven from the back side of the PI film substrate using three‐dimensional signal wires, which go through the TPVs. The resistance of a TPV was evaluated with a TPV chain with 1000 TPVs connected in series and was found to be as small as 1.3 Ω. Furthermore, the transfer characteristics of an oxide TFT in a test element group for a pixel circuit were evaluated from the back side of the PI film substrate. The TFT exhibited clear switching behavior with an on/off current ratio of more than 108 and a high mobility of 25 cm2/Vs, which are sufficient to drive light‐emitting devices.

Selectively Self-Aligned Sol-Gel Copper Oxide for Large-Area Multi-Valued Logic Devices.

Rapid expansion of digital information density has led to a growing demand for multi-valued logic (MVL) systems, which aim to minimize energy and time consumption for computations. Heterojunction transistors represent a class of device architectures for MVL circuits; however, partially layered structures can be realized only for vacuum-deposited organic and transferred 2D materials due to the constraints of patterning processes. In this study, a novel CuxO/IGZO heterojunction-based ternary inverter is presented via a sol-gel technique and direct patterning process using a self-assembled monolayer (SAM). This approach allows for a promising alternative to conventional photolithography, with the electrical characteristics of SAM-processed oxide thin-film transistors closely matching those of pristine devices. Structural investigations validate the partially overlapped heterojunction and its smoothness. Depth profiling with x-ray photoelectronspectroscopy highlights an oxidation gradient in CuxO, suggesting enhanced hole introduction at the IGZO interface. This mechanism potentially supports efficient hole transport and negative differential transconductance, foundational for MVL systems. Such advancements signify the potential for solution-processable digital electronics that offer streamlined fabrication at an affordable budget.

The Effect of Doping Conditions on Amorphous IGZO Electrical Conductivity

In recent years, there has been a noticeable increase in interest in thin-film transistors (TFTs) employing oxide semiconductors in the display industry. Among various oxide semiconductors, amorphous indium gallium zinc oxide (a-IGZO) has emerged as a particularly promising material and being used for the backplane of the OLED (organic light emitting diode) TV. It offers several advantages over conventional materials such as amorphous silicon (a-Si) and organic semiconductors, including higher electron mobility, lower leakage current, and wide area process applicability.For the top-gate self-aligned structure offers distinct advantages over the bottom-gate structure, reducing parasitic capacitance between source/drain and gate electrodes. For low contact resistance between the source/drain electrodes and a-IGZO, the doping process on the IGZO layer is necessary to enhance conductivity at the source and drain region. Various doping techniques are employed for a-IGZO, including ultraviolet (UV) irradiation [1], ion implantation, and plasma treatment [2]. Ion implantation is a widely used method in semiconductor manufacturing, where ions are injected into the semiconductor using high-energy ion beams. UV irradiation, on the other hand, utilizes ultraviolet light to shift the Fermi level below the conduction band, thereby making the semiconductor conductive. Plasma doping, the focus of this study, typically involves using equipment such as PECVD (Plasma Enhanced Chemical Vapor Deposition) or RIE (Reactive Ion Etching) to dope a-IGZO within a low-pressure chamber using plasma generated. Reactive gases are introduced, and plasma ions with high energy disrupt the metal-oxygen bonds within a-IGZO, enhancing conductivity and reducing sheet resistance.In this study, plasma doping was employed and the changes in sheet resistance was investigated under different plasma conditions, particularly focusing on various reaction gases. Doping experiments were conducted for various gases, while the effects of plasma treatment were evaluated through the sheet resistance measurements and comprehensive composition analysis. The results of this study provide insights into the relationship between plasma doping through controlled reaction gases and changes in sheet resistance in a-IGZO.Our experimental results reveal that plasma treatment leads to a decrease in the electrical conductivity of the IGZO layer. Moreover, we explore how varying plasma treatment time and power levels influence this conductivity reduction. Furthermore, we examine the effect of post-annealing on the electrical conductivity of plasma treated IGZO layers. Our findings demonstrate that post-annealing conditions play a crucial role in determining the final electrical conductivity of IGZO layers after plasma treatment.[1] H. Seo, et al. "Permanent optical doping of amorphous metal oxide semiconductors by deep ultraviolet irradiation at room temperature," Appl. Phys. Lett. 96, 222101 (2010).[2] W. -S. Liu, C. -H. Hsu, Y. Jiang, Y. -C. Lai, and H. _C. Kuo, “Improving device characteristics of dual-gate IGZO thin-film transistors with Ar-O2 mixed plasma treatment and rapid thermal annealing,” Membranes 12, 49 (2022).

Revisiting Band Tails and Localized States in Amorphous Semiconductors

Amorphous semiconductors, such as hydrogenated amorphous silicon (a-Si:H) and amorphous indium gallium zinc oxide (a-IGZO) have been central to the development of thin film transistors (TFTs) for large-area electronic applications such as displays. This is a result of the exceptional material uniformity that can be achieved when depositing over very large areas (~10 m2). This means that all TFTs are essentially identical over an entire large display panel. However, there is a technological price to pay – the carrier mobility is generally less in amorphous semiconductors compared to their crystalline equivalent.The origin of this reduced carrier mobility is a result of a key difference in the density of states between crystalline semiconductors and their amorphous counterparts. The long-range order of a crystalline lattice means that all carrier states in the conduction and valence bands exist over long distances. These ‘extended states’ are associated with generally high mobility carriers. However, there is no long-range order in amorphous semiconductors, but only short-range order over one to two bond lengths associated with local atomic coordination requirements (and to some degree a medium-range order over a few bond lengths). The result is that the bottom of the conduction band and top of the valence band gain ‘tail’ states which are localized in nature.Not only do these localized states frequently dominate (or at least significantly affect) conduction in amorphous semiconductors and hence the switching characteristics of TFTs, but they also have a role to play in other important processes such as hysteresis and bias stress instability. But what are these localized band tail states, how should we think about them in the context of conduction and how do they relate to extended states?These questions are revisited from the starting point that there is a perturbation in the delocalized charge concentration with position in an amorphous semiconductor compared to its crystalline counterpart, and this can be quantified as a spatially varying excess charge concentration (where a deficit is just a negative excess). The rate of spatial variation is long relative to the rate of change in the electron wavefunction, and reflects the short- and medium-range order distances. Charge conservation means that that this excess charge concentration will have a mean of zero and a Gaussian probability distribution is assumed. A model using this as a starting point has been created which reproduces band tails and which provides new insights into their physics which are discussed.

Unveiling the Mechanics Behind Polyimide's Friction-Greening Phenomenon.

Polyimide (PI) has been widely used as a flexible substrate in the OLED display industry to achieve folding and other functions. However, it has unintended side effects, such as friction-greening, a green screen phenomenon caused by friction after prolonged usage. This is related to drifting TFT characteristics caused by charge accumulating in the PI in combination with the high efficiency of green pixels. In this study, the mechanism of the influence of PI structure on friction-greening was investigated. Increasing the process temperature from 350 °C to 470 °C, the chain segment structure within the PI became more regularized. Thus, the material had higher conductivity and shallower trap energy levels, which was confirmed by X-ray small angle scattering, dielectric, photoluminescence, and other methods. Under prolonged discharge conditions, less charge accumulated within PI, thus effectively mitigating the threshold voltage drift of the thin-film transistor (TFT). These results will contribute to the further optimization of the process and the development of PI materials.

Low-frequency noise analysis on asymmetric damage and self-recovery behaviors of ZnSnO thin-film transistors under hot carrier stress

The need for understanding the low-frequency noise (LFN) of metal oxide semiconductor thin-film transistors (TFTs) is increasing owing to the substantial effects of LFN in various circuit applications. A focal point of inquiry pertains to the examination of LFN amidst bias stress conditions, known to compromise TFT reliability. In this study, we investigate the effects of hot carrier stress (HCS) on zinc tin oxide (ZTO) TFTs by low-frequency noise (LFN) analysis. Asymmetric damage caused by HCS is analyzed by measuring the power spectral density at the source and drain sides. The excess noise generated by the HCS is analyzed with consideration of trap density of states (DOS). It is revealed that the needle defects are generated during the HCS, significantly affecting the LFN characteristics of the ZTO TFTs. Additionally, we observe a self-recovery behavior in the devices and demonstrate the relevant changes in the LFN characteristics following this phenomenon. This study provides valuable insights into the LFN characteristics of ZTO TFTs under HCS conditions and sheds light on the underlying mechanisms.

Ultrathin In2O3 thin-film transistors deposited from trimethylindium and ozone

Indium oxide (In2O3) is a promising channel material for thin-film transistors (TFTs). In this work, we develop an atomic layer deposition (ALD) process of using trimethylindium and ozone (O3) to deposit In2O3 films and fabricate ultrathin In2O3 TFTs. The In2O3 TFTs with 4 nm channel thickness show generally good switching characteristics with a high I on/I off of 108, a high mobility (μ FE) of 16.2 cm2V−1s−1 and a positive threshold voltage (V th) of 0.48 V. Although the 4 nm In2O3 TFTs exhibit short channel effect, it can be improved by adding an ALD Ga2O3 capping layer to afford the bilayer In2O3/Ga2O3 channel structure. The afforded In2O3/Ga2O3 TFTs exhibit improved immunity to the short channel effect, with good TFT characteristics of I on/I off of 107, μ FE of 9.3 cm2V−1s−1 , and positive V th of 2.23 V. Overall, the thermal budget of the entire process is only 400 °C, which is suitable for the display and CMOS back-end-of-line-compatible applications.

(Invited) Polarization Stability Improvement for Hf0.5Zr0.5O2-Based Ferroelectric Capacitor

The instability in polarization during the endurance test of Hf0.5Zr0.5O2 (HZO) ferroelectrics thin films including the wake-up and the fatigue are still major challenges for the development of HZO-based ferroelectric memories. In this work, we will review the proposed mechanisms of the instabilities in polarization including wake-up and fatigue of the HZO-based metal-ferroelectric-metal (MFM) capacitors. Then, the material processing techniques to address the issues of instabilities are provided. The in-situ deposition of electrode and ferroelectric layers by atomic layer deposition (ALD) attracted considerable attention as a promising solution. Owing to the improved interface quality, both the endurance characteristics and remanent polarization were enhanced. We have also developed a HfO2/ZrO2 superlattice structure to further enhance the ferroelectric endurance of the MFM capacitors. The superlattice MFM capacitors show wake-up free characteristics with excellent endurance. The device performances and endurance characteristics of ferroelectric thin film transistor will also be presented.

Effect of interface defects on electrical characteristics of a-ITGZO TFTs under bottom, top, and dual gatings

Here, we investigate the effects of interface defects on the electrical characteristics of amorphous indium-tin-gallium-zinc oxide (a-ITGZO) thin-film transistors (TFTs) utilizing bottom, top, and dual gatings. The field-effect mobility (27.3 cm2/V∙s) and subthreshold swing (222 mV/decade) under a dual gating is substantially better than those under top (12.6 cm2/V∙s, 301 mV/decade) and bottom (11.1 cm2/V∙s, 487 mV/decade) gatings. For an a-ITGZO TFT, oxygen deficiencies are more prevalent in the bottom-gate dielectric interface than in the top-gate dielectric interface, and they are less prevalent inside the channel layer than at the interfaces, indicating that the presence of oxygen deficiencies significantly affects the field-effect mobility and subthreshold swing. Moreover, the variation in the electrical characteristics due to the positive bias stress is discussed here.

Characteristics of Fully-Depleted Poly-Si Thin Film Transistors Operated in Above-Threshold Region with Low Drain Bias

Transfer and output characteristics of fully-depleted polycrystalline silicon thin film transistors, including both tail and deep acceptor-like trap states in bulk, in the above-threshold region with low drain bias are presented under low or high state density in the situation without or with interface charge, respectively. The characteristics are calculated by a simple surface-potential-based drain current model in the strong inversion region with valid bias condition explained, and 2D-device simulation. The above-threshold region is found to be divided into Regions I and II, with Vsi , indicating the channel beginning to be completely strongly-inverted and large currents, and explication of deviations between the model and simulation in Region I. The large-traps effect on the range of Region I and Vth in the high state density situation is discovered.

Aqueous solution-processed In2O3 TFTs using focused plasma in gas mixtures

Solution-processed indium oxide (In2O3) thin films have been studied widely as active layers for transparent semiconducting devices because of their high charge carrier concentration, low absorbance, simple fabrication methods, and low cost. Several studies on improving the electrical characteristics of thin-film transistors (TFTs) by optimizing and fine-tuning the fabrication process and using various post-deposition treatments have been conducted to take full advantage of these semiconductor films in high-performance electronics. This study examined the effects of a focused plasma (FP) treatment on In2O3 thin films prepared using a simple solution process at 250 °C. The effects of the FP generated from N2 gas and two gas mixtures (N2-H2 and N2-H2-O2) on the electrical performance of the TFTs were analyzed. The FP treatment enhanced the electrical properties of the device, and the specific performance and stability parameters were improved by the treatment conditions. X-ray photoelectron spectroscopy showed that the FP treatment could effectively control the oxygen vacancies and carrier concentration in the solution-processed In2O3 thin films. Therefore, an FP beam is a viable method for optimizing In2O3 TFTs prepared at low temperatures for application in high-performance transparent electronic devices.

A Simple Scan Driver Circuit Suitable for Depletion-Mode Metal-Oxide Thin-Film Transistors in Active-Matrix Displays

Metal-oxide (MOx) thin-film transistors (TFTs) require complex circuit structures to cope with their depletion mode characteristics, making them applicable only to large-area active matrix (AM) displays despite their low manufacturing cost and decent performance. In this paper, we report a simple MOx 10T-2C scan driver circuit that overcomes the depletion mode characteristics using a series-connected two transistor (STT) configuration and clock signals with two kinds of low-voltage levels. The proposed circuit has a wide operating range of TFT characteristics, i.e., −2.8 V ≤ VTH ≤ +3.0 V. Through the measurement results of the manufactured sample, it was confirmed that the performance and area of our circuit are suitable for high-resolution mobile displays.

P‐2: Investigation of high mobility crystalline IGO TFT with top‐gate structure for LCD display application

The present paper reports the study of electrical characteristics and bias temperature stress (BT) stability of crystalline Indium‐Gallium oxide (IGO) dual‐gate thin film transistor (TFT) with top‐gate structure. TFT with normalized Ion over 100εA and PBTS/NBTIS of 0.35/‐2.85V was successfully fabricated. By adjusting oxygen partial pressure (O2%) and substrate temperature, we can control the wet etching rate (WER) of as‐deposited IGO film. After post annealing, crystalline IGO containing In2O3 phase with preferred orientation of (222) has been formed. The TFT characteristics uniformity and BT stability were found to depend on parameters of gate insulator (GI) deposition and pre‐treatment before GI. Based on experimental results, we propose high GI deposition temperature associated with low N2O plasma treatment power as the optimal condition for industrial production of crystalline IGO TFT.

Effects of iodine doping on structural and electrical characteristics of solution-processed indium oxide thin-film transistors and its potential application for iodine sensing

Effects of iodine doping on structural and electrical characteristics of solution-processed indium oxide thin-film transistors and its potential application for iodine sensing

Analysis on charge-retention characteristics of sub-threshold synaptic IGZO thin-film transistors with defective gate oxides

We provide a quantitative analysis on the charge-retention characteristics of sub-threshold operating In–Ga–Zn–O (IGZO) thin-film transistors (TFTs) with a defective gate-oxide for low-power synaptic applications. Here, a defective SiO2 is incorporated as the synaptic gate-oxide in the fabricated IGZO TFTs, where a defect is physically playing the role as an electron trap. With this synaptic TFT, positive programming pulses for the electron trapping are applied to the gate electrode, followed by monitoring the retention characteristics as a function of time. And this set of the programming and retention-monitoring experiments is repeated in several times for accumulating effects of pre-synaptic stimulations. Due to these accumulated stimulations, electrons are expected to be getting occupied within a deeper trap-state with a higher activation energy, which can lead to a longer retention. To verify these phenomena, a stretched exponential function and respective inverse Laplace transform are employed to precisely estimate a retention time and trap activation-energy for transient experimental results.

Low-temperature preparation and characteristics of top-gate thin-film transistors with La-ZTO active layers and polymethylmethacrylate dielectric layers

A top-gate coplanar-structure thin-film transistor (TFT) combining the advantages of both a co-sputtered amorphous La-doped ZnSnO (a-La-ZTO) active layer and solution-based polymethylmethacrylate (PMMA) gate dielectric layer has been prepared under low temperature (100 °C) with low cost for the first time. The results indicate that the PMMA thin film demonstrates anti-reflection properties when it combines with a-La-ZTO layer to form a double-layer film, displaying high transparency to visible light of ∼90.3%. Moreover, it was found that the La target power during the deposition of a-La-ZTO film plays an important role in suppressing the formation of oxygen vacancies and adjusting the carrier concentration of a-La-ZTO active layer, thus impacting a-La-ZTO TFT performance. Overall, the optimum a-La-ZTO TFT with a La target power of 13.9 W, working in an n-channel enhancement mode, possesses a large saturated mobility (>10 cm2 (Vs)−1) and an on/off drain current ratio over 105.

Floating body effect in indium–gallium–zinc–oxide (IGZO) thin-film transistor (TFT)

In this paper, the floating body effect (FBE) in indium-gallium-zinc-oxide (IGZO) thin-film transistor (TFT) and the mechanism of device failure caused by that are reported for the first time. If the toggle AC pulses are applied to the gate and drain simultaneously for the switching operation, the drain current of IGZO TFT increases dramatically and cannot show the on/off switching characteristics. This phenomenon was not reported before, and our study reveals that the main cause is the formation of a conductive path between the source and drain: short failure. It is attributed in part to the donor creation at the drain region during the high voltage (Vhigh) condition and in part to the donor creation at the source region during the falling edge and low voltage (Vlow) conditions. Donor creation is attributed to the peroxide formation in the IGZO layer induced by the electrons under the high lateral field. Because the donor creation features positive charges, it lowers the threshold voltage of IGZO TFT. In detail, during the Vhigh condition, the donor creation is generated by accumulated electrons with a high lateral field at the drain region. On the other hand, the floating electrons remaining at the short falling edge (i.e., FBE of the IGZO TFT) are affected by the high lateral field at the source region during the Vlow condition. As a result, the donor creation is generated at the source region. Therefore, the short failure occurs because the donor creations are generated and expanded to channel from the drain and source region as the AC stress accumulates. In summary, the FBE in IGZO TFT is reported, and its effect on the electrical characteristics of IGZO TFT (i.e., the short failure) is rigorously analyzed for the first time.

Enhancement of electrical characteristics of SnGaO thin-film transistors via argon and oxygen plasma treatment

The impact of Ar or O2 plasma treatment on the electrical characteristics of SnGaO thin film transistors (TFTs) fabricated via solution method was examined. The findings of the study revealed that Ar plasma treatment for an optimal duration enhances the electrical properties of SnGaO TFTs, including the improvement of mobility, subthreshold swing (S·S.), and on-off ratio. This result is considered to be due to the increased concentration of oxygen vacancy as donor in the channel layer. Oxygen plasma treatment has an opposite effect on the change in oxygen vacancy concentration, thereby reducing the off-state current and facilitating the adjustment of threshold voltage. However, excessive Ar or O2 plasma treatment duration led to an increase in deep defect states and a significant “hump" phenomenon in the output characteristic curve.