Thin-film Transistors Channel Research Articles

All-oxide thin-film transistors with channels of mixed InOx-ZnOy formed by plasma-enhanced atomic layer deposition process

To make high mobility oxide thin-film transistors (TFTs) for transparent large displays, the authors fabricated all-oxide TFTs having amorphous mixed-oxide channels of indium oxide (InOx) and zinc oxide (ZnOy). Liquid precursors of 3-(dimethyl amino)propyl-dimethyl indium (C7H18InN) and diethyl zinc [(C2H5)2Zn] and oxygen plasma were used to form mixed-oxide channels by plasma-enhanced atomic layer deposition (ALD). The authors varied the cycle ratio of InOx and ZnOy to deduce the optimal ratio of InOx:ZnOy for high performance TFTs. X-ray photoelectron spectroscopy analyses were performed to reveal the decrease in the oxygen-deficient state as the fraction of InOx increases. At a deposition cycle ratio of InOx:ZnOy = 2:1, the TFT demonstrated the best performance of field effect mobility of 30.3 cm2/V s, subthreshold of 0.14 V/decade, and Ion/Ioff ratio of 3.1 × 109. By adjusting the relative cycles of different oxides in an ALD process, one may obtain the desired mixed-oxide channel TFT properties, which is not readily possible in the sputtering process. By varying the compositions of the oxide channel layer, the latitude of device fabrication could be widening, thereby enabling performance customization.

Carrier and heat transport properties of poly-crystalline GeSn films for thin-film transistor applications

Thin-film transistors (TFTs) on insulator substrates are widely used in applications from liquid crystal displays to sensor devices. However, insulator substrates with low heat conductivity lead to unfavorable self-heating effects in the channel regions. Herein, the carrier and heat transport properties of polycrystalline GeSn films on SiO2/Si substrates were improved by suppressing Sn segregation in the films to fabricate GeSn channel TFTs. Alloying with 5.5% Sn enabled the formation of larger grains than those in poly-Ge films after low-temperature annealing (below 520 °C) without Sn segregation. In addition, the films had a hole mobility of 40 cm2 V−1 s−1 at a hole density of 1.1 × 1018 cm−3 and a thermal conductivity of 12.1 Wm−1 K−1 at room temperature. The temperature dependences of the carrier and heat transport properties of the poly-GeSn films were investigated to accurately simulate a device with a poly-GeSn channel TFT. This was achieved by using the carrier transport measurements and numerical simulations of the heat transport in the Debye model. The simulated device allowed an accurate assessment of the self-heating effects of the TFT and thus provides a design guide for TFTs.

Degradation Induced by Forward Synchronized Stress in Poly-Si TFTs and Its Reduction by a Bridged-Grain Structure

In this letter, forward synchronized stress (FSS) is proposed to further simulate the working conditions of switching thin-film transistors (TFTs) in active-matrix displays. The FSS induces tremendous device degradation in polycrystalline (poly-Si) TFTs, which is dominated by a dynamic hot carrier (HC) effect. For the first time, it is found that the dynamic HC effect is dependent on both rising time and falling time. Incorporated with TCAD simulations, the degradation mechanism is tentatively discussed. To alleviate such FSS-induced tremendous degradation, a bridged-grain structure, which can effectively suppress the peak value of lateral electric field by multiple reversed junctions, is applied in the active channel of poly-Si TFTs.

High-Performance Thin-Film Transistors of Quaternary Indium-Zinc-Tin Oxide Films Grown by Atomic Layer Deposition.

A new deposition technique is required to grow the active oxide semiconductor layer for emerging oxide electronics beyond the conventional sputtering technique. Atomic layer deposition (ALD) has the benefits of versatile composition control, low defect density in films, and conformal growth over a complex structure, which can hardly be obtained with sputtering. This study demonstrates the feasibility of growing amorphous In-Zn-Sn-O (a-IZTO) through ALD for oxide thin-film transistor (TFT) applications. In the ALD of the a-IZTO film, the growth behavior indicates that there exists a growth correlation between the precursor molecules and the film surface where the ALD reaction occurs. This provides a detailed understanding of the ALD process that is required for precise composition control. The a-IZTO film with In/Zn/Sn = 10:70:20 was chosen for high-performance TFTs, among other compositions, regarding the field-effect mobility (μFE), turn-on voltage ( Von), and subthreshold swing (SS) voltage. The optimized TFT device with the a-IZTO film thickness of 8 nm revealed a high performance with a μFE of 22 cm2 V-1 s-1, Von of 0.8 V, and SS of 0.15 V dec-1 after annealing at 400 °C for 30 min. Furthermore, an emerging device such as a vertical channel TFT was demonstrated. Thus, the a-IZTO ALD process could offer promising opportunities for a variety of emerging oxide electronics beyond planar TFTs.

Numerical Simulation on Thickness Dependency and Bias Stress Test of Ultrathin IGZO Thin‐Film Transistors Via a Solution Process

The authors report the effect of ultra‐thin channel layer thickness on the performance of an amorphous InGaZnO (a‐IGZO) thin‐film transistor (TFT). Numerical simulation is used to investigate the thickness effect on the a‐IGZO TFT output parameters. The simulation results are compared to measurements of the stability of nitrate ligand‐based hexaaqua complexes solution‐processed ultrathin a‐IGZO transistors a‐IGZO. This TFT is also tested under negative illumination bias stress (NIBS) and positive bias stress (PBS). The thinner channel layer is found to have a better performance than the thicker channel layer. The 4 nm‐thick, ultra‐thin a‐IGZO TFT exhibits high saturation mobility (7.56 cm2 V−1 s−1), low threshold voltage (2.73 V), a small value of sub threshold swing (0.22 V dec−1), and a high on/off ratio (). It is also noticed that the threshold voltage (Vth) shifts negatively as the thickness increases. The 4 nm long channel TFT shows more stability under NIBS and PBS while 16 nm have a strong degradation under NIBS and PBS.

High-Performance ALD Al-Doped ZnO Thin-Film Transistors Grown on Flexible Substrates

We report a CMOS compatible high-performance ALD Al-doped ZnO thin-film transistor (TFT) fabricated on flexible substrate with a sub-150 °C processing temperature. The TFTs channel are optimized through Al doping (2–3 at.%) using all low-temperature steps to enable flexible substrate processing while minimizing the piezoelectric effect in the channel. The optimized device has an electron mobility as high as ~30 cm2/Vs in comparison to earlier reported values of 0.1–0.7 cm2/Vs for ZnO TFTs while maintaining desired threshold voltages of 1–2 V and $I_{ \mathrm{\scriptscriptstyle ON}}/I_{ \mathrm{\scriptscriptstyle OFF}}$ ratios of 107–109.

Silver-doped tin oxide for electrical property enhancement in p-type channel thin film transistor

Though tin oxide (SnO) is one of the strong candidates for p-type oxide semiconductor thin film transistors (TFTs), poor properties and a narrow window of deposition condition are obstacles for implementation. An Ag-doped Sn thin film was studied for the improvement of electrical performance of TFTs. SnO and Ag-doped SnO thin films were deposited by direct current magnetron sputtering as the channel for thin film transistors. The concentration of Ag doping was controlled by the amount of Ag pellets in the sputtering target preparation. A change in oxide states was observed in an Ag-doped SnO film, which can lead to the reduction of the Sn4+ oxide phase. Ag-doped SnO showed improvement of carrier mobility and concentration and resulted in improved electrical characteristics.

Investigation of the Electrical Characteristics of Bilayer ZnO/In₂O₃ Thin-Film Transistors Fabricated by Solution Processing.

Metal-oxide thin-film transistors (TFTs) have been developed as promising candidates for use in various electronic and optoelectronic applications. In this study, we fabricated bilayer zinc oxide (ZnO)/indium oxide (In2O3) TFTs by using the sol-gel solution process, and investigated the structural and chemical properties of the bilayer ZnO/In2O3 semiconductor and the electrical properties of these transistors. The thermogravimetric analysis results showed that ZnO and In2O3 films can be produced by the thermal annealing process at 350 °C. The grazing incidence X-ray diffraction patterns and X-ray photoemission spectroscopy results revealed that the intensity and position of characteristic peaks related to In2O3 in the bilayer structure were not affected by the underlying ZnO film. On the other hand, the electrical properties, such as drain current, threshold voltage, and field-effect mobility of the bilayer ZnO/In2O3 TFTs obviously improved, compared with those of the single-layer In2O3 TFTs. Considering the energy bands of ZnO and In2O3, the enhancement in the TFT performance is explained through the electron transport between ZnO and In2O3 and the formation of an internal electric field in the bilayer structure. In the negative gate-bias stress experiments, it was found that the internal electric field contributes to the electrical stability of the bilayer ZnO/In2O3 TFT by reducing the negative gate-bias-induced field and suppressing the trapping of holes in the TFT channel. Consequently, we suggest that the bilayer structure of solution-processed metal-oxide semiconductors is a viable means of enhancing the TFT performance.

Indium Tungsten Oxide Thin Films for Flexible High-Performance Transistors and Neuromorphic Electronics

Thin-film transistors (TFTs) with high electrical performances (mobility > 10 cm2/V s, Vth < 1 V, SS < 1 V/decade, on/off ratio ≈ 106) obtained from the silicon- and oxide-based single-crystalline semiconductor materials require high processing temperature and hence are not suitable for flexible electronics. Amorphous oxide-based transparent electronic devices are attractive to meet emerging technological demands where crystalline oxide-/silicon-based architectures cannot provide a solution. Here, we tackle this problem by using a novel amorphous oxide semiconducting material-namely, indium tungsten oxide (IWO)-as the active channel in flexible TFTs (FTFTs). Post-annealing temperature as low as 270 °C for amorphous IWO thin films deposited by radio frequency sputtering at room temperature could result in smooth morphology ( Rrms ≈ 0.42 nm), good adhesion, and high carrier density ( n ≈ 7.19 × 1018 cm-3). Excellent TFT characteristics of flexible devices could be achieved with linear field effect mobility μFE ≈ 25.86 cm2/V s, subthreshold swing SS ≈ 0.30 V/decade, threshold voltage Vth ≈ -1.5 V, and on/off ratio Ion/ Ioff ≈ 5.6 × 105 at 3 V and stable operation during bending of the FTFT. Additionally, IWO TFTs were implemented as synapses, the building block for neuromorphic computing. Paired-pulse facilitation up to 138% was observed and showed an exponential decay resembling chemical synapses. Utilizing this characteristic, a high-pass dynamic temporal filter was devised providing increased gain from 1.55 to 21 when frequency was raised from 22 to 62 Hz. The high performance and stability of flexible TFTs obtained with IWO films demonstrate their promise for low-voltage electronic applications.

(Invited) Channel Length Dependence of Mechanical Strain for Flexible (a-IGZO) TFT

We investigated the dependence of mechanical strain upon channel length, in flexible amorphous-indium-gallium-zinc-oxide (a-IGZO) thin-film transistors (TFTs) on 20 μm thick Polyimide substrate by using different radii cylinder. The negative shift of the transfer characteristic associated with strain decreases for increasing channel length (L) and is practically suppressed in devices with L=100 μm. Amorphous oxide semiconductor (AOS) based devices are the future of transparent and flexible displays because of many advantages such as low deposition temperature and low manufacturing [1]-[2]. Recently, flexible a-IGZO TFTs on plastic substrates have been enthusiastically studied because they have the advantage of being thinner, lighter, bendable, rollable, and unbreakable [3]-[4]. Fig. 1 (a)-(c) shows the effects of vertical mechanical bending on the electrical performance of the flexible TFTs up to 0.80% strain having the TFT channel width (W) = 50 μm and length (L) = 10, 50, and 100 μm, respectively. A distinct robust TFT performance is observed by long channel TFT (L = 100 μm) as compared to short channel TFT (L = 10 μm) under the same strain condition. All the TFTs exhibited a negative shift of VTH (V) after mechanical strain. Negative VTH (V) shift under mechanical strain is thought to generation of donor-like defects (ΔNGD) at the bending part of the TFT channel [5], which might be at the center part of the channel. This highly strained channel region might generate more defects, resulting in an increase of carrier concentration. It has been reported that long channel length TFTs are less sensitive against the generation of deep donor-like defects [6] which also support our experimental results. Therefore, the TFT with different channel lengths can have a different change in transfer curve. We also performed TCAD simulation to fit the data shown in Fig.1. Circles represent measurement data and solid lines TCAD fitting. In the TCAD simulation, we adopt density of states (DOS) parameters from Mehedi et al.[5]. We also found that the increment of defect states after different strain. These defects are mainly oxygen vacancies [5]-[8]. Therefore, it is confirmed by experimental results and TCAD simulation that the long channel TFTs are more robust and generation of oxygen vacancy might be the origin of the instability under mechanical bending strain. References S. Lee, J. Shin, and J. Jang, Adv. Funct. Mater., 27, 1604921 (2017).S. Lee, D. Jeong, A. Takagi, M. Mativenga, and J. Jang, Adv. Funct. Mater., 27, 1700437 (2017) .H. Nishide, and K. Oyaizu, Science, 319, 5864, PP. 737-738, (2008).M. Koo, K. I. Park, S.-H. Lee, M. Suh, D. Y. Jeon, J. W. Choi, K. Kang, and K. J. Lee, “Nano lett., 12, 9,(2011).M. M. Hasan, M. M. Billah, M. N. Naik, J.G. um and J. Jang, IEEE Electronic Device Letter, 38, 8, (2017).J. G. Um, M. Mativenga, P. Migliorato and J. Jang, App. Phys. Lett., 117, 23, (2015).M. M. Billah, M. M. Hasan and J. Jang, IEEE Electronic Device Letter, 38, 7, (2017).M. M. Hasan, M. M. Billah, and J. Jang, IEEE Electronic Device Letter, 39, 2, (2018). Figure 1

Reliability of Al2O3/In-Si-O-C Thin-Film Transistors with an Al2O3 Passivation Layer under Gate-Bias Stress

Introduction Bottom-gate-type thin-film transistors (TFTs) have an advantage of active channel protection because the In-Si-O-C channel can be formed in the final fabrication process. However, it still remains a big issue of poor stability because the back-side surface of the In-Si-O-C channel is directly exposed to the environmental conditions, and some charges can easily occur due to the adsorption and desorption of gaseous species in air. To overcome this problem, the formation of a passivation layer is one promising process to protect the In-Si-O-C channel. Various inorganic materials, such as SiO2, Si3N4, and Al2O3, have been characterized as passivation layer. Al2O3 layer deposited by atomic layer deposition (ALD) has exhibited excellent passivation capabilities for realizing the stable high-mobility oxide TFTs [1]. Al2O3 passivation layers, which deposited by sputtering methods or the ALD process, generally have thicker film of over 20 nm, and a post-deposition annealing process is sometimes performed to improve the quality of the Al2O3 layer [2, 3]. However, there is no report on the influences of growth temperature and thickness of the Al2O3 passivation layer on the reliability for In-Si-O-C TFTs have been extensively studied. In this paper, we studied gate-bias stress instability of bottom-gate-type Al2O3/In-Si-O-C TFT with an Al2O3 passivation layer, which deposited by low-temperature ALD at 50 °C. We also compared transistor properties of Al2O3 gate insulator fabricated ALD and PE-ALD under gate-bias stress conditions. Experiment A 50-nm-thick Pt film as the gate electrode was deposited on Si substrate using an e-beam evaporator, followed by patterned by a photolithographic process. Next, a 30-nm-thick Al2O3 gate insulator was deposited on the Pt gate electrode by ALD and PE-ALD at 300 °C using trimethylaluminium precursor and H2O oxidant gas and plasma oxygen gas, respectively, subsequently patterned using a dry etching process. A 10-nm-thick In-Si-O-C channel was formed on the Al2O3 gate insulator through a stencil shadow mask at room temperature by co-sputtering using In2O3 and SiC targets under an Ar/O2 (11.0/1.0) atmosphere at 0.2 Pa. Post-deposition annealing was then performed at 300 °C for 60 min in air. An Au (100 nm)/Ti (10 nm) layer was deposited by the thermal evaporation method as the source and drain electrodes. Post-metal deposition annealing was performed at 250 °C for 10 min in O3. Finally, an Al2O3 passivation layer was covered on the back-side surface of the In-Si-O-C channel by ALD at 50 °C using TMA and H2O gases. The thickness of the Al2O3 passivation layer was varied to 2 nm (AlO-2), 5 nm (AlO-5), and 10 nm (AlO-10) by changing the number of ALD cycles. Results and Discussion Figure 1 shows a cross-sectional schematic of the fabricated bottom-gate-type Al2O3 insulator/In-Si-O-C channel TFT with an Al2O3 passivation layer. The channel length and width of the TFT used in this study were 350 μm and 1000 μm, respectively. Figure 2 shows the threshold voltage shift (ΔV th) behavior of all devices as a function of the Al2O3 passivation layer thickness under negative gate-bias stress (NBS) conditions. A significant negative V th shift appeared with the w/o device. The negative V th shift is generally recognized to cause hole charge trapping in the gate insulator and at the Al2O3 insulator/In-Si-O-C channel interface. The holes are thought to be due to absorbed H2O molecules on the back-side of In-Si-O-C channel. The ΔV th of the AlO-2 and AlO-5 devices were slightly reduced compared to the w/o device. On the other hand, the ΔV th of the AlO-10 device were exhibited negligible small value, indicating that the thickness of Al2O3 as a passivation layer is required to be 10 nm or more. Here, the Al2O3 passivation layer which contains residual carbon impurities has low quality because of low-temperature ALD at 50 °C [4]. However, noted that this Al2O3 film can effectively passivate the defects from absorbed H2O molecules. Low-temperature processable Al2O3 passivation layer can be expected in flexible substrate. Conclusions We investigated gate-bias stress instability of bottom-gate-type Al2O3/In-Si-O-C TFTs with the Al2O3 passivation layer, which deposited by low-temperature ALD at 50 °C. The AlO-10 device was exhibited negligible small ΔV th, which has no influence of H2O molecules. We found that the low-temperature fabricated Al2O3 film is essential for suppressing influence of absorbed H2O molecules. Acknowledgment This work was supported by Grant-in-Aid for JSPS Fellows.

Gate-induced drain leakage current characteristics of p-type polycrystalline silicon thin film transistors aged by off-state stress

Thin film transistors have become crucial components of several electronic display devices. However, high leakage current is a frustrating impediment to increasing the efficiency of these transistors. We have performed an experimental and quantitative study on the effects of off-state bias stress on the characteristics of a p-type polycrystalline silicon (poly-Si) thin film transistor (TFT). The gate-induced drain leakage (GIDL) current under off-state bias stress conditions was investigated by changing gate-source voltage (Vgs) and drain-source voltage (Vds). Off-state bias stress was found to dramatically increase the threshold Vgs from 1 to 11 V, thereby increasing the voltage needed to turn off the TFT, without causing significant changes in on-state current or subthreshold swing. We developed local defect creation and charge trapping models for a technology computer-aided design simulation platform to understand the mechanisms underlying these observed effects. Using the model, we showed that off-state stress induces charge trapping within the local defects of a high electric field region in the TFT channel near the drain. This reduces the electric field and thermionic field-emission current, which in turn lowers the GIDL current by increasing threshold voltage Vgs.

Low-temperature (150 °C) activation of Ar+O2+H2-sputtered In–Ga–Zn–O for thin-film transistors

In–Ga–Zn–O (IGZO) sputtering in an Ar, O2, and H2 atmosphere followed by annealing represents an effective method for defect reduction of the resulting films. The carrier density of Ar+O2+H2-sputtered IGZO films increases with increasing H2 amount during sputtering; however, we found that the increased carrier density was markedly decreased by annealing even at 150 °C. The Ar+O2+H2-sputtered IGZO was used as the active channel in thin-film transistors (TFTs), which led to markedly improved electrical properties after annealing at 150 °C, compared with those obtained using conventional Ar+O2-sputtered films. The proposed method is very promising for low-temperature-processed oxide TFTs.

Off-current reduction in p-type SnO thin film transistors

SnO is one of the few candidates for p-type oxide thin film transistors (TFTs) because it retains a reasonable high hole mobility in a nanocrystalline film. However, the high off-current of SnO TFT limits its usefulness. In this work, SnO TFTs were fabricated using thermal evaporation under ultra-high vacuum. In order to decrease the off-current in p-type SnO thin film transistors (TFTs), we used yttrium to reduce n-type minority charges in the channel. The on/off ratio of the TFT increases from 102 to 5 × 104 and the mobility of the TFT in the saturated regime reduces from 1.6 to 1.4 cm2/V s when the SnO channel is doped with 1 wt. % of Y. Grazing incidence X-ray diffraction and X-ray photoelectron spectroscopy reveal that the reduction of SnO2 in the Y-doped SnO TFT channel is the main reason for the improvement in the TFT characteristics.

Reduced Mechanical Strain in Bendable a-IGZO TFTs Under Dual-Gate Driving

We report the reduced strain in bendable amorphous indium–gallium–zinc oxide (a-IGZO) thin-film transistor (TFT) with dual-gate (DG) driving. The performance of the fabricated TFTs on a 15- $\mu \text{m}$ polyimide substrate are sensitive to bending radius and the changes in threshold voltage ( $\Delta \mathrm {V}_{\mathrm {TH}}$ ) fits well by analytical modeling. DG driving TFTs are found very stable under tensile strain ( $\varepsilon$ ) compared with single-gate (SG) TFTs. Technology computer-aided design strain distribution confirms a 25% less strain on a-IGZO layer for DG TFT structure compared with SG TFT and the maximum tensile strain is observed at the center of the TFT channel. The SG and DG TFTs under 1 mm radius exhibit $\Delta \mathrm {V}_{\mathrm {TH}}$ (V) shift of −1.5 and −0.3 V, respectively, from the flat state, which is due to the reduced strain in the DG TFT.

Self-Assembled Photochromic Molecular Dipoles for High-Performance Polymer Thin-Film Transistors.

The development of high-performance multifunctional polymer-based electronic circuits is a major step toward future flexible electronics. Here, we demonstrate a tunable approach to fabricate such devices based on rationally designed dielectric super-lattice structures with photochromic azobenzene molecules. These nanodielectrics possessing ionic, molecular, and atomic polarization are utilized in polymer thin-film transistors (TFTs) to realize high-performance electronics with a p-type field-effect mobility (μFET) exceeding 2 cm2 V-1 s-1. A crossover in the transport mechanism from electrostatic dipolar disorder to ionic-induced disorder is observed in the transistor characteristics over a range of temperatures. The facile supramolecular design allows the possibility to optically control the extent of molecular and ionic polarization in the ultrathin nanodielectric. Thus, we demonstrate a 3-fold increase in the capacitance from 0.1 to 0.34 μF/cm2, which results in a 200% increase in TFT channel current.

1.1: Invited Paper: TFT Backplane for Display

Thin Film Transistors (TFT) are being widely used as backplane to drive display components, such as LCD, OLED, and even u‐LCD. A‐Si, poly Si, oxide, and organic are common materials for TFT. Mobility, scale‐up and long term stability are among the key concern for TFT. Vertical channel thin film transistors (VTFTs) are proposed as an effective approach to reduce driving voltage and power consumption for achieving high speed and high resolution displays. Considering that oxide semiconductors have large‐area compatible processes, it will be better to find a method for achieving low driving voltages with conventional optical lithography machines used for large area display panels. In this talk, we will review the state of art of the vertical TFTs and explore the major fabrication issues. In addition, we will examine amorphous indium gallium zinc oxide (a‐IGZO) vertical channel TFT fabricated at low temperature to evaluate the impact of gate dielectric on electric characteristics of the vertical vis‐à‐vis planar TFTs. VTFTs employing vertical amorphous a‐IGZO channel of 500 nm have been fabricated without additional photolithography process. The various issues related to the improved device performance will be addressed. Solution based organic TFT will also be examined to explore its feasibility for backplane to drive display and other components.

Amorphous-InGaZnO Thin-Film Transistors Operating Beyond 1 GHz Achieved by Optimizing the Channel and Gate Dimensions

Amorphous indium–gallium–zinc oxide (a-InGaZnO or a-IGZO) has already started replacing amorphous silicon in backplane driver transistors for large-area displays. However, hardly any progress has been made to commercialize a-IGZO for electronic circuit applications mainly because a-IGZO transistors are not yet capable of operating at gigahertz frequencies. Here, nanoscale a-IGZO thin-film transistors (TFTs) are fabricated on a high-resistivity silicon substrate with a Ta2O5 gate dielectric. Carrier mobilities up to 18.2 cm2V−1s−1 have been achieved. By optimization of the TFT channel length and contact overlap, we are able to demonstrate current gain and power gain cutoff frequencies at 1.24 and 1.14 GHz, respectively, both beyond the 1-GHz benchmark. Such a performance may have implications in developing at least medium performance, a-IGZO-TFTs-based circuits for low-cost or flexible electronics.

Highly Stable AlInZnSnO and InZnO Double-Layer Oxide Thin-Film Transistors With Mobility Over 50 $\text{cm}^{2}/\text{V} \cdot \text{s}$ for High-Speed Operation

We present high-mobility back channel etch Al–In–Zn–Sn–O/In–Zn–O (IZO) double-layer channel thin-film transistors (TFTs). The field-effect mobility of 53.2 $\text{cm}^{2}/\text{V} \cdot \text{s}$ , threshold voltage of 0.5 V, and subthreshold swing of 0.15 V/decade were obtained with a thin IZO-inserted double-layer channel TFT. The positive bias stability was improved with an IZO-inserted double-layer channel. We fabricated 13-stage ring oscillators, which exhibited an oscillating frequency of 296 kHz at ${V} _{\text {DD}} = {20}$ . These results demonstrate that the proposed double-layer channel oxide TFT can be used for demanding applications such as backplane devices for ultrahigh resolution display.

Effects of Channel Type and Doping on Hysteresis in Low-Temperature Poly-Si Thin-Film Transistors

The influence of channel type and doping on hysteresis in the current–voltage characteristics of poly-Si thin-film transistors (TFTs) has been investigated using p-/n- and intrinsic/B-doped channel TFTs. The hysteresis is greater in the p-channel than the n-channel and decreases in the p-channel but increases in the n-channel as the channel is doped with B. The energy profiles of the border trap density show asymmetry, in which the trap density is greater in the lower half of the bandgap. The border trap density increases as the channel is doped with B. The difference in border trap density between the near bandedge and near midgap energy levels is greater in the p-channel than the n-channel and decreases in the p-channel but increases in the n-channel as the channel is doped with B. The results show good agreement between the hysteresis effect and the energy profiles of border trap density.