Thin-film Transistor Technology Research Articles

(Invited) Recent Advances in Oxide-TFT Technology for Next-Generation Sustainable Electronics

Metal-oxide semiconductors and the relevant electronic devices, particularly thin-film transistor technology are nowadays acknowledged as promising elements for the development of next-generation ubiquitous sustainable electronics. Due to their superior characteristics, such as high electron mobility even in disordered structures, wide-bandgap nature, and low-temperature processability, these technologies offer high-performance, low-power device operation, and cost-effective fabrication processes. A n-channel oxide-TFT using amorphous In-Ga-Zn-O (a-IGZO) channel has already been successfully commercialized as a pixel TFT back-plane in several state-of-art displays such as high-resolution active-matrix flat panel display (AMFPD), large-sized liquid-crystal display (LCD), and high-resolution organic light-emitting display (OLED). Oxide electronics continues to explore new device applications, extending beyond display technologies to areas such as sensors and back-end-of-line (BEOL) transistors, paving the way for next-generation electronics.Here I present recent advancements of oxide-TFT technology, mainly based on our research activity. Firstly, we will assess the advancements made in n-channel/p-channel oxide thin-film transistor (TFT) technology and address the outstanding challenges that need to be resolved for the development of next-generation electronics. We will also discuss various types of oxide-TFT-based circuit applications, such as NMOS (n-channel metal-oxide semiconductor), PMOS (p-channel metal-oxide semiconductor), and CMOS (complementary metal-oxide semiconductor).

Development of Vertical Structured TFT Using Interfacial Oxidation

As advancements in display technology persist, ongoing research endeavors into Thin-Film Transistors (TFTs) to move forwards display evolution endure. Among the various semiconductors in TFT technologies, oxide TFTs have garnered considerable attention due to their manifold advantages, including heightened electron mobility in comparison to a-Si, superior transmittance, and suitability for medium to large-scale applications.Recent developments in display engineering suggest that Augmented Reality (AR), Virtual Reality (VR), and flexible displays are the vanguards of next-generation displays. These rapidly expanding applications desire several specifications for TFTs, such as minimalized occupied area, high resolution, low-power operation, etc. Given the challenges associated with fulfilling these mentioned requirements using conventional TFT technologies is difficult due to the facing physical limitations. Therefore, a novel enhancement methodology becomes necessary. In response to this necessity, there has been a rapidly growing interest in Vertical TFTs (VTFTs), which represent a structural refinement of next-generation TFTs in recent years.VTFT was propounded by Professor Y. Uchida of Japan in 1984 utilizing a-Si [1]. In the V-TFT structure, the source and drain electrodes are vertically separated by an insulator spacer. The annel lies between them, attached to the spacer's sidewall, directing carrier flow vertically. Therefore, VTFTs can easily achieve short channel lengths under 1µm, larger aspect ratios W/L, and higher packaging density, greatly reducing the occupied area over conventional TFTs. Nevertheless, the development of previously proposed VTFTs facing into unresolved challenges, including process complexity attributable to the requisite spacers and interlayer dielectrics (ILDs), as well as reduced yields due to the process complexity.M. Chandra Sekhar et al., have postulated a methodology [2] employing the oxide layer formed at the interface as a leading layer during the deposition of metal and oxide, subsequently evaluating its reliability. This oxide film is termed Interfacial Oxidation.As illustrated in Figure 1, our study introduces a novel VTFT processing methodology assured to improve process complexity and low yield rates, which represent inherent challenges in conventional VTFT fabrication.Tantalum (Ta), characterized by low Gibbs's free energy, is harnessed as the gate electrode, while Indium Tin Oxide (ITO) serves as the source and drain electrodes. Concurrently, an interfacial oxide film occurs through the heat treatment-induced interfacial oxidation reaction between ITO and Ta, serving as an insulating film. This innovative VTFT processing protocol offers the following advantages: 1) Substituting the gate electrode prevents the necessity for conventional spacers and prevents the deposition of an interlayer insulating film, thereby simplifying the fabrication process considerably. 2) The insulating layer conforms to the contour of the gate electrode, obviating the deposition process for the insulating layer. This prevents defects that may emerge during additional insulating layer processing, mitigating electrode damage and averting diminished yields. 3) As a result, VTFT configuration offers an exceedingly short channel in the nm range, corresponding to the gate thickness, thereby producing a low power consumption—an outstanding advantage for driving applications.Consequently, this research holds the potential to substantially contribute to the advancement of low-power electronic devices and the realization of next-generation display applications, encompassing form factor innovations, automotive integration, and AR/VR implementation, while simultaneously addressing the challenges posed by vertical TFT technology. Figure 1

(Invited) TFT Technologies from Commercial Displays to Emerging Immersive Displays

Thin film transistors (TFTs) are used in displays providing the function of controlling light transmission, such as LCDs, reflection, such as electrophoretic displays, or emission, such as LED or OLED displays, from individual pixels in a 2D array – named active matrix flat panel displays (AMFPDs). The advantages of using TFTs in displays include gray-scale, dynamic, crosstalk-free, and uniform images as well as low power consumption over a large area.The first report on the functional TFT and the outline and demonstration of the TFT LCD triggered worldwide research and development activities on AMFPDs. The lack of commercial products on the market is due to the bottleneck in the manufacturing technology, i.e., availability of a large area, low temperature, and high throughput process. The invention of the a-Si: H TFT in 1979 solved the production problem [1]. TFT LCDs were quickly introduced to the market. The size of the commercial displays changed from 4” in the 1980s to 98” in 2023, as shown in Figure 1 [2]. Extremely low power consumption electrophoretic displays were also introduced to the market. The main drawback of the a-Si:H TFT is the low field effect mobility, e.g., £1 cm2/Vs, which limits applications in driver circuits as well as very high speed or high driving current displays. Poly-Si TFTs can have mobilities up to 2 orders of magnitude higher than that of a-Si:H TFT. However, due to the complicated process conditions, their applications have been limited to small-sized displays, such as 20-inch LCDs, OLEDs, and μ-LEDs. The driver circuits were successfully integrated into the display. The a-IGZO TFT has a field effect mobility between those of a-Si:H TFT and poly-Si TFT. The a-IGZO TFT array can be mass-produced at a low temperature on a large substrate. Therefore, since the first report of the a-IGZO TFT in 2004 [3], it was quickly accepted by the display industry. Commercial OLEDs and μ-LEDs based on a-IGZO TFTs have been manufactured. Driver circuits have also been demonstrated. However, due to the lack of the p-channel TFT, the CMOS circuit has to be made of the n-channel oxide TFT and the p-channel poly-Si TFT.Recently, due to the advancement in semiconductor technology and software, immersive displays have emerged in areas of entertainment, industry, education, etc. Displays play an important role in this trend because the human interface with the data is critical to these functions [4]. There are some basic requirements on the display concerning image quality, power consumption, response to the environment, and the user’s physical condition. In many applications, the size, weight, and flexibility of the display are important. In this paper, the authors will discuss these issues based on the existing TFT technology and explore opportunities. Kuo, ECS Interface, 22(1), 55-61, 2013.A commercial TCL 98" LCD downloaded from Google.Nomura, et al., Nature, 432, 488-492, 2004.Kuo, IEEE J. Immersive Displays, 1, 28-40, 2024. Figure 1

A Sliding-Kernel Computation-In-Memory Architecture for Convolutional Neural Network.

Presently described is a sliding-kernel computation-in-memory (SKCIM) architecture conceptually involving two overlapping layers of functional arrays, one containing memory elements and artificial synapses for neuromorphic computation, the other is used for storing and sliding convolutional kernel matrices. A low-temperature metal-oxide thin-film transistor (TFT) technology capable of monolithically integrating single-gate TFTs, dual-gate TFTs, and memory capacitors is deployed for the construction of a physical SKCIM system. Exhibiting an 88% reduction in memory access operations compared to state-of-the-art systems, a 32 × 32 SKCIM system is applied to execute common convolution tasks. A more involved demonstration is the application of a 5-layer, SKCIM-based convolutional neural network to the classification of the modified national institute of standards and technology (MNIST) dataset of handwritten numerals, achieving an accuracy rate of over 95%.

Enhancing the Performance of Electrochemical RAM (ECRAM) through Modeling Guided Device Engineering

Traditionally, the only ions allowed or welcomed by the microelectronic industry are those that act as fixed dopants. The issue of mobile ions became welcome primarily due to the memristor technology however, thin film transistor technologies benefit from them too. The electrochemical (transistor) random access memory (ECRAM) is emerging as a promising building block for multi-level neuromorphic computing. Using FAB-compatible materials we construct the ECRAM using CuOx as the gate and ions source (Cu+). The morphology of the HfOx gate insulator layer is tuned to render it ion transporting such that it can act as a uniform electrolyte layer. Lastly, the channel material is WOx with tungsten metal as the source/drain contact.While there are several reports of ECRAM devices, the operation mechanisms are not fully known/understood thus withholding progress of this field. Using the Sentaurus device simulator by Synopsis, including the hydrogen diffusion module, we simulate the mixed ionic electronic operation of the device. We have recently reported that by fitting the simulation to the device performance, we could identify the potentiation mechanism (i.e., insulator charging) and the occurrence of copper plating that takes place under high Cu+ ion flux (as in fast charging of Li batteries).[1]In the first part of the talk, we will expand on the chemical-physics details of the ECRAM device mentioned above. Next, we will present a new device architecture where we remove the WOx layer and study the ionic-electronic conduction of a modified HfOx layer. By fine-tuning the stoichiometry of the HfOx layer, it assumes both roles of ionic electrolyte and electronic conducting channel. Following detailed modelling of the measured properties, we introduce AlO2 as an ionic barrier layer at the WOx/HfOx interface to enhance the ionic retention of the HfOx layer. Using the above three device architectures in conjunction with the mixed ionic-electronic device simulation we reveal the role of the two memory mechanisms: a) Electric field-activated ion transport and b) Structure-induced trapping by ion-barrier layers.Reference[1] Nir Tessler, Nayeon Kim, Heebum Kang, Jiyong Woo; Switching mechanisms of CMOS-compatible ECRAM transistors—Electrolyte charging and ion plating. J. Appl. Phys. 21 August 2023; 134 (7): 074501. https://doi.org/10.1063/5.0154153 Figure 1

Three-dimensional integrated metal-oxide transistors

AbstractThe monolithic three-dimensional vertical integration of thin-film transistor (TFT) technologies could be used to create high-density, energy-efficient and low-cost integrated circuits. However, the development of scalable processes for integrating three-dimensional TFT devices is challenging. Here, we report the monolithic three-dimensional integration of indium oxide (In2O3) TFTs on a silicon/silicon dioxide (Si/SiO2) substrate at room temperature. We use an approach that is compatible with complementary metal–oxide–semiconductor (CMOS) processes to stack ten n-channel In2O3 TFTs. Different architectures—including bottom-, top- and dual-gate TFTs—can be fabricated at different layers in the stack. Our dual-gate devices exhibit enhanced electrical performance with a maximum field-effect mobility of 15 cm2 V−1 s−1, a subthreshold swing of 0.4 V dec−1 and a current on/off ratio of 108. By monolithically integrating dual-gate In2O3 TFTs at different locations in the stack, we created unipolar invertor circuits with a signal gain of around 50 and wide noise margins. The dual-gate devices also allow fine-tuning of the invertors to achieve symmetric voltage-transfer characteristics and optimal noise margins.

Review of Integrated Gate Driver Circuits in Active Matrix Thin-Film Transistor Display Panels.

Many advanced technologies have been employed in high-performance active matrix displays, including liquid crystal displays, organic light-emitting diode displays, and micro-light-emitting diode displays. On the other side, there exists a strong demand for cost reduction, and it is one of the low-cost schemes for integrating the driver circuit in a panel based on thin-film transistor technologies. This paper reviews the overall concept, operation principles, and various circuit approaches in shift registers for scanning pulse generation. In addition, it deals with the implementation of additional functionalities in gate drivers to support pixel compensation, multi-line driving, in-cell capacitive touch screen, pixel sensing, and adaptive scanning region control.

Interfacial thermal resistance effect in self-aligned top-gate a-IGZO thin film transistors

This study investigates the interfacial thermal resistance effect, primarily associated with the bottom-gate stack, in self-aligned top-gate amorphous indium gallium zinc oxide (a-IGZO) thin-film transistors (TFTs). We analyze self-heating and heat transfer characteristics across three different a-IGZO TFT configurations: single-gate, dual-gate type 1, and dual-gate type 2. Temperature maps, corresponding to various bias conditions, are acquired using infrared thermal microscopy. The extracted values of thermal resistance reveal a significant disparity between single- and dual-gate configurations. This suggests that the bottom-gate stack in a-IGZO TFTs, including the interfaces, notably impedes heat dissipation. These findings offer crucial insights into the power dissipation aspects of TFT technology, highlighting the importance of interfacial design for thermal management in advanced electronic devices.

Dual-bootstrapping gate driver circuit design using IGZO TFTs

To promote the integration of thin-film transistor (TFT) gate driver circuit technology into high-resolution large-size display application with narrow bezel, achieving high speed is a critical challenge. This paper proposed a dual-bootstrapping TFT integrated gate driver circuit for large-size display. The over-drive voltage of the driving TFT was increased both at the rising and falling edges of the output waveforms. To validate the circuit feasibility, the proposed circuit was fabricated using amorphous indium-gallium-zinc-oxide (a-IGZO) TFT technology and measured in terms of transient response with cascaded stages and reliability tests over long operating time. Compared to conventional approaches, the proposed gate driver demonstrates a 39 % reduction in the falling time as well as compact layout. Therefore, the proposed gate driver schematic is well-suited for large-size display applications that involves heavy resistance–capacitance (RC) loadings and require high resolution above 8 K.

P‐32: Dual Gate Amorphous Silicon Thin Film Transistor Technology for High Brightness and High Frame Rate Outdoor Display Panels

In this paper, we present the development of a dual‐gate (DG) architecture for hydrogenated amorphous silicon thin film transistors (a‐Si:H TFTs). The aim is to address the challenges of low on‐state current (Ion) and light‐induced degradation in traditional single‐gate (SG) TFTs. The experimental results demonstrate that the DG‐TFT exhibits significantly higher Ion compared to the SG‐TFT, and the improvement depends on the thickness of the top gate insulator. Additionally, the threshold voltage (Vth) can be adjusted by applying the top gate voltage, allowing for a full‐ swing modulation coefficient of approximately 0.2. To ensure long‐term stability, a light‐blocking layer has been incorporated as the top gate electrode, enabling the DG‐ TFT to maintain its initial properties even under intense illumination conditions of up to 28,000 nits.

Revolutionizing electronics with oxide thin-film transistor technology

Revolutionizing electronics with oxide thin-film transistor technology

Multi-project wafers for flexible thin-film electronics by independent foundries

Flexible and large-area electronics rely on thin-film transistors (TFTs) to make displays1–3, large-area image sensors4–6, microprocessors7–11, wearable healthcare patches12–15, digital microfluidics16,17 and more. Although silicon-based complementary metal–oxide–semiconductor (CMOS) chips are manufactured using several dies on a single wafer and the multi-project wafer concept enables the aggregation of various CMOS chip designs within the same die, TFT fabrication is currently lacking a fully verified, universal design approach. This increases the cost and complexity of manufacturing TFT-based flexible electronics, slowing down their integration into more mature applications and limiting the design complexity achievable by foundries. Here we show a stable and high-yield TFT platform for the fabless manufacturing of two mainstream TFT technologies, wafer-based amorphous indium–gallium–zinc oxide and panel-based low-temperature polycrystalline silicon, two key TFT technologies applicable to flexible substrates. We have designed the iconic 6502 microprocessor in both technologies as a use case to demonstrate and expand the multi-project wafer approach. Enabling the foundry model for TFTs, as an analogy of silicon CMOS technologies, can accelerate the growth and development of applications and technologies based on these devices.

The fabrication and characterization of direct conversion flat panel X-ray imager with TlBr film

The novel direct conversion flat panel detectors (FPDs) utilizing thallium bromide (TlBr) films are developed and characterized in this study. Thin TlBr films, deposited using an evaporation technique, achieved thicknesses of 10 μm and 50 μm. A pixel sensor array, with a pixel size of 235 × 235 μm2 and a sensitive area of 29.61 × 39.48 mm2, was developed using low-temperature polysilicon thin-film transistor (LTPS TFT) technology as the initial study to explore performance characteristics of developed imaging system. The TlBr film was characterized based on the current-voltage (I–V) profile, showing a resistivity of 2.78 × 1010 Ω·cm. The LTPS TFT showed a leakage current of about 10−13 A, while the noise of TlBr FPD system was around 104 e− rms, primarily limited by the readout system. The detector system was characterized using radiation from an X-ray tube with a voltage in the range of 30 kV–100 kV and a current of 2 mA, involving an X-ray test chart as the object with the processing time of 18.15–18.30 ms per frame. Based on the contrast and contrast-to-noise ratio (CNR) values, the 10 μm and 50 μm TlBr FPD clearly captured the image in operation between 30 kV and 100 kV. The 50 μm TlBr FPD demonstrated improved sensitivity, showing pixel values with 10 times higher intensity and enhanced line pair detail at 30 kV X-ray operation. The 10 μm TlBr achieved spatial resolution of 267 μm full width at half maximum (FWHM), while the 50 μm TlBr achieved 250 μm FWHM. In the X-ray imaging demonstration, the shape and structure of anchovy was clearly distinguished. The TlBr film FPD presents promising potential for a room temperature X-ray imager.

Selenium-alloyed tellurium oxide for amorphous p-channel transistors.

Compared to polycrystalline semiconductors, amorphous semiconductors offer inherent cost-effective, simple and uniform manufacturing. Traditional amorphous hydrogenated Si falls short in electrical properties, necessitating the exploration of new materials. The creation of high-mobility amorphous n-type metal oxides, such as a-InGaZnO (ref. 1), and their integration into thin-film transistors (TFTs) have propelled advancements in modern large-area electronics and new-generation displays2-8. However, finding comparable p-type counterparts poses notable challenges, impeding the progress of complementary metal-oxide-semiconductor technology and integrated circuits9-11. Here we introduce a pioneering design strategy for amorphous p-type semiconductors, incorporating high-mobility tellurium within an amorphous tellurium suboxide matrix, and demonstrate its use in high-performance, stable p-channel TFTs and complementary circuits. Theoretical analysis unveils a delocalized valence band from tellurium 5p bands with shallow acceptor states, enabling excess hole doping and transport. Selenium alloying suppresses hole concentrations and facilitates the p-orbital connectivity, realizing high-performance p-channel TFTs with an average field-effect hole mobility of around 15 cm2 V-1 s-1 and on/off current ratios of 106-107, along with wafer-scale uniformity and long-term stabilities under bias stress and ambient ageing. This study represents a crucial stride towards establishing commercially viable amorphous p-channel TFT technology and complementary electronics in a low-cost and industry-compatible manner.

Flexible Unipolar IGZO Transistor-Based Integrate and Fire Neurons for Spiking Neuromorphic Applications.

In this article, three different implementations of an Axon-Hillock circuit are presented, one of the basic building blocks of spiking neural networks. In this work, we explored the design of such circuits using a unipolar thin-film transistor technology based on amorphous InGaZnO, often used for large-area electronics. All the designed circuits are fabricated by direct material deposition and patterning on top of a flexible polyimide substrate. Axon-Hillock circuits presented in this article consistently show great adaptability of the basic properties of a spiking neuron such as output spike frequency adaptation and output spike width adaptation. Additional degrees of adaptability are demonstrated with each of the Axon-Hillock circuit varieties: neuron circuit threshold voltage adaptation, differentiation between input signal importance, and refractory period modulation. The proposed neuron can change its firing frequency up to three orders of magnitude by varying a single voltage brought to a circuit terminal. This allows the neuron to function, and potentially learn, at vastly different timescales that coincide with the biologically meaningful timescales, going from milliseconds to seconds, relevant for circuits meant for interaction with the environment. Thanks to careful design choices, the average measured power consumption is kept in the nW range, realistically allowing upscaling towards the spiking neural networks in the future. The spiking neuron with refractory period modulation presented in this work has an area of 607.3 μm × 492.2 μm, it experimentally demonstrated firing rates as low as 11.926 mHz, and its energy consumption per spike is ≈ 700 pJ at 30 Hz.

High Reliability Tungsten-Doped Indium Zinc Oxide Thin Film Transistors for Display Applications

Recently, flat panel display technologies are based on amorphous silicon (a-Si), polycrystalline silicon (poly-Si) or amorphous oxide semiconductor (AOS) thin film transistors (TFTs) technology. In order to reach higher performance for ultra-high resolution display applications, the material selection for the channel layer is vital. AOS TFTs drawn lots of attention because of its advantages such as low leakage current, high driving current and high uniformity [1,3]. In this work, we presented a novel amorphous oxide semiconductor (AOS) material of gallium-free a-InWZnO thin film transistors (IWZO TFTs) which is very promising to be applied for ultra-high resolution display technology. Experiment In this work, we demonstrated the structure of a-IWZO TFTs processes. Figure 1 shows the schematic of the TFT cross-section. After growing a 550 nm thermal oxide layer as buffer layer, a 25-nm-thick of molybdenum was deposited by DC-sputter as the bottom gate electrode. A 10-nm-HfO2 was deposited by plasma-enhanced atomic layer deposition (PEALD) system as high-κ gate dielectric (GI). Then, post deposition annealing (PDA) was carried out to enhance the quality of the insulator layer. Next, an ultra-thin body a-IWZO was deposited by RF-sputter as channel layer. Finally, source and drain were defined by lift-off process and the gate contact via was etched by dry etching to finish the device fabrication. Result and Discussion Figure 1(b) shows the negative gate bias stress (NGBS) transfer curve (ID-VG) of a-IWZO TFTs with passivation layer. The experimental results have shown that passivation layer could keep the back channel of IWZO channel from exposing to oxygen and hydrogen from the atmosphere. Without the passivation layer, the back channel would contact moisture leading the diffused hydrogen atoms to fill oxygen vacancy sites and de-trap free carriers, causing the VTH shifts negatively. The ultra-thin a-IWZO TFTs with passivation layer exhibited a low subthreshold swing (S.S.) of 89.7 mV/dec, high on/off current ratio (ION/IOFF) of 2.1×107 and small threshold voltage shift (ΔVth) of -0.097 V during NGBS of -2MV/cm with 2000s. To sum up, the passivation layer could enhance the a-IWZO TFTs reliability. Reference [1] Kamiya, H. Hosono, NPG Asia Mater., vol. 2, pp. 15, 2010.[2] Nomura, H. Ohta, A. Takagi, T. Kamiya, M. Hirano, and H. Hosono, nature, vol. 432, no. 7016, pp. 488-492, 2004.[3] Y. Kuo, C. M. Chang, I. H. Liu, and P. T. Liu, Scientific reports, vol. 9, no. 1, pp. 1-7, 2019. Figure 1

High-performance thin-film transistors based on aligned carbon nanotubes for mini- and micro-LED displays

Inorganic mini-LEDs (mLEDs) and micro-LEDs (μLEDs) have ultrahigh luminance and long lifetimes, and are challenging liquid crystal displays (LCDs) and organic light-emitting diode (OLED) displays for next-generation displays. Backplane thin-film transistors (TFTs) for mLED/μLED displays with high mobility and large driving current are under development as currently widely used backplane active materials such as crystalline silicon (CMOS Si), amorphous silicon (a-Si), low-temperature polycrystalline silicon (LTPS), and metal oxides are facing difficulties to meet the requirements. Semiconducting carbon nanotubes (s-CNTs) have long been considered as promising materials for TFTs because of their unique electronic properties. However, TFTs based on s-CNT random networks show inadequate performance due to large amounts of inter-tube junctions. Here, we report high performance TFTs based on wafer-scale, high-density aligned s-CNT array (A-CNT) for mLED/μLED driving backplanes. These A-CNT TFTs with micrometer scale channel length were fabricated using standard semiconductor manufacturing process, and exhibited mobility as high as 160 cm2/Vs and driving current as large as 417 μA/μm at operation voltage of ∼3 V, exceeding commercially available TFTs with similar device sizes. In addition, these A-CNT TFTs have demonstrated good driving capability for commercial mLEDs in a one-transistor-one-diode (1T1D) pixel circuit configuration, and been capable of driving commercially available mLED/μLED displays. Moreover, a prototype display with 2 × 2 mLED array have been demonstrated with full control of each pixel, manifesting the great potential for A-CNT TFT technology for backplane of mLED/μLED displays.

CFP-Special Issue on “Thin-Film Transistor Technologies”

CFP-Special Issue on “Thin-Film Transistor Technologies”

Integrated Water-Level Sensor Using Thin-Film Transistor Technology.

A low-cost water-level sensor was developed utilizing a capacitive sensor design with only one thin-film transistor (TFT). The integration of the a-IGZO TFT process facilitated the complete integration of the water-level sensor on a substrate, including essential components, such as the transistor, capacitor, wires, and sensing electrode. This integration eliminates the need for a separate mounting process, resulting in a robust sensor assembly. To comprehensively assess the performance of the developed water-level sensor, rigorous evaluations were conducted using both MOSFET and TFT integration. In the case of the water-level sensor featuring a-IGZO TFT integration, a voltage output of 4.2 V was measured when the tank was empty, while a voltage output of 0.9 V was measured when the tank was full. Notably, the integrated sensor system demonstrated a higher output voltage compared with the MOSFET sensor, primarily due to the significantly reduced parasitic capacitance of the TFT. The use of a-IGZO TFT in the integrated sensor system contributes to enhanced sensitivity and accuracy. The lower parasitic capacitance inherent in TFT technology allows for improved voltage measurement precision, resulting in more reliable and precise water-level sensing capability. The development of this integrated water-level sensor holds immense potential for a wide range of applications that require a combination of cost-effectiveness, accurate monitoring, and flexibility in form factor. With its affordability, the sensor is accessible for various industries and applications.

A 6-bit Analog-to-Digital Converter for Electromyography Implemented Using N-Type Metal-Oxide Thin-Film Transistors

Consisting of more than 2000 n-type metal-oxide thin-film transistors (TFTs), a 6-bit analog-to-digital converter (ADC) adopting the subranging architecture is designed, fabricated, characterized and applied to digitize an electromyogram (EMG). Consisting of amplifiers each with a feedback stage for gain-boosting, the comparators at the heart of the ADC incorporate a scheme for compensating the offset error arising from the inevitable non-uniformity of the TFT parameters. Compared to the specifications of reported ADCs based on TFTs, a higher sampling rate of 1000 S/s, a smaller differential non-linearity of 0.76 least-significant bit (LSB) and a smaller integral non-linearity of 0.88 LSB are achieved. Since the same low-temperature TFT technology for fabricating the EMG acquisition system on a flexible substrate is used to construct the ADC, the two could be readily monolithically integrated.