Thin-film Transistor Configuration Research Articles

Bipolar Plasticity in Synaptic Transistors: Utilizing HfSe2 Channel with Direct-Contact HfO2 Gate Dielectrics

The investigation of dual-mode synaptic plasticity was conducted in thin-film transistors (TFTs) featuring an HfSe2 channel, coupled with an oxygen-deficient (OD)-HfO2 layer structure. In these transistors, the application of negative gate pulses resulted in a notable increase in the post-synaptic current, while positive pulses led to a decrease. This distinctive response can be attributed to the dynamic interplay of charge interactions, significantly influenced by the ferroelectric characteristics of the OD-HfO2 layer. The findings from this study highlight the capability of this particular TFT configuration in closely mirroring the intricate functionalities of biological neurons, paving the way for advancements in bio-inspired computing technologies.

Elucidation of electric characteristics for P and N type polycrystalline silicon vertical thin film transistors

P and N type polycrystalline silicon has been applied in thin film transistors (TFTs) for driving a range of displays, and for building up complementary metal oxide semiconductor (CMOS)-like circuits. In one aspect, the high driving current is required, which is usually achieved by improving field effect mobility of the active layer. For another, balanced electrical characteristics are required for achieving CMOS-like logic circuits. In this article, in order to increase driving current, P and N type polycrystalline silicon vertical TFTs configuration is proposed that can get rid of the strict requirement of the field effect mobility in order to increase the driving current. In addition, the balanced electrical properties are demonstrated for P and N type vertical TFTs, which are elucidated by the density of states calculations. The simple Simulation Program with Integrated Circuit Emphasis (SPICE) modelling indicates the potential application in CMOS inverter based on our vertical TFTs.

High-sensitivity hybrid PbSe/ITZO thin film-based phototransistor detecting from 2100 to 2500 nm near-infrared illumination

We report that high absorption PbSe colloidal quantum dots (QDs) having a peak absorbance beyond 2100 nm were synthesized and incorporated into InSnZnO (ITZO) channel layer-based thin film transistors (TFTs). It was intended that PbSe QDs with proportionally less photocurrent modulation can be remedied by semiconducting and low off-current ITZO-based TFT configuration. Multiple deposition scheme of PbSe QDs on ITZO metal oxide thin film gave rise to nearly linear increase of film thickness with acceptably uniform and smooth surface (less than 10 nm). Hybrid PbSe/ITZO thin film-based phototransistor exhibited the best performance of near infrared (NIR) detection in terms of response time, sensitivity and detectivity as high as 0.38 s, 3.91 and 4.55 × 107 Jones at room temperature, respectively. This is indebted mainly from the effective diffusion of photogenerated carrier from the PbSe surface to ITZO channel layer as well as from the conduction band alignment between them. Therefore, we believe that our hybrid PbSe/ITZO material platform can be widely used to be in favour of incorporation of solution-processed colloidal light absorbing material into the high-performance metal oxide thin film transistor configuration.

High-Responsivity Multilayer MoSe2 Phototransistors with Fast Response Time

There is a great interest in phototransistors based on transition metal dichalcogenides because of their interesting optoelectronic properties. However, most emphasis has been put on MoS2 and little attention has been given to MoSe2, which has higher optical absorbance. Here, we present a compelling case for multilayer MoSe2 phototransistors fabricated in a bottom-gate thin-film transistor configuration on SiO2/Si substrates. Under 650-nm-laser, our MoSe2 phototransistor exhibited the best performance among MoSe2 phototransistors in literature, including the highest responsivity (1.4 × 105 AW−1), the highest specific detectivity (5.5 × 1013 jones), and the fastest response time (1.7 ms). We also present a qualitative model to describe the device operation based on the combination of photoconductive and photogating effects. These results demonstrate the feasibility of achieving high performance in multilayer MoSe2 phototransistors, suggesting the possibility of further enhancement in the performance of MoSe2 phototransistors with proper device engineering.

Modification of the optoelectronic properties of two-dimensional MoS2 crystals by ultraviolet-ozone treatment

We report the modification of the optoelectronic properties of mechanically-exfoliated single layer MoS2 by ultraviolet-ozone exposure. Photoluminescence emission of pristine MoS2 monotonically decreased and eventually quenched as ultraviolet-ozone exposure time increased from 0 to 10 min. The reduction of photoluminescence emission accompanied reduction of Raman modes, suggesting structural degradation in ultraviolet-ozone exposed MoS2. Analysis with X-ray photoelectron spectroscopy revealed that the formation of SO and MoO bonding increases with ultraviolet-ozone exposure time. Measurement of electrical transport properties of MoS2 in a bottom-gate thin-film transistor configuration suggested the presence of insulating MoO3 after ultraviolet-ozone exposure. These results demonstrate that ultraviolet-ozone exposure can significantly influence the optoelectronic properties of single layer MoS2, providing important implications on the application of MoS2 and other two-dimensional materials into optoelectronic devices.

Characterization of Covalently Bound Anti-Human Immunoglobulins on Self-Assembled Monolayer Modified Gold Electrodes.

Bioconjugated gold surfaces constitute interesting platforms for biosensing applications. The immobilization of antibodies such as anti-immunoglobulin G and M (anti-IgG and anti-IgM) on gold electrodes via self-assembled monolayers (SAMs) is here studied as a model system for further immunoassays development. The biolayer is characterized by means of X-ray photoelectron spectroscopy (XPS), atomic force microscopy (AFM), a dedicated thin-film transistor (TFT)-based platform and electrochemical surface plasmon resonance (EC-SPR). XPS analysis confirms the presence of all the chemical species involved in the fabrication process as well as the covalent attachment of the antibodies with high reproducibility. Visualization of the biolayer topography by AFM shows nanostructures with a thickness consistent with the actual size of the protein, which is also verified by SPR measurements. EC-SPR allows taking advantage of complementary electrochemical and optical signals during the functionalization steps. Moreover, the functionalization of gold leads to a change in the work function, which is demonstrated in an electrolyte gated thin-film transistor configuration. Such configuration enables also to evaluate the electrostatic changes occurring on the gate that are connected with the threshold voltage shifts. The data support that functional biomodified gold surfaces can be reproducibly prepared, which is a prerequisite for further biosensor development.

Improvement in Sensing Responses to Ammonia Gas for Gas Sensors With Separately Designed Sensing Element Using ALD-Grown ZnO Nanoparticles and Read-Out Element of Top-Gate In-Ga-Zn-O Thin-Film Transistor

Ammonia (NH3) gas sensors with unique oxide semiconductor thin-film transistor (TFT) configuration using ZnO nanoparticles (NPs) as gas-sensing element were fabricated and their gas-sensing responses were evaluated. The ZnO NPs composing the sensing elements were synthesized using atomic layer deposition (ALD). The optimum ALD conditions for the particle-like island-growth of ZnO were established by systematically investigating the ALD temperature and cycle conditions from 140 °C to 160 °C and from 5 to 30, respectively. Controlled devices of the sensor TFTs were prepared with different ALD conditions, in which sensing and read-out elements were designed to be physically separated. This unique device configuration provided us both benefits of improvement in gas-sensing property and stability of the device characteristics. The device showed instant gas responses as well as stable device behaviors at different operating temperature even with repeated gas measurements. Sufficiently good response to NH3 were obtained at 150 °C, which was significantly lower than the operating temperature of previously reported NH3 gas sensors. Based on the results the combination of novel TFT configuration and ALD-prepared ZnO NPs could be an effective method for the improvement in device characteristics of the gas sensors.

Fully Printed and Encapsulated SWCNT-Based Thin Film Transistors via a Combination of R2R Gravure and Inkjet Printing.

Fully printed thin film transistors (TFT) based on poly(9,9-di-n-dodecylfluorene) (PFDD) wrapped semiconducting single walled carbon nanotube (SWCNT) channels are fabricated by a practical route that combines roll-to-roll (R2R) gravure and ink jet printing. SWCNT network density is easily controlled via ink formulation (concentration and polymer:CNT ratio) and jetting conditions (droplet size, drop spacing, and number of printed layers). Optimum inkjet printing conditions are established on Si/SiO2 in which an ink consisting of 6:1 PFDD:SWCNT ratio with 50 mg L-1 SWCNT concentration printed at a drop spacing of 20 μm results in TFTs with mobilities of ∼25 cm2 V-1 s-1 and on-/off-current ratios > 105. These conditions yield excellent network uniformity and are used in a fully additive process to fabricate fully printed TFTs on PET substrates with mobility values > 5 cm2 V-1 s-1 (R2R printed gate electrode and dielectric; inkjet printed channel and source/drain electrodes). An inkjet printed encapsulation layer completes the TFT process (fabricated in bottom gate, top contact TFT configuration) and provides mobilities > 1 cm2 V-1 s-1 with good operational stability, based on the performance of an inverter circuit. An array of 20 TFTs shows that most have less than 10% variability in terms of threshold voltage, transconductance, on-current, and subthreshold swing.

Gate controllable resistive random access memory devices using reduced graphene oxide

The biggest challenge in the resistive random access memory (ReRAM) technology is that the basic operational parameters, such as the set and reset voltages, the current on-off ratios (hence the power), and their operational speeds, strongly depend on the active and electrode materials and their processing methods. Therefore, for its actual technological implementations, the unification of the operational parameters of the ReRAM devices appears to be a difficult task. In this letter, we show that by fabricating a resistive memory device in a thin film transistor configuration and thus applying an external gate bias, we can control the switching voltage very accurately. Taking partially reduced graphene oxide, the gate controllable switching is demonstrated, and the possible mechanisms are discussed.

Control of Grain Boundary Depletion Layer and Capacitance in ZnO Thin Film by a Gate with Electric Double Layer Dielectric

We report a comprehensive investigation of the impedance spectroscopy of nanostructured ZnO films with different morphologies used as channels in Thin Film Transistor configuration with a gate of Electric Double Layer dielectric. The different morphologies (achieved by growth on different types of substrates) range from films with grains of random orientations (grown on Si/SiO2) to films with nanocrystallites with strong texturing (grown on R-Sapphire and Kapton). The polymer electrolyte gate dielectric used enables a large carrier density at the ZnO interface in excess of 1013/cm2 even at a gate bias of 1 V. It has been shown that even with a moderate gate bias (Vg) of +3 V, the complex impedance can be severely suppressed, and the frequency characteristics of the impedance curves can be changed. Application of a negative gate bias similarly enhances the complex impedance. The observed data were explained as arising from control of the grain boundary depletion layer and the associated grain boundary capacitance (CGB) as well as the grain boundary potential barrier (φGB) by the field induced large charge density. We show that CGB can vary from a small value (large depletion width) when a negative Vg is applied to a large value (small depletion width) when the large majority charge density is induced by a positive gate bias.

High performance tetrathienoacene-DDP based polymer thin-film transistors using a photo-patternable epoxy gate insulating layer

High performance organic thin-film transistors (OTFTs) are fabricated on an epoxy based photo-patternable organic gate insulating layer (p-OGI) using a top contact thin-film transistor configuration. This negative tone p-OGI material is composed of an epoxy type polymer resin, a polymeric epoxy cross-linker, and a sulfonium photoacid generator (PAG). Features from p-OGI can be precisely patterned down to ∼3μm via i-line photolithography. In order to evaluate the potential of this epoxy type resin as a gate insulator, we evaluated the dielectric properties of the p-OGI and its gate insulating performance upon fabricating solution processed OTFTs using an organic semiconductor (OSC), namely tetrathienoacene-DPP copolymer (PTDPPTFT4). Results show that the PTDPPTFT4 based OTFTs with this p-OGI exhibit field-effect mobilities up to 1cm2V−1s−1, indicating the potential of high performance solution processed OTFT based on an epoxy based p-OGI/OSC system.

Achieving time-of-flight mobilities for amorphous organic semiconductors in a thin film transistor configuration

We observe bulk-like hole transport in amorphous organic semiconductors in a thin film transistor (TFT) configuration. Five different organic hole transporters (HTs) commonly used in organic light-emitting diodes are investigated. When these HTs are deposited on SiO2 gate dielectric layer, the TFT mobilities are 1–2 orders of magnitude smaller than those obtained from bulk films (3–8μm) using time-of-flight (TOF) technique. The reduction of hole mobilities can be attributed to the interactions between the organic HTs and the polar SiO bonds on the gate dielectric layer. Detailed temperature dependence studies, employing the Gaussian disorder model, indicate that the SiO2 gate dielectric contributes between 60 and 90meV of energetic disorder in the charge hopping manifold. Besides SiO2 gate dielectric, similar effects can also be observed for other polar insulators including polymeric PMMA and BCB, or HMDS-modified SiO2. However, when a common non-polar polymer, polystyrene (PS), is employed as the dielectric layer, the dipolar energetic disorder becomes negligible. Holes effectively experience bulk-like transport on the PS gate dielectric surface. TFT mobilities extracted from all five organic HTs are in excellent agreements with TOF mobilities. The present study should have broad applications in the transport characterization of amorphous organic semiconductors.

A framework for assessing amorphous oxide semiconductor thin‐film transistor passivation

AbstractAmorphous oxide semiconductor thin‐film transistors (TFTs) are moving towards commercialization for a variety of display applications. Invariably, display applications require a bottom‐gate TFT configuration in which passivation of the top channel layer surface is required. The objective of this work is to propose a conceptual model framework for assessing TFT passivation schemes, within the context of amorphous oxide semiconductor electronics. This model involves first estimating the energy of the charge neutrality levels (CNLs) for the channel and passivation layers. Then, an energy band diagram is drawn to establish the relative position of these CNLs prior to their establishment of intimate contact. A situation in which the passivation layer CNL is below that of the channel layer CNL is considered undesirable because interface state electronic transfer from the channel to the passivation layer leads to formation of an accumulation layer at this interface. Although the opposite case in which the passivation layer CNL is above that of the channel layer CNL is more desirable, the ideal situation would be when both CNLs align because no interface state electronic transfer would occur. This framework is then employed in a discussion of the passivation of indium gallium zinc oxide and zinc tin oxide bottom‐gate TFTs.

Complementary integrated circuits on plastic foil using inkjet printed n- and p-type organic semiconductors: Fabrication, characterization, and circuit analysis

Complementary thin-film transistor circuits composed of 6,13-bis(triisopropyl-silylethynyl) pentacene (TIPS–PEN) and a rylene carboxylic diimide derivative for p- and n-channel thin-film transistors (TFTs) were fabricated on flexible foils. The so-called staggered TFT configuration is used, meaning that the semiconductors layers are deposited last. The work-function of the injecting gold electrodes were modified using several self-assembled monolayers (SAMs). For optimized contacts the mobility of the n- and p-channel TFTs was 0.5cm2/Vs and 0.2cm2/Vs, respectively. Strongly degraded performance is obtained when the n-channel material was printed on contacts optimized for the p-channel TFT, and vice versa. This illustrates that for CMOS circuits we need careful work-function engineering to allow proper injection for both electrons and holes. We show for the first time that by using a bimolecular mixture for the SAM we can systematically vary the work function, and demonstrate how this affects the performance of discrete n-type and p-type transistors, as well as CMOS inverters and ring oscillators. Under optimal processing conditions we realized complementary 19-stage ring oscillators with 10μs stage delay operating at 20V.

Employ Present Five Masks Amorphous Silicon Thin-Film Transistor Design and Process Flow to Realize 5-in. InGaZnO Active-Matrix Liquid Crystal Display with Improved Stress Stability

The present five masks bottom gate and staggered amorphous silicon (a-Si) thin-film transistor (TFT) process flow is not suitable for indium–gallium–zinc-oxide (IGZO) TFT because of its vulnerability to post etching process during the source/drain pattern. Bottom gate and coplanar IGZO TFTs were made feasible through the reverse of second (channel layer) and third (source/drain electrodes) masks process flow to avoid etching damage problem. Besides, the post IGZO nitrous oxygen (N2O) plasma treatment was employed to improve the stress instability. On the basis of secondary ion mass spectrometry (SIMS) and X-ray spectroscopy (XPS) results, it is believed that the post N2O plasma treatment passivates the interface states and converts the inhomogeneous and low quality IGZO to the homogeneous and high quality IGZO. In the end, a 5-in. IGZO active-matrix liquid crystal display was demonstrated via five masks bottom gate and coplanar TFT configuration.

Transparent dual-gate InGaZnO thin film transistors: OR gate operation

Transparent dual-gate (DG) InGaZnO4 thin film transistors for OR logic operation were fabricated on a glass substrate. A 100-nm-thick SiO2 layer used as both top and bottom gate dielectrics was deposited by plasma enhance chemical vapor deposition at 200°C. Compared to bottom gate, top gate thin film transistors (TFTs) exhibited better device performance with higher saturation mobility, drain current on-to-off ratio, lower threshold voltage, and subthreshold gate-voltage swing. This improved performance was mainly attributed to low process-induced damage or low parasitic capacitance between gate and source/drain and low parasitic resistance between channel and source/drain in top-contact TFT configuration (coplanar type). DG-mode TFTs showed saturation mobility of ∼16.9cm2V−1s−1, drain current on-to-off ratio of ∼1×106, subthreshold gate-voltage swing of ∼0.33Vdecade−1, and threshold voltage of ∼1.25V. The results demonstrate that DG InGaZnO4 TFTs are effective in improving the device performance because the channel layer is modulated independently by a top or, bottom gate signal and are well suited for OR gate operation.

Thin Film Transistors Based on Alkylphenyl Quaterthiophenes: Structure and Electrical Transport Properties

Thin films based on the akylphenyl-substituted quaterthiophenes 5,5‘ ‘‘-bis(4-methylphenyl)-2,2‘:5‘,2‘ ‘:5‘ ‘,2‘ ‘‘-quaterthiophene (1), 5,5‘ ‘‘-bis(4-n-propylphenyl)-2,2‘:5‘,2‘ ‘:5‘ ‘,2‘ ‘‘-quaterthiophene (2), and 5,5‘ ‘‘-bis(4-hexylphenyl)-2,2‘:5‘,2‘ ‘:5‘ ‘,2‘ ‘‘-quaterthiophene (3) were grown by vacuum deposition on thermally grown SiO2 substrates and characterized in a thin film transistor (TFT) configuration. Atomic force microscopy and specular (θ−2θ) X-ray diffraction (XRD) revealed films with small, crystalline grains, in which the oligothiophenes were oriented “end-on” with respect to the SiO2 substrate. Interplanar spacing increased (1 = 28.0 A, 2 = 29.5 A, 3 = 37.7 A), consistent with increasing alkyl tail length. Grazing incidence X-ray diffraction (GIXD) of the films (ca. 350 A thick) revealed nearly equivalent in-plane unit-cell areas (1 = 44.1 A2, 2 = 44.4 A2, 3 = 43.8 A2). The films functioned as p-channel semiconductors in a TFT configuration, exhibiting nearly equivalent hole mobilities...

Optical evidence of Stark effect in single-walled carbon nanotube transistors

The effect of an externally applied electric field in single-walled carbon nanotubes was studied using a thin-film transistor configuration. Under the electric field, the optical spectra displayed redshifts and broadening. These phenomena present evidence of the Stark effect in single-walled carbon nanotubes. The finding of the Stark effect suggests the potential use of carbon nanotubes in electro-optic devices for optical communication.

Simplified electrode arrangement for TFT-matrix liquid crystal displays

The standard thin-film transistor configuration, used in TFT-matrix addressing of complex liquid crystal displays, has an inherent design fault in that there is a metal-metal crossover associated with each transistor. This arrangement makes shorts and open circuits more likely with increase in panel size. In this paper, a modification is proposed that overcomes this problem.