Thin Equivalent Oxide Thickness Research Articles

Reduction of Slow Trap Density in Al2O3/GeO x N y /n-Ge MOS Interfaces by PPN-PPO Process

The realization of high- ${k}$ /IL/Ge MOS interfaces with thin equivalent oxide thickness (EOT), low interface state density ( $\text{D}_{{\text {it}}}$ ), and high reliability is strongly needed for realizing Ge metal–oxide–semiconductor field-effect transistors (MOSFETs). In this article, we examine the properties of the slow trap areal density ( $\Delta \text{N}_{{\text {st}}}$ ) and $\text{D}_{{\text {it}}}$ in Al2O3/GeOxN y /n-Ge MOS interfaces formed by atomic layer deposition (ALD) Al2O3 films with plasma post nitridation (PPN) and plasma post oxidation (PPO). Here, the process order and process time of PPN and PPO are systematically changed to optimize the Al2O3/GeO x N y /n-Ge MOS interface properties. It is found that N atoms induced into GeO x can suppress slow electron trapping. An Al2O3/n-Ge structure with 1-min PPN before PPO can reduce $\Delta \text{N}_{{\text {st}}}$ by 34% in a weak electric field, whereas PPN after PPO increase $\Delta \text{N}_{{\text {st}}}$ . Also, the sufficient time PPO process after PPN can decrease $\text{D}_{{\text {it}}}$ to a similar level as that at the Al2O3/GeO x /n-Ge MOS interfaces. The temperature dependence of electron trapping properties is also experimentally evaluated. The slow electron trapping is expected to be more suppressed for the GeO x N y interfaces at real device operation temperature.

Slow Trap Properties and Generation in Al2O3/GeOx/Ge MOS Interfaces Formed by Plasma Oxidation Process

Understanding of slow traps near Ge MOS interfaces and reduction of the slow trap density are one of the most crucial issues for realizing Ge CMOS devices, in addition to the thin equivalent oxide thickness (EOT) and the low density of fast interface states (Dit). In this study, we examine the slow trap density and location in the Al2O3/GeOx/Ge interfaces fabricated by plasma oxidation. The slow trap density of Al2O3/GeOx/Ge MOS interfaces formed by pre-plasma oxidation (pre-PO) is compared with that of the MOS interfaces formed by post-plasma oxidation (post-PO). Also, the dependence of the slow trap density on the GeOx and Al2O3 thickness is systematically evaluated for the Al2O3/GeOx/Ge MOS interfaces formed by pre-PO. It is found that additional slow traps for electrons can be generated during the post-PO process near the conduction band side of Ge. It is also found that the main slow traps for electrons and holes in the Al2O3/GeOx/Ge MOS interfaces can locate near the GeOx/Ge interfaces and the Al2O3...

Impact of Atomic Layer Deposition High k Films on Slow Trap Density in Ge MOS Interfaces With GeOx Interfacial Layers Formed by Plasma Pre-Oxidation

For realizing of Ge complementary metal–oxide–semiconductor with a Ge gate stack with thin equivalent oxide thickness, low interface state density ( $\text{D}_{\mathrm{ it}}$ ) and high reliability. In this paper, we examine the slow trap behaviors in the ALD high-k materials including Al2O3, Y2O3, HfO2, and La2O3 on GeOx/Ge interfaces, where the GeOx interfacial layers are formed by plasma pre-oxidation. The C–V curves, $\text{D}_{\mathrm{ it}}$ and slow trap density of the high-k/GeOx/n- and p- Ge MOS capacitors are evaluated and compared. The Ge 3d spectra in X-ray photoemission spectroscopy are also compared among the Al2O3, Y2O3, HfO2, and La2O3 on GeOx/Ge structures. It is found that Al2O3 provides the lowest slow trap density for both electrons and holes in comparison with Y2O3, HfO2, and La2O3 high-k films, while similar $\text{D}_{\mathrm{ it}}$ values are observed among the MOS interfaces with Al2O3, Y2O3, HfO2, and La2O3. The additional slow traps in the MOS capacitors with Y2O3, HfO2, and La2O3 are attributable to any defects in the high-k films and/or the interfaces with GeOx.

Reduction of slow trap density of Al2O3/GeOx/n-Ge MOS interfaces by inserting ultrathin Y2O3 interfacial layers

The realization of Ge gate stacks with thin equivalent oxide thickness (EOT), low interface state density (Dit) and small hysteresis is a crucial issue for Ge CMOS. In this study, we propose a new Al2O3/ultrathin Y2O3/GeOx/Ge MOS interface, formed by atomic layer deposition (ALD) Al2O3/Y2O3/Ge MOS structures with plasma post oxidation (PPO) for introducing Y into GeOx and mitigating slow trapping. Both Dit and slow trap density (ΔNst) in the Al2O3/Y2O3/Ge system are reduced by PPO. A 1.5-nm-thick Al2O3/0.63-nm-thick Y2O3/GeOx/Ge interface can provide a 36% lower amount of ΔNst at Eox of 3×106V/cm with maintaining similar levels of Dit than the control Al2O3/GeOx/Ge interface. It is found that the optimum Y2O3 thickness exists for minimizing ΔNst.

Properties of slow traps of ALD Al2O3/GeOx/Ge nMOSFETs with plasma post oxidation

The realization of Ge gate stacks with a small amount of slow trap density as well as thin equivalent oxide thickness and low interface state density (Dit) is a crucial issue for Ge CMOS. In this study, we examine the properties of slow traps, particularly the location of slow traps, of Al2O3/GeOx/n-Ge and HfO2/Al2O3/GeOx/n-Ge MOS interfaces with changing the process and structural parameters, formed by atomic layer deposition (ALD) of Al2O3 and HfO2/Al2O3 combined with plasma post oxidation. It is found that the slow traps can locate in the GeOx interfacial layer, not in the ALD Al2O3 layer. Furthermore, we study the time dependence of channel currents in the Ge n-MOSFETs with 5-nm-thick Al2O3/GeOx/Ge gate stacks, with changing the thickness of GeOx, in order to further clarify the position of slow traps. The time dependence of the current drift and the effective time constant of slow traps do not change among the MOSFETs with the different thickness GeOx, demonstrating that the slow traps mainly exist near the interfaces between Ge and GeOx.

Improved n-channel Ge gate stack performance using HfAlO high-k dielectric for various Al concentrations

We demonstrate improved Ge n-channel gate stack performance versus HfO2 using HfAlO high-k dielectric for a wide (1.5–33%) range of Al% and post-high-k-deposition annealing (PDA) at 400 °C. Addition of Al to HfO2 is shown to mitigate degradation of the GeO2/Ge interface during PDA. HfAlO stacks with an equivalent oxide thickness (EOT) of 8 nm and large Al% exhibit improved transistor mobility (1.8 times higher) and midgap Dit (2 times lower), whereas thin (1.9 nm) EOT HfAlO stacks show reduced gate leakage Jg (by 10 times) and Dit (by 1.5 times) and 1.6 times higher mobility for Al% as low as 1.5% at matched EOT.

Study on void reduction in direct wafer bonding using Al2O3/HfO2 bonding interface for high-performance Si high-k MOS optical modulators

We have investigated the direct wafer bonding (DWB) method with a thin bonding dielectric interface to fabricate Si high-k MOS optical modulators with a thin equivalent oxide thickness (EOT). To suppress void generation on the bonded wafer during high-temperature annealing, we examined the high-k dielectric bonding interfacial layers, such as Al2O3 and HfO2. We found that the Al2O3/HfO2 bilayer enables void-less wafer bonding in conjunction with pre-bonding annealing at 700 °C. By using the 0.5-nm Al2O3/2.0-nm HfO2 bonding interface, the density of voids is reduced by three orders of magnitude as compared with that in the case of using the Al2O3 bonding interface. We achieved a density of voids of approximately 2 × 10−3 cm−2 even when the bonded wafer is annealed at 700 °C. By thermal desorption spectroscopy (TDS), we found that degassing from the bonding interface is successfully suppressed by the introduction of the HfO2 layer and the pre-bonding annealing at 700 °C, which are considered to suppress void generation. Wafer bonding with thin Al2O3/HfO2 high-k bonding interface is promising for Si high-k MOS optical modulators.

Impact of Postdeposition Annealing Ambient on the Mobility of Ge nMOSFETs With 1-nm EOT Al2O3/GeOx/Ge Gate-Stacks

The impact of postdeposition annealing (PDA) ambient on electrical properties of thin equivalent oxide thickness (EOT) Al2O3/GeO x /Ge gate-stacks is investigated. It is found that the surface states inside the conduction band of Ge are significantly suppressed by 40% through PDA with atomic deuterium ambient. As a result, enhancement of the effective mobility in the Ge nMOSFETs is realized in high normal field region. The electron mobility of 396 cm2/Vs is achieved at $N_{s}$ of $10^{13}$ cm $^{-2}$ with small EOT of $\sim 1$ nm, which is similar to the highest mobility reported so far at such small EOT range.

Fabrication and MOS interface properties of ALD AlYO3/GeOx/Ge gate stacks with plasma post oxidation

The realization of Ge gate stacks with thin equivalent oxide thickness (EOT), low interface state density (Dit) and small hysteresis is a crucial issue for Ge CMOS. In this study, we propose a new AlYO3/GeOx/Ge MOS interface, formed by atomic layer deposition (ALD) AlYO3/Ge MOS structures with plasma post oxidation (PPO). Reduction in Dit by PPO is found for AlYO3/Ge system. A 1.5-nm-thick AlYO3/GeOx/Ge interface with 1.25-nm EOT can provide a lower amount of the slow trap density, particularly in the valence band side of Ge, than the control Al2O3/GeOx/Ge interface and the Y2O3/GeOx/Ge interface. Deposition of any high-k films on the AlYO3/GeOx/Ge structure leads to the increase in the slow trap density to the same level, suggesting the influence of any traps at the interface between the high-k films and AlYO3.

Electrical characteristics of ALD La2O3 capping layers using different lanthanum precursors in MOS devices with ALD HfO2, HfSiOx, and HfSiON gate dielectrics

We have investigated the electrical characteristics – flat band voltage (VFB) shift, equivalent oxide thickness (EOT) scaling and charge trapping – of atomic layer deposition (ALD) La2O3 capped high-k gate dielectrics (HfO2, HfSiOx, and HfSiON) in the metal-oxide-semiconductor (MOS) device structure, where two different lanthanum precursors – ① lanthanum formamidinate, La(fAMD)3, and ② lanthanum betadiketonate, La(thd)3, – were used for ALD capping layer. Regardless of precursors, La2O3 capping layer on the ALD high-k films leads to negative VFB shift and thinner EOT as increasing capping thickness. However, more shift and further EOT scaling are observed with La2O3 thin film using La(fAMD)3. In addition, La2O3 capping layer using La(fAMD)3 precursor shows lower interface state density (Dit) and stronger immunity against charge trapping than La2O3 capping layer with La(thd)3 precursor. Similar trends are attained with Si containing HfO2 – HfSiOx and HfSiON, but amount of VFB shift and EOT reduction is smaller than that of HfO2-based device, resulting from suppressed La-diffusion due to stronger Si–O bonds as well as nitrogen blocking in the dielectrics.

Analysis of Single-Trap-Induced Random Telegraph Noise and its Interaction With Work Function Variation for Tunnel FET

This paper analyzes the impacts of a single acceptor-type and donor-type interface trap induced random telegraph noise (RTN) on tunnel FET (TFET) devices and its interaction with work function variation (WFV) using atomistic 3-D TCAD simulations. Significant RTN amplitude (ΔID/ID) is observed for a single acceptor trap near the tunneling junction, whereas a donor trap is found to cause more severe impact over a broader region across the channel region. In addition, several device design parameters that can be used to improve TFET subthreshold characteristics (thinner equivalent oxide thickness or longer Leff) are found to increase the susceptibility to RTN. Our results indicate that under WFV, TFET exhibits weaker correlation between ION and IOFF than that in the conventional MOSFET counterpart. In the presence of WFV, the RTN amplitude can be enhanced or reduced depending on the type of the trap and the composition/orientation of metal-gate grain.

Effects of composition and thickness of TiN metal gate on the equivalent oxide thickness and flat-band voltage in metal oxide semiconductor devices

VFB and EOT are modulated by varying composition and thickness of TiN metal gate.Metallic TiN shows lower VFB while N-rich TiN exhibits higher VFB.Thicker TiN shows higher VFB values.Metallic and thinner TiN is compatible with nMOS while N-rich and thicker TiN is for good pMOS. We investigated the effects of gas flow rates during sputtering and thickness of TiN metal gate on the equivalent oxide thickness (EOT) and flat band voltage (VFB) in the gate-first (GF) processed metal oxide semiconductor (MOS) devices with HfO2 and HfSiON-based gate dielectrics. For both HfO2 and HfiSON devices, more metallic TiN causes thinner EOT with lower VFB while higher VFB is observed along with thicker EOT for nitrogen-rich TiN case. Also, thicker TiN induces more positive VFB shift. However, for HfSiON, amount of VFB shift and EOT reduction is smaller than those of HfO2-based device, resulting from stronger immunity of Hf-Si bonding against oxygen vacancy generation during thermal process.

Reduction of silicon dioxide interfacial layer to 4.6Å EOT by Al remote scavenging in high-κ/metal gate stacks on Si

• Al diffusion into gate stack leads to EOT reduction. • Process reduces the EOT at low temperature (400 °C) and is suitable for replacement gate processes. • Extensive interface studies support the electrical measurements. • Reactions are in agreement with thermodynamical considerations. The continued device scaling demands the reduction of the equivalent oxide thickness (EOT) below 1 nm. For HfO 2 -based gate stacks, the interfacial SiO 2 limits the EOT scaling. A low EOT can only be achieved if the interfacial layer (IL) is reduced to its physical limit of ∼4 Å. Such thin EOT are achievable if redox reactions within the gate stack are employed in order to reduce SiO 2 . This study reports on the use of an Al layer in combination with a TiN metal electrode to reduce the IL and achieve lowest EOT values. The lowest EOT achieved was 4.6 Å. However, the scavenging process was found to strongly depend on the thermal budget after Al deposition. The presented process adapts a standard metal-inserted poly-Si flow (MIPS) prior to Al deposition, but may also be an option to control IL regrowth.

(Invited) MOS Interface Control of High Mobility Channel Materials for Realizing Ultrathin EOT Gate Stacks

One of the most critical issues for Ge/III-V MOSFETs is gate insulator formation. In this paper, we focus on viable Ge/III-V MOS gate stack technologies realizing the requirements of MOS interface quality and thin equivalent oxide thickness (EOT). these requirements. As for Ge gate stacks, we present a ultrathin EOT Al2O3/GeOx/Ge gate stack fabricated by a plasma post oxidation method and pMOSFETs using this gate stack. (100) Ge pMOSFETs using GeOx/Ge MOS interfaces is demonstrated with EOT down to 0.98 nm and high hole peak mobility of 401 cm2/Vs. As for InGaAs gate stacks, we show the impact of Al2O3 inter-layers on interface properties of HfO2/InGaAs MOS interfaces. The 1-nm-thick capacitance equivalent thickness (CET) in the HfO2/Al2O3/InGaAs MOS capacitors is realized with good interface properties and low gate leakage of 2.4e-2 A/cm2.

InGaAs/InP Tunnel FETs With a Subthreshold Swing of 93 mV/dec and $I_{\rm ON}/I_{\rm OFF}$ Ratio Near $\hbox{10}^{6}$

Vertical n-channel tunnel field-effect transistors (TFETs) with tunneling normal to the gate based on an n+ In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">∞=0.53-&gt;;1</sub> GaAs/p <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> InP heterojunction have been demonstrated to exhibit simultaneously a high I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> ratio of 6 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">5</sup> , a minimum subthreshold swing (SS) of 93 mV/dec, and an on-current of 20 μA/μm at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> = 0.5 V and a gate swing of 1.75 V at 300 K, a record TFET performance. The significant improvement in device performance is ascribed to the adoption of a thin equivalent oxide thickness (EOT) of ~1.3 nm for improved electrostatics and the use of plasma-enhanced chemical vapor deposition SiN <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">∞</sub> mesa passivation to preserve the integrity of the thin exposed semiconductor layers.

Improved Characteristics of HKMG MOS Capacitor with Different Ultrathin Interface Layers

In order to improve the HKMG interface states density and electrical characteristics, four different interface layers have been studied in this paper. They are 7Aå thickness of SiO2 produced by rapid thermal annealing process at 1000°C, 4Aå thickness of SiO2 produced by rapid thermal annealing process at 700°C, 10Aå thickness of silicon nitride produced by LPCVD process at 620°C, and 20Aå thickness of SiO2 produced by traditional horizontal furnace process at 830°C. It was found that there were two samples, the interface layers of 7Aå SiO2 and 10Aå silicon nitride, having excellent interface state density (1.5~1.7×1011cm-2ev-1) and gate leakage (3.1~3.5×10-7A). Considering the thinner equivalent oxide thickness (Eot), we choose 10Aå silicon nitride as the best one

Gate-First Metal-Gate/High-$k$ n-MOSFETs With Deep Sub-nm Equivalent Oxide Thickness (0.58 nm) Fabricated With Sulfur-Implanted Schottky Source/Drain Using a Low-Temperature Process

Gate-first high- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> /metal-gate n-MOSFETs with a deep subnanometer (sub-nm) equivalent oxide thickness (EOT) of 0.58 nm were successfully fabricated with Schottky source/drain contacts using a low-temperature process. The key to achieving such a thin EOT is the use of a low-temperature process for the NiSi Schottky source/drain formation. A sulfur implantation technique was used to overcome the Schottky barrier height between Si and NiSi, which is the main problem in NiSi Schottky source/drain fabrication. The advantage of Schottky source/drain MOSFETs over conventional source/drain MOSFETs was successfully demonstrated.

Study of nitrogen impact on VFB–EOT roll-off by varying interfacial SiO 2 thickness

Flat band voltage ( V FB) roll-off in long channel devices at thin equivalent oxide thickness (EOT) is studied on SiO 2/nitrided-HfSiO stacks. V FB increases when SiO 2 interfacial layer thickness decreases, and charges pumping (CP) frequency sweep analysis shows higher trap density near Si/SiO 2 interface. Based on this observation, an atomic diffusion model is introduced. Higher concentration of nitrogen atom in the HfSiO(N) layer diffuses to the Si/SiO 2 interface through the SiO 2 layer in thinner SiO 2 device, and accumulates near Si/SiO 2 interface which can introduce higher density of interfacial traps. Lifetime extracted from negative bias temperature instability (NBTI), and mobility are also degraded in thinner SiO 2 devices due to the higher interfacial trap density. The V FB roll-off can be improved by lowering nitrogen concentration in the HfSiO(N) layer from optimizing plasma nitridation pressure, decreasing post deposition anneal temperature, or using defect absorbing layer on the high-k oxide.

High-Performance Poly-Si Nanowire Thin-Film Transistors Using the $\hbox{HfO}_{2}$ Gate Dielectric

High-performance polycrystalline-silicon (poly-Si) nanowire (NW) thin-film transistors (TFTs) using hafnium dioxide as gate dielectric is successfully fabricated for the first time. The excellent short-channel characteristics are attributed to the high- gate dielectric, ultrathin poly-Si NW channel thickness, and omega-shaped gate structure. The record high driving capability of 549 results from the ultrashort gate length , thin equivalent oxide thickness, and Ni silicide metal source/drain. This letter reveals the opportunity of high-performance poly-Si TFT circuits for system-on-panel and 3-D integrated circuit (3-D IC) applications.

Performance Evaluation of GaAs–GaP Core–Shell-Nanowire Field-Effect Transistors

We evaluate the performance of GaAs-GaP core-shell (C-S)-nanowire (NW) field-effect transistors by employing a semiclassical ballistic transport model. The valence-band structures of GaAs-GaP C-S NWs are calculated by using a kldrp method including the strain effect. The calculations show that the strain causes substantial band warping and pushes valence subbands to move up. We demonstrate that the on current can be enhanced with the strength of strain induced in the core, but an extremely thin equivalent oxide thickness may suppress the effect of the strain-induced current improvement. The achieved results can provide a design guide for optimizing device performance.