Thin Chemical Oxide Research Articles

Silicon-Rich Silicon Carbide Hole-Selective Rear Contacts for Crystalline-Silicon-Based Solar Cells.

The use of passivating contacts compatible with typical homojunction thermal processes is one of the most promising approaches to realizing high-efficiency silicon solar cells. In this work, we investigate an alternative rear-passivating contact targeting facile implementation to industrial p-type solar cells. The contact structure consists of a chemically grown thin silicon oxide layer, which is capped with a boron-doped silicon-rich silicon carbide [SiCx(p)] layer and then annealed at 800-900 °C. Transmission electron microscopy reveals that the thin chemical oxide layer disappears upon thermal annealing up to 900 °C, leading to degraded surface passivation. We interpret this in terms of a chemical reaction between carbon atoms in the SiCx(p) layer and the adjacent chemical oxide layer. To prevent this reaction, an intrinsic silicon interlayer was introduced between the chemical oxide and the SiCx(p) layer. We show that this intrinsic silicon interlayer is beneficial for surface passivation. Optimized passivation is obtained with a 10-nm-thick intrinsic silicon interlayer, yielding an emitter saturation current density of 17 fA cm-2 on p-type wafers, which translates into an implied open-circuit voltage of 708 mV. The potential of the developed contact at the rear side is further investigated by realizing a proof-of-concept hybrid solar cell, featuring a heterojunction front-side contact made of intrinsic amorphous silicon and phosphorus-doped amorphous silicon. Even though the presented cells are limited by front-side reflection and front-side parasitic absorption, the obtained cell with a Voc of 694.7 mV, a FF of 79.1%, and an efficiency of 20.44% demonstrates the potential of the p+/p-wafer full-side-passivated rear-side scheme shown here.

Charge storage characteristics of nonvolatile memories with chemically-synthesized and vacuum-deposited gold nanoparticles

Carrier injection and charge loss characteristics of nonvolatile memories with chemically-synthesized (CS) and vacuum-deposited (VD) gold nanoparticles (Au-NPs) have been investigated. Compared to CS counterparts, the memories with VD Au-NPs exhibit a higher dot density of 3.77 × 1011 cm−2, leading to a larger memory window. Further, the energy from valence-band edge to vacuum level (EVB_vac) of tunneling oxide for the samples with CS and VD Au-NPs is found to be 9.04 and 9.85 eV respectively. The small EVB_vac value of the memories with CS Au-NPs is resulted from the formation of a thin chemical oxide (SiOx) on thermally-grown SiO2 tunneling layer during the chemically synthesized process, contributing to a slow erasing behavior. Besides, the programming of the memories with VD Au-NPs is saturated at high gate bias, which has been well-explained by the electrons induced potential coupling between Au-NPs. Superior data retention property and high temperature dependence of charge loss are observed for the memories with CS Au-NPs, which can be ascribed to the thick tunneling oxide layer by the additional SiOx film.

(Invited) High Pressure Sputtering for High-K Dielectric Deposition. Is It Worth Trying

(Invited) High Pressure Sputtering for High-K Dielectric Deposition. Is It Worth Trying

High-quality spin-on glass-based oxide as a matrix for embedding HfO2 nanoparticles for metal-oxide-semiconductor capacitors

By using a low cost, simple, and reproducible spin-coating method, thin films of SOG (spin-on-glass)-based oxides with electrical characteristics resembling those of a dry thermal oxide have been obtained. The superior electrical characteristics of Metal-Oxide-Semiconductor (MOS) capacitors based on SOG-oxides come from both (1) reducing the organic content of the SOG solutions after dilution with deionized water and (2) passivation of the silicon surface by a thin chemical oxide. Fourier transform infrared spectroscopy analysis shows that the organic content in H2O-diluted SOG-oxides is reduced compared to undiluted SOG after N2 annealing. In addition, by chemically embedding HfO2 nanoparticles (np-HfO2) to these SOG-based oxides, an effective increase in the accumulation capacitance of MOS capacitors is observed and this is related to the increase in the final dielectric constant of the resulting oxide after annealing so that potential use of SOG as a glass matrix for embedding HfO2 nanoparticles and produce higher-k oxide materials is demonstrated.

The effects of treatment of Si(1 1 1) surfaces with NH 4F solution on Schottky diode parameters

A study on Al/p-Si(1 1 1) Schottky barrier diodes (SBDs) parameters with and without a thin chemical oxide layer on p-type Si has been performed. The oxide layer has been formed by a wet chemical oxidation in HNO 3 solution. In order to avoid native oxide formation on the sample surface, the silicon dangling bonds have been passivated with hydrogen atoms by dipping in a NH 4F solution. It is shown that these treatments give almost the same barrier height values. In addition, it has been found that the treatment of the sample back surface in NH 4F solution reduces the reverse current and the series resistance.

In situ transmission electron microscopy study of Ni silicide phases formed on (001) Si active lines

The formation of Ni silicides is studied by transmission electron microscopy during in situ heating experiments of 12 nm Ni layers on blanket silicon, or in patterned structures covered with a thin chemical oxide. It is shown that the first phase formed is the NiSi2 which grows epitaxially in pyramidal crystals. The formation of NiSi occurs quite abruptly around 400 °C when a monosilicide layer covers the disilicide grains and the silicon in between. The NiSi phase remains stable up to 800 °C, at which temperature the layer finally fully transforms to NiSi2. The monosilicide grains show different epitaxial relationships with the Si substrate. Ni2Si is never observed.

Growth of patterned thin epitaxial CoSi 2-films by a titanium oxide mediated epitaxy process

A new method for fabricating thin patterned CoSi 2 layers has been studied. The silicide layers were generated by a solid phase epitaxy process, in which Co and Ti were deposited on a thin chemical oxide on Si(100) substrates. Rapid thermal annealing (RTA) of this structure leads to the formation of epitaxial CoSi 2 with a capping layer on top. Two-step annealing in a forming ambient gas produces high quality epitaxial layers with a capping layer which can be easily removed by wet chemicals. A layer structure consisting of 30 nm SiO 2 and 300 nm Si 3N 4, which is patterned using conventional optical lithography and dry etching, induces a stress field into the underlying layers near the patterning edges. This leads to a formation of separated CoSi 2 layers during the silicide formation caused by the anisotropic diffusion of the atoms in the stress field. Such layers show nearly uniform gaps of approximately 100 nm in width.

A study on the oxidation kinetics of silicon in inductively coupled oxygen plasma

The oxidation kinetics of silicon in inductively coupled oxygen plasma (ICP) was studied at temperatures ranging from 350 to 450 °C. The oxide growth kinetics was described by a linear-parabolic growth law, with a rapid initial growth and a negative linear-rate constant. Under oxygen pressure of 10 mTorr, the initial oxide growth at 350 °C (thickness below 25 nm) was faster than at 400 °C. An analysis of transverse-optical mode frequencies and etch rates indicated that the density of the surface oxide was lower than that of the bulk oxide. The oxidation kinetics was explained qualitatively by assuming that the ICP oxide consisted of a surface layer with a larger diffusion coefficient and a bulk layer with a smaller diffusion coefficient. On the other hand, the ICP oxidation of silicon with a thin chemical oxide showed a positive linear-rate constant and no surface layer effect, supporting the fact that the oxide grown by the ICP oxidation has a low-density surface layer with a larger diffusion coefficient.

Palladium-promoted oxidation of Si at low temperatures

A palladium (Pd) layer deposited on the ultrathin silicon oxide-covered Si substrate promotes Si oxidation. Take-off angle dependent X-ray photoelectron spectroscopy (XPS) measurements and the capacitance-voltage measurements show that after the heat treatment of the 〈Pd/chemical oxide/Si(100)〉 specimens at 400°C in oxygen, the thickness of the oxide layer between the Pd layer and the Si substrate increases to 4-4.5 nm but no oxide is formed on the Pd surface. When the Pd layer is deposited on the hydrofluoric acid-etched Si surface, palladium silicide is formed, while no silicide is formed in cases where the Pd film is deposited on the thin chemical oxide covered-Si substrate. It is concluded that the diffusing and reaction species are oxygen atoms (or oxygen ions), initially formed at the Pd surface.

A new method for the growth of silicon oxide layers below 300°C by use of catalytic activity of platinum overlayers

A new method to grow silicon oxide layers at temperatures below 300°C is developed using catalytic activity of platinum. In this method, a ca. 1 nm-thick chemical oxide layer is formed on the Si surface and then a ca. 3 nm-thick platinum layer is deposited on it. The thin chemical oxide layer effectively prevents the silicide formation and the Si outdiffusion, and consequently, a silicon oxide layer grows between the Pt layer and the Si substrate, but not formed on the Pt surface. When the device with the (ca. 3 nm-Pt/ca. 1 nm-chemical oxide/Si(100)) structure is kept at room temperature in air for a week, the thickness of the oxide layer increases to ca. 2.6 nm. Measurements of X-ray photoelectron spectra under biases show that the interface state density for this device is lower than that for the (ca. 3 nm-Pt/ca. 3–3.5 nm-thermal oxide/n-Si(100)) devices. After heat-treatments of the oxide layer with the Pt overlayer at 300°C for 1 h in oxygen, the oxide thickness increases to ca. 4.6 nm.

Low temperature catalytic formation of Si-based metal–oxide–semiconductor structure

Si-based metal–oxide–semiconductor structure is formed at temperatures as low as 300 °C using the catalytic activity of the platinum (Pt) layer. X-ray photoelectron spectroscopy and transmission electron micrography measurements show that heat treatments of the ∼5 nm-Pt/∼1 nm-chemical oxide/Si(100)〉 devices at 300 °C increase the thickness of the oxide layer to 4–4.5 nm and the oxide layer is present between the Pt layer and the Si substrate, but not on the Pt surface. It is found that the thin chemical oxide layer effectively prevents the Pt diffusion and the silicide formation during the heat treatments. Heat treatments in dry- and wet-oxygen result in nearly the same oxide thickness. Oxygen atoms (or oxygen ions) produced at the Pt surface are suggested to be a diffusing species through the Pt and silicon oxide layers.

The interface between sipos and silicon

Semi-insulating polycrystalline silicon (SIPOS) is formed by introducing oxygen during the deposition of silicon. SIPOS is currently used as a passivation layer for high voltage devices. More recently, it has also been introduced as an emitter material for bipolar transistors. Electrical properties are expected to be influenced by many factors, some of which are: dopant type and concentration, the grain size and contiguity of the silicon crystals, and the microstructure of the SIPOS/Si interface. This contribution reports cross-section TEM results obtained from samples that have undergone different silicon wafer preparation prior to SIPOS deposition and different post-deposition rapid thermal anneal (RTA) treatments.One set of silicon wafers was dipped in buffered HF immediately prior to SIPOS deposition in order to remove any oxide. A thin chemical oxide ∼1 nm thick was intentionally left on the other set of wafers.