Thick Buffer Research Articles

(Digital Presentation) Fabrication of Thick SiGe／Ge Multiple Quantum Wells on Ge-on-Si and Their Optical Properties

Recently, silicon photonics has been attracting increased attention toward the realization of on-chip optical interconnection, which requires high-efficiency light-emitting devices to be integrated on Si substrates. Although Ge is an indirect-band-gap semiconductor like Si, it is expected that strong direct-transition luminescence can be obtained from tensile-strain induced Ge-on-Si. We have previously reported that highly efficient room temperature EL emission can be obtained from strained Ge-on-Si p-i-n diodes[1]. Further increase in luminescence intensity and control of emission wavelengths can be made possible by introducing a quantum well structure in the active layer. Although the fabrication of high-quality strained SiGe layers on Ge is essential for the fabrication of quantum well structures, critical thickness limits the total growth thickness and numbers of strained layers, which makes device applications difficult. We have succeeded in fabricating a strained SiGe layer that is much thicker than the critical thickness by using a patterning method, and this result is very promising for the fabrication of SiGe/Ge multi-quantum well structure[2]. It also makes it possible to increase the number of layers of MQW structure. In this work, we fabricate relatively thick strained SiGe/Ge MQW structures on Ge-on-Si by utilizing the patterning method, and evaluate their crystallinity and optical properties.In experiments, the crystal growth was carried out with solid source molecular beam epitaxy. The Ge-on-Si was fabricated using the so-called two-step method. 40 and 500 nm thick Ge layers were subsequently grown on a Si(100) or Si(111) substrate at 350 and 600℃, respectively, followed by annealing at 800℃ for 10 min. Subsequently we carried out the patterning of the Ge-on-Si(111) substrate by photolithography process. 50nm thick Ge buffer layer ware grown on a Ge-on-Si(100) or Ge-on-Si(111), 6nm thick Si0.1Ge0.9 barrier layer and 10nm thick Ge well layer ware grown with 10-20 cycles at 350℃.Laser microscopic measurements showed no clear roughness on the surface. X ray diffraction measurements show periodic peaks originated from the multi layers of SiGe/Ge, which indicates that the sample has high crystallinity and abrupt interface between the Ge and SiGe layers. TEM observation indicated that no defect was found inside the crystal in the MQW structure. Photoluminescence (PL) measurements were carried out at room temperature and a PL peak originated from the quantum-confinement in the SiGe/Ge MQW was obtained. This PL peak wavelength was also found to shift depending on the Ge concentration of the SiGe. PL intensity of the peak was increased compared with Ge-on-Si without the SiGe/Ge MQW overgrowth. From these results, it is demonstrated that high quality SiGe/Ge multiple quantum structures can be fabricated on Ge-on-Si by utilizing the patterning method and strong room temperature PL was obtained from the MQW, indicating that SiGe/Ge MQW is promising for the applications to light-emitting devices integrated on the Si platform.[1] K.Yamada et al. Appl. Phys. Express 14 045504(2021) [2] Y.Wagatsuma et al. Appl. Phys. Express 14 025502(2021) Figure 1

Hydrogen-Assisted Molecular Beam Epitaxy of SiGeSn

Since its first synthesis in 2003 [1], the ternary alloy semiconductor SiGeSn has seen an increasing interest due to its unique properties in the field of Group-IV semiconductors [2–6]. SiGeSn not only allows the decoupling of its bandgap and lattice-constant by what it is predestined for the epitaxy of strain-reduced heterostructures on the Si platform. Furthermore, SiGeSn becomes a direct bandgap semiconductor at high Sn concentrations. Considering these properties, SiGeSn is an attractive material system for optoelectronic applications. An exemplary heterojunction optoelectronic device is the single confinement heterostructure laser diode, the still missing key component for the monolithic integration of the optical on-chip communication on Si.However, one of the greatest challenges faced by many Group-IV researchers is the epitaxy of SiGeSn bulk alloys with high crystal quality. The temperature induced segregation of Sn results in interstitial Sn atoms and subsequently in acceptor-like defect states, as it was already reported for GeSn [7].In this work, we show the molecular beam epitaxy (MBE) of SiGeSn structures under Hydrogen ambient. First of all, we determined the concentration of the acceptor-like defect states of undoped SiGeSn NA,defect on the basis of capacitance-voltage (C-V) measurements of SiGeSn pin diodes. Furthermore, we investigated Hydrogen-assisted epitaxy as an approach for the reduction of the acceptor-like defect states.All epitaxy experiments were performed in a 6” MBE system, where Si, Ge and Sn are used as matrix materials and B and Sb as dopants respectively. In particular, we investigated the influence of molecular (H2) as well as atomic (H) Hydrogen on the epitaxy process and therefore the quality of the grown structures. For this purpose, the MBE system was upgraded with a Hydrogen atom beam source for the generation of an atomic Hydrogen flux.Since the Sn segregation is affected mostly by the substrate temperature, this critical growth parameter is measured in-situ using an infrared pyrometer, which allows the observation of the dynamic processes on the sample surface [8] and the precise control of the substrate temperature at TSub = 200 °C during the SiGeSn epitaxy.All SiGeSn structures are based on Ge virtual substrates (Ge-VS) on Si(001) [9], followed by a 400 nm thick additional Ge buffer layer. In order to fulfil lattice matching of SiGeSn on Ge, a constant ratio of Si and Sn of Si/Sn = 3.67 was kept for all structures. The Sn concentration was varied in the range of 5 % < cSn < 10 %. For material characterization, 300 nm thick undoped SiGeSn layers were grown on this substrate layer stack (see Fig. 1a). A detailed characterization of the crystallinity and the surface roughness was performed using X-ray diffraction (XRD) and atomic force microscopy (AFM), respectively. The comparison of AFM micrographs of SiGeSn layers, grown with and without Hydrogen assistance (see Fig. 1b) show a clear reduction of the surface roughness due to Hydrogen assisted epitaxy.In order to determine NA,defect, C-V measurements on SiGeSn pin diodes (see Fig. 1c) were performed. The diode layer structure, also based on the previously described substrate layer stack, starts with a 400 nm thick p-doped SiGeSn bottom layer with an acceptor concentration of NA = 5x1019 cm-3, followed by an 300 nm thick undoped SiGeSn layer and a closing 200 nm thick n-doped SiGeSn top layer with a donor concentration of ND = 5x1019 cm-3. Subsequently, pin diodes were fabricated using a single mesa process consisting of four basic steps: Mesa structuring using inductive coupled plasma reactive ion etching (ICP-RIE) with HBr, mesa passivation with plasma enhanced chemical vapor deposition (PECVD) grown SiO2, oxide window opening using RIE with CHF3 and metallization using sputtered Al. An exemplary device can be seen in the scanning electron microscopy (SEM) image in Fig. 1d.The SiGeSn pin diodes were electrically characterised by means of C-V measurements using a Keithley 4200 semiconductor characterisation system. For further evaluation, the C-V characteristics of the pin diodes show linear behaviour when plotted on a C-2-V-scaled diagram (Fig. 1e). Under the assumption of a strongly asymmetric pn junction, (ND >> NA,defect), the slope m of the C-2-V characteristics is proportional to NA,defect. In this manner, we determined NA,defect for several SiGeSn pin diodes in dependence of the alloy composition. The results, as shown in Fig. 1f, show an acceptor-like defect concentration between 1017 cm-3 < NA,defect < 1018 cm-3, which is comparable with results reported by other groups for GeSn [7].In our presentation, we will discuss Hydrogen-assisted epitaxy as a promising approach for improving the SiGeSn crystal quality. Figure 1

(Digital Presentation) Fabrication of Microbridges Based on Ge-on-SOI and Observation of Strong Resonant Light Emission

Introduction Ge is one of the most attractive material for silicon-based optoelectronics because it can be epitaxially grown on a Si substrate, allowing us to integrate Ge based light emitters and photodetectors monolithically on the Si platform. Although Ge is an indirect band gap semiconductor like Si, by epitaxially growing Ge on the Si substrate, tensile strain is introduced into Ge, resultantly leading to the Γ-valley shifts and increase in the light emission efficiency via the direct transition. The amount of the strain induced in Ge-on-Si, however, is not sufficiently large, demanding other methods of applying large tensile strain to Ge. Fabrication of Ge microbridge structure is expected to induce the larger strain and further improve light emission efficiency [1]. In general, microbridges reported so far have been fabricated by the electron beam lithography process, which is not appropriate for mass production. In this study, we fabricate Ge microbridge by simple photolithography process based on Ge-on-Si and Ge-on-SOI structures and very strong room temperature photoluminescence is obtained and strong resonant peaks can be observed. Experimental Method Ge layers were grown on a Si (110) wafer (Ge-on-Si) or a SOI (100) wafer (Ge-on-SOI) using a two-step growth method by solid source MBE. Firstly, a 40nm thick buffer layer at a low temperature of 350 ~ 400℃. Secondly, a 500 nm thick Ge layer was grown at a high temperature of 550 ~ 650℃. Post-growth-annealing was carried out at 800℃ for 10 minutes. The microbridge structures were defined by the standard photolithography process and mesa etching was performed by the reactive ion etching. Subsequently, the Si under the bridge and pads was selectively removed by KOH etchant, leading to free-standing Ge microbridge. For the Ge-on-SOI, the underlying SiO2 layer (buried oxide) was additionally removed by HF. Results and Discussion It was observed by SEM measurements that the Ge microbridges fabricated from Ge-on-Si were slightly warped from both ends to the center of the bridges. Hydrogen gases generated due to the reaction of Si and KOH during the selective etching are considered to be responsible for the warping of the microbridges, which makes it difficult to control the strain of the Ge. The selective etching time, therefore, has to be minimized to reduce the effects of the gas generation. For this purpose, the microbridges were fabricated from Ge-on-SOI, where the floating structure can be easily formed by the etching of the buried SiO2 layer with HF and the etching time of Si with KOH was reduced by a factor of four. As a result, the warping was completely suppressed and very flat microbridges were fabricated without any warping.Photoluminescence measurements at the center of the microbridge on Ge-on-SOI were performed at room temperature. Strong PL emissions were obtained in the wavelength range of 1630-2000 nm, where several strong resonant peaks appear. This resonance is considered to occur due to reflection at the side wall of the bridge and the peaks can be well fitted with the cavity length of the bridge width. Also, we carried out PL measurements from one end to another end of the bridge, and investigated the bridge position dependence of the PL emission. It was found that the light emission intensity increased toward the center of the bridge, and the highest intensity was obtained at the center. Moreover, the strain amounts were measured by micro Raman line scan along the bridge and strain dependence of PL emission was investigated. It was also shown that the strain amount increased toward the center of the bridge and became the highest at it. It was demonstrated that the higher PL intensity can be obtained due to the higher tensile strain at the center of the microbridge. In summary, we fabricated Ge microbridge structures by photolithography process and obtained strong room temperature resonant light emission from the Ge microbridges formed from Ge-on-SOI where bridge-warping was completely suppressed by shortening the etching time. From this result, we can say that the Ge microbridge light emitting devices are very promising for applications to the light sources on the Si platform.This work was partially supported by JSPS KAKENHI (Nos. 19H02175, 19H05616 and 20K21009).[1] M. J. Suess et al, Nat. Photonics 7: 466, 2013 Figure 1

High-rate and durable sulfide-based all-solid-state lithium battery with in situ Li2O buffering

Sulfide electrolytes (SEs)-based all-solid-state lithium batteries (ASSLBs) are advantageous over traditional lithium-ion batteries (LIBs) because of high energy density and safety. Unfortunately, the commercialization of SEs-based ASSLBs is presently hindered by interfacial instability between SEs and active materials, sluggish dynamics and poor cycling performance. Here we report, for the first time, a stable and conductive Li2O buffering coating for Ni-rich LiNi0.8Co0.1Mn0.1O2 (NCM811) in ASSLBs using SEs of Li6PS5Cl via a facile one-step sintering. We show using judiciously combined computation and experiment that Li2O buffering improves the stability of NCM811 and significantly boosts transfer of Li+. Via tuning the thickness of the Li2O buffer, we demonstrate the high initial discharge capacity of 189.66 mAh g − 1 (0.1C) and rate capability of 61.71 mAh g − 1 (3C), together with outstanding long-term cycling performance of ∼ 2600 cycles at 1C with capacity retention of 81.47%, and Coulombic efficiency of 99.9%. We conclude that conductive Li2O buffering can be used to obviate interfacial instability between SEs and active materials and to boost dynamics and cycling performance. Findings will be of immediate benefit to a range of researchers in design for high-performance ASSLBs for practical application and commercialization.

Viewing SiGe Heterostructure for Qubits with Dislocation Theory

Strained isotopically enriched 28Si strained layers in SiGe/Si/SiGe heterostrustructures is an excellent material platform for electron spin qubits. In this work, we report the fabrication of 28SiGe/28Si/28SiGe heterostructures for qubit devices by a hybrid MBE/CVD growth, where the thick relaxed SiGe buffer is realized by a reduced-pressure CVD and the 28SiGe/28Si/28SiGe stack is grown by an MBE. Here, we achieve a fully strained 28Si layer in such heterostructure with a 29Si concentration as low as 200 ppm within the MBE grown layers. It was possible to conclude that 29Si primarily originates from the residual natural Si vapour in the MBE chamber. Furthermore, we also present our studies about the growth temperature effect on the misfit dislocation formation in this heterostructure. It was possible to show that at a low MBE growth temperature, such as 350°C, the misfit dislocation formation is significantly suppressed.

Enhanced Photoluminescence of 1.3 μm InAs Quantum Dots Grown on Ultrathin GaAs Buffer/Si Templates by Suppressing Interfacial Defect Emission.

We report on the photoluminescence enhancement of 1.3 μm InAs quantum dots (QDs) epitaxially grown on an ultrathin 250 nm GaAs buffer on a Si substrate. Decreasing the GaAs buffer thickness from 1000 to 250 nm was found to not only increase the coalesced QD density from 6.5 × 108 to 1.9 × 109 cm-2 but also decrease the QD photoluminescence emission intensity dramatically. Inserting an Al0.4Ga0.6As potential barrier layer maintained strong photoluminescence from the QDs by effectively suppressing carrier leakage to the GaAs/Si interfacial region even when the GaAs buffer was thinned to 250 nm. We then fabricated a light-emitting diode using the ultrathin 250 nm GaAs buffer on Si and confirmed strong electroluminescence peaking at 1.28 μm without interfacial defect emission at room temperature. We believe that this work is promising for monolithically integrated evanescent Si lasers using InAs/GaAs QDs.

Common Metals as Electrodes for Leak‐Free Organic Light‐Emitting Devices Using Extraordinary Thick Phosphotungstic Acid Buffer Layers

AbstractElectrical leakage is one of the fatal faults associated with thin‐film devices (TFDs) including organic light‐emitting devices (OLEDs). To prevent electrical leakage, highly smooth electrodes are required to avoid the concentration of the electric field at local points. However, this requires the use of expensive electrode substrates. Here, OLEDs using inexpensive, aluminum‐foil‐based electrode substrates with an extremely high surface roughness are fabricated. A low leakage current is realized by incorporating extraordinary thick buffer layers of phosphotungstic acid (PWA) exhibiting the negative differential resistance (NDR) property. In its pristine state, PWA exhibits a high electrical resistance. However, upon applying electric current, the resistance is significantly decreased, resulting in increased conductivity and expression of NDR property, owing to the formation of conductive filaments and charge‐storage effects. The OLEDs produced with PWA achieve a low‐driving voltage and high external quantum efficiency simultaneously. Aluminum‐foil‐based OLEDs with a light‐emission area of 64 cm2 are fabricated. They emit steady luminescence even in crumpled and torn states. To the best of authors’ knowledge, this is the first report of a large‐area OLED exhibiting steady luminescence in such deformed states.

Ultrathin GaN film and AlGaN/GaN heterostructure grown on thick AlN buffer by MOCVD

High-quality AlGaN/GaN/AlN heterostructures with thin GaN channel and thick AlN buffer layer were grown by metal organic chemical vapor deposition (MOCVD) on SiC substrate. By analyzing growth modes of GaN films on AlN buffer layers with different thicknesses, it is revealed that film-forming point of GaN grown on AlN buffer increases with the increase in AlN buffer thickness. Accordingly, new growth model of GaN on AlN buffer was proposed, which shows that there is an optimal matching value between Ga source flow rate and AlN thickness when GaN is grown on AlN buffer of different thicknesses. Under optimal conditions, AlGaN/GaN/AlN heterostructures with 120 nm thin GaN channel layer and thick AlN buffer show excellent carrier-limited domain, high crystalline quality, and good transport properties. Results in this work would be useful for preparing high-quality heterostructures on AlN buffer and high electron mobility transistor (HEMT) devices. Moreover, these findings can also be applied to the growth of other hyperfine structures (quantum wells, superlattices, and digital alloys) in the future.

Efficiency enhancement of Cd-free buffer layers on CIGS solar cell performance using WxAMPS

In this paper, the impact of three buffers structures layers on the CIGS solar cell performance was numerically investigated using the one-dimensional simulation program wxAMPS. For Cd-free buffer layers, ZnS,µc_3C_SiC and Mg0.19Zn0.81O have been proposed as alternative buffers layers materials to replace the currently toxic CdS material used for the CIGS solar cells. A scrupulous optimization strategy based on the performance analysis of the thickness and doping concentration density effects was applied to each layer of the proposed stack solar cell structure ZnO/ Buffer layer/ CIGS. Moreover, the impact of the series resistance (Rs) was also examined and taken into account in the optimization process. As known, the combination of the parameter optimization (doping concentration density, thickness) with the lowest series resistance provides a minimum loss resistivity and high optical throughput. Consequently, the maximum achieved conversion efficiencies values for the three investigated solar cell structures (ZnS, µc_3C_SiC and Mg0.19Zn0.81O) were 31.16%,30.42% and 27.52%, respectively. The optimum value of 2µm was selected for the CIGS thickness while for the CIGS doping concentration density, the optimum values chosen were: 5×1018cm−3,3×1019cm−3 and 1×1018cm−3, respectively. These efficiencies parameters were obtained with a thickness absorber of 2μm, a buffer thickness layer of 40nm, and a ZnO window layer of 20nm.

Immense Reduction in Interfacial Resistance between Sulfide Electrolyte and Positive Electrode.

Low interfacial resistance between the solid sulfide electrolyte and the electrode is critical for developing all-solid-state Li batteries; however, the origin of interfacial resistance has not been quantitatively reported in the literature. This study reports the resistance values across the interface between an amorphous Li3PS4 solid electrolyte and a LiCoO2(001) epitaxial thin film electrode in a thin-film Li battery model. High interfacial resistance is observed, which is attributed to the spontaneous formation of an interfacial layer between the solid electrolyte and the positive electrode upon contact. That is, the interfacial resistance originates from an interphase mixed layer instead of a space charge layer. The introduction of a 10 nm thick Li3PO4 buffer layer between the solid electrolyte and positive electrode layers suppresses the formation of the interphase mixed layer, thereby leading to a 2800-fold decrease in the interfacial resistance. These results provide insight into reducing the interfacial resistance of all-solid-state Li batteries with sulfide electrolytes by utilizing buffer layers.

MicroRaman Study of Nanostructured Ultra-Thin AlGaN/GaN Thin Films Grown on Hybrid Compliant SiC/Por-Si Substrates

In our study, for the first time we demonstrate the advantages of using a compliant hybrid substrate of porSi/SiC to grow high-quality ultra-thin nanostructured AlxGa1−xN/GaN heterostructures using molecular beam epitaxy with plasma-activated nitrogen. Comparison of our experimental results obtained by micro-Raman spectroscopy, deconvolution, and the fitting of the experimental Raman spectra and subsequent calculations with information from already established literature sources show that the use of such a hybrid SiC/porSi substrate has a number of undeniable advantages for the growth of ultra-thin AlxGa1−xN/GaN nanoheterostructures without requiring the use of thick AIIIN buffer layers. Direct growth on a hybrid compliant substrate of SiC/porSi leads to a substantial relaxation in the elastic stresses between the epitaxial film, porous silicon, and silicon carbide, which consequently affects the structural quality of the ultra-thin AlxGa1−xN/GaN epitaxial layers. The experimental and computational data obtained in our work are important for understanding the physics and technology of AlxGa1−xN/GaN nanoheterostructures and will contribute to their potential applications in optoelectronics.

Comparative study of nanostructured ultra-thin AlGaN/GaN heterostructures grown on hybrid compliant SiC/porSi substrates by molecular beam epitaxy with plasma nitrogen activation

This study demonstrates the advantages of using a hybrid compliant substrate containing a porous silicon (porSi) layer, obtained through electrochemical etching of the original silicon substrate, and a silicon carbide (SiC) layer, formed on its surface through the Kukushkin method, to grow high-quality, ultra-thin nanostructured AlхGa1-xN/GaN heterostructures with nanocolumnar morphology by molecular beam epitaxy with plasma-activated nitrogen.Comparison of our experimental results with information from prior literature illustrates that the use of such a hybrid SiC/porSi substrate has a number of undeniable advantages for the growth of ultra-thin AlхGa1-xN/GaN nanoheterostructures without the use of thick AIIIN buffer layers. Direct growth on a hybrid compliant substrate and SiC/porSi leads to a substantial relaxation of elastic stresses between the epitaxial film, porous silicon, and silicon carbide; this consequently affects the structural quality and optical characteristics of AIIIN nitride-based transistor ultra-thin structures.The experimental and computational data obtained in our research are important for understanding the physics and technology of AlхGa1-xN/GaN nanoheterostructures, and they will contribute to their potential applications in optoelectronics.

GaN HEMTs on low resistivity Si substrates with thick buffer layers for RF signal amplification and power conversion

We report GaN high-electron-mobility transistors (HEMTs) with a thick (7.7 µm) GaN buffer on a Czochralski low resistivity Si (LRS) substrate. The GaN HEMTs exhibit high performance for both radio-frequency (RF) amplification and power conversion. The thick GaN buffer was grown by means of vacancy engineering, delivering a low dislocation density of ∼1.6 × 108 cm−2, contributing to suppressed RF signal coupling to the lossy Si substrate and a high vertical voltage blocking capability. For RF performance, GaN HEMTs with a 650 nm gate exhibit an fT/fMAX value of 25.1/32.3 GHz and a maximum output power POUT of 2.2 W/mm at 4 GHz with a drain voltage VDS of 20 V, which is comparable with the performance of RF GaN HEMTs on a high-resistivity silicon substrate without the existence of the field plate. For power performance, the vertical breakdown voltage of the wafer is 1160 V, and the three-terminal lateral breakdown voltage is 885 V in a GaN HEMT with a gate-to-drain distance of 8 µm. The thick GaN layer on the LRS substrate scheme thus provides a compelling platform for monolithic integration of high-performance RF devices and high-voltage power devices.

Oxide Two-Dimensional Electron Gas with High Mobility at Room-Temperature.

The prospect of 2‐dimensional electron gases (2DEGs) possessing high mobility at room temperature in wide‐bandgap perovskite stannates is enticing for oxide electronics, particularly to realize transparent and high‐electron mobility transistors. Nonetheless only a small number of studies to date report 2DEGs in BaSnO3‐based heterostructures. Here, 2DEG formation at the LaScO3/BaSnO3 (LSO/BSO) interface with a room‐temperature mobility of 60 cm2 V−1 s−1 at a carrier concentration of 1.7 × 1013 cm–2 is reported. This is an order of magnitude higher mobility at room temperature than achieved in SrTiO3‐based 2DEGs. This is achieved by combining a thick BSO buffer layer with an ex situ high‐temperature treatment, which not only reduces the dislocation density but also produces a SnO2‐terminated atomically flat surface, followed by the growth of an overlying BSO/LSO interface. Using weak beam dark‐field transmission electron microscopy imaging and in‐line electron holography technique, a reduction of the threading dislocation density is revealed, and direct evidence for the spatial confinement of a 2DEG at the BSO/LSO interface is provided. This work opens a new pathway to explore the exciting physics of stannate‐based 2DEGs at application‐relevant temperatures for oxide nanoelectronics.

Re-evaluation of the bentonite buffer dimension in a geological repository for spent nuclear fuel under the KURT conditions

The KBS-3 type geological repository was proposed for the disposal of spent nuclear fuel around 40 years ago. The long-term safety of the repository strongly depends on an engineered barrier consisting of a copper disposal canister and a bentonite buffer. The major functions of the buffer are to protect the disposal canister against corrosion and minimize the release of radionuclides from the canister. However, the current design of a thick buffer height above a canister makes it difficult to retrieve the deposited spent nuclear fuel. In this work, we re-evaluate the dimensions of a buffer in terms of radionuclide migration and corrosion using a mathematical approach under the KURT conditions. The calculation results show that the corrosion lifetime of the canister is longer than one million years even if the buffer thickness is reduced from 0.36 m to 0.25 m. Similarly, the buffer height above a disposal canister is reduced from 2.5 m to 1.5 m. However, it is expected that more detailed further analyses such as effects of buffer uplifting and buffer erosion should be carried out to carefully assure the safety of the repository.

Interfacial engineering for semi-insulating GaN/sapphire template with low dislocation density

Achieving semi-insulating (SI) GaN epilayers with low threading dislocation density (TDD) on sapphire substrates is critically important but challenging for electronic and optoelectronic devices. To obtain low-TDD SI GaN within a thin layer, herein, we performed interfacial engineering for early regulating dislocation and impurity behaviors. It is found that introducing an ultrathin (10 nm) sputtered AlN interfacial buffer layer can effectively suppress dislocations and oxygen (O) impurities. Compared with GaN and thick AlN buffer layers, the ultrathin AlN buffer layer can be nano-pixelated into discrete islands with higher density, ensuring an adequate three-dimensional growth with locally quick coalescence. Hence, the TDD value of the GaN epilayer was rapidly decreased to a low level at the earlier stage of growth. In addition, benefiting from the high diffusion barrier of O in AlN, AlN buffers demonstrate a superior blocking effect of O impurities over GaN buffer, even if the thickness is only 10 nm. Finally, GaN epilayer with a TDD value of 2.7 × 108 cm−2 and a sheet resistance of 2.43 × 1011 Ω/sq can be achieved at the same time. The interfacial buffer engineering provides a simple and effective strategy to obtain high-crystalline-quality SI materials, without additional negative effects introduced.

Reducing the Source Resistance by Increasing the Gate Effect on Substrate for Future Terahertz HEMT Device

In this paper, we present the dependence of source resistance sensibility on the gate bias effect in a High Electron Mobility Transistor (HEMT) using the Drift-Diffus (D-D) model with the SILVACO Technology Computer-Aided Design (TCAD) tool. The obtained results show that the increases of gate bias effect on substrate lead to decreasing the source resistance of the simulated device. The reported increase in the effect of gate induces the increases of transferred holes concentration towards the source region and which induce the decreases of source resistance. The decrease of source resistance can also be made by reducing the buffer thickness which leads to an increase in the gate effect on the substrate. The source resistance value is influenced by the Drain-Induced Barrier Lowering (DIBL) effect where the rate of decreasing the source resistance will be decreasing consequently to increase the drain bias. The reduction of the source resistance induces the increase of device sensibility for lows values of current.

Ultra-thin AlGaN/GaN HFET with a high breakdown voltage on sapphire substrates

In this Letter, an ultra-thin AlGaN/GaN heterostructure field effect transistor (HFET) with a total thickness of ∼200 nm was fabricated on sapphire substrates by combing physical vapor deposition and metal organic chemical vapor deposition growth methods. Thanks to the absence of a conventional semi-insulating thick GaN buffer by taking advantage of an ex situ sputtered AlN nucleation layer, we achieved a profound soft breakdown voltage of 1700 V accompanied by a 12.5 Ω·mm on-resistance and a low off-state leakage of 0.1 μA/mm in such ultra-thin HFET devices. Our work demonstrates an alternative strategy to fabricate GaN based power devices with high breakdown voltage and low cost.

Complex magnetic textures in Ni/Irn/Pt(111) ultrathin films

A combined approach using first-principles calculations and spin dynamics simulations is applied to study $\mathrm{Ni}/{\mathrm{Ir}}_{n}/\mathrm{Pt}(111)$ ($n=0,1,2$) films. The lowest-energy states are predicted to be spin spirals but with a minute (of the order of a few $\ensuremath{\mu}\mathrm{eV}/\mathrm{atom}$) energy difference with skyrmionic states. The spontaneous low-temperature skyrmions, with $\ensuremath{\sim}15$ nm to $\ensuremath{\sim}35$ nm size, arise from a large Dzyaloshinskii-Moriya (DM) and Heisenberg exchange interactions ratio and, in particular, from a large in-plane DM vector component for nearest neighbors. The skyrmions become larger and more dispersed with the enhancement of the Ir buffer thickness. Also, with increasing $n$, the skyrmions' stability decreases when an external magnetic field is applied or the temperature is raised. For $n=0$ and $n=1$, we find that metastable skyrmioniums can occur, which are characterized by a slightly lower stability with respect to the external fields and larger critical currents, compared to skyrmions.

GaAsP/SiGe tandem solar cells on porous Si substrates

III-V compound semiconductors and SiGe alloys can be combined to develop multijunction solar cells on Silicon substrates with optimum bandgap combinations. Current implementations of such devices have reached efficiencies over 20%, using thick –and thus costly– buffer layers which induce the appearance of cracks in large area samples. As a strategy to mitigate these two issues (thick buffers and cracking), a GaAsP/SiGe tandem solar cell has been developed employing group IV reverse graded buffer layers grown on Ge/Si virtual substrates with a subsurface Silicon porous layer. Reverse buffer layers facilitate a reduction in the threading dislocation density with limited thicknesses but can also induce cracks. To minimise this, a porous silicon layer has been incorporated close to the Ge/Si interface so that the ductility of this layer suppresses crack propagation. In terms of solar cell performance, this porous layer reduces the problem of cracks, not totally supressing them though. Accordingly, the low shunt resistance observed in previous designs has been increased thus improving solar cell efficiency, which is still notably behind designs using thicker forward graded buffer layers. The first results of this new architecture are presented here.