Thermionic Limit Research Articles

Steep Slope Field Effect Transistors Based on 2D Materials

AbstractWith field effect transistor (FET) sustained to downscale to sub‐10 nm nodes, performance degradation originates from short channel effects (SCEs) degradation and power consumption increment attributed to inhibition of supply voltage (VDD) scaling down proportionally caused by thermionic limit subthreshold swing (SS) (60 mV dec−1) pose substantial challenges for today's semiconductor industry. To further sustain the Moore's law life, incorporation of new device concepts or new materials are imperative. 2D materials are predicted to be able to combat SCEs by virtue of high carrier mobility maintainability regardless of thickness thinning down, dangling bonds free surface and atomic thickness, which contributes to super gate electrostatic controllability. To overcome increasing power dissipation problem, new device structures including negative capacitance FET (NCFET), tunnel FET (TFET), dirac source FET (DSFET) and the like, which show superiority in decreasing VDD by lowering SS below thermionic limit of 60 mV dec−1 have been brought out. The combination of 2D materials and ultralow steep slope device structures holds great promise for low power‐dissipation electronics, which encompass both suppressed SCEs and reduced VDD simultaneously, leading to improved device performance and lowered power dissipation.

Strain tuning on Van der Waals negative capacitance transistors

Negative differential capacitance induced by the energy barrier formed by the nonlinear ferroelectric insulating layer during the phase transition in negative capacitance field effect transistors (NCFETs) can break through the fundamental thermionic limit of the metal-oxide-semiconductor field effect transistors (MOSFETs), which is set at a subthreshold swing (SS) of 60 mV/dec at room temperature for low-power switching. Strain engineering has been shown effective for modulating both intrinsic and coupled properties of ferroelectric materials. However, while the modulation of negative capacitance (NC) by strain primarily remains within theoretical predictions, there is a lack of experimental studies to explore its effect on NCFETs. This study introduces strain to NCFETs by utilizing the magnetostriction of Terfenol-D upon the applied magnetic field. Results reveal a decrease in SSmin from 43.5 mV/dec to 15.2 mV/dec with a compressive strain increase from 0 to −0.005%. Additionally, theoretical results by using time-evolving Ginzburg-Landau equations and Kirchhoff's laws demonstrate that compressive strain enhances both the amplitude and duration of transient NC in CuInP2S6, while vice versa under tensile strain. This work offers valuable insights for the design of NCFET devices.

Steep slope threshold switching field‐effect transistors based on 2D heterostructure

AbstractIn dealing with the increasing power dissipation of electronic systems with increasing integration density, a field‐effect transistor (FET) with steep switching slope that overcomes the thermionic limit is vital to achieve low‐power operations. Here, we report two types of threshold switching (TS) FETs based on 2D Van der Waals heterostructures by virtue of the abrupt resistive switching of the hexagonal boron nitride (hBN) TS device. The common hBN dielectric layer functions as the switching medium for the TS device and the gate dielectric for the 2D FET enabling seamless integration of the hBN TS device and baseline 2D FET. TS FET in source configuration by connecting the TS device to the source terminal of the 2D FET offers an ultralow average subthreshold swing (SS) of 1.6 mV/dec over six decades of drain current at room temperature and suppressed leakage current. TS FET in gate configuration by connecting the TS device to the gate terminal of the 2D FET also exhibits steep switching slope with ultralow SS of 10.6 mV/dec. The proposed compact device structures integrating 2D FET and TS device provide a potential approach of monolithic integration toward next‐generation low‐power electronics.

Quantum interference enhances the performance of single-molecule transistors

Quantum effects in nanoscale electronic devices promise to lead to new types of functionality not achievable using classical electronic components. However, quantum behaviour also presents an unresolved challenge facing electronics at the few-nanometre scale: resistive channels start leaking owing to quantum tunnelling. This affects the performance of nanoscale transistors, with direct source–drain tunnelling degrading switching ratios and subthreshold swings, and ultimately limiting operating frequency due to increased static power dissipation. The usual strategy to mitigate quantum effects has been to increase device complexity, but theory shows that if quantum effects can be exploited in molecular-scale electronics, this could provide a route to lower energy consumption and boost device performance. Here we demonstrate these effects experimentally, showing how the performance of molecular transistors is improved when the resistive channel contains two destructively interfering waves. We use a zinc-porphyrin coupled to graphene electrodes in a three-terminal transistor to demonstrate a >104 conductance-switching ratio, a subthreshold swing at the thermionic limit, a >7 kHz operating frequency and stability over >105 cycles. We fully map the anti-resonance interference features in conductance, reproduce the behaviour by density functional theory calculations and trace back the high performance to the coupling between molecular orbitals and graphene edge states. These results demonstrate how the quantum nature of electron transmission at the nanoscale can enhance, rather than degrade, device performance, and highlight directions for future development of miniaturized electronics.

Negative capacitance field-effect transistors based on ferroelectric AlScN and 2D MoS2

Al0.68Sc0.32N (AlScN) has gained attention for its outstanding ferroelectric properties, including a high coercive field and high remnant polarization. Although AlScN-based ferroelectric field-effect transistors (FETs) for memory applications have been demonstrated, a device for logic applications with minimal hysteresis has not been reported. This study reports on the transport characteristics of a MoS2 negative capacitance FET (NCFET) based on an AlScN ferroelectric material. We experimentally demonstrate the effect of a dielectric layer in the gate stack on the memory window and subthreshold swing (SS) of the NCFET. We show that the hysteresis behavior of transfer characteristics in the NCFET can be minimized with the inclusion of a non-ferroelectric dielectric layer, which fulfills the capacitance-matching condition. Remarkably, we also observe the NC effect in MoS2/AlScN NCFETs arrays based on large-area monolayer MoS2 synthesized by chemical vapor deposition, showing the SS values smaller than its thermionic limit (∼36 to 60 mV/dec) and minimal variation in threshold voltages (<20 mV).

Observing suppressed polarization in flexible ferroelectric negative capacitance field effect transistors

Negative capacitance (NC) has the potential to enable low power microelectronics beyond the fundamental thermionic limit, and it has been theorized that the thermodynamically unstable NC of ferroelectrics can be stabilized by linear dielectric, making negative capacitance ferroelectric field effect transistors (NC-FeFET) possible. Nevertheless, the validity of NC as a physical concept for ferroelectrics remain contentious despite numerous theoretical and experimental investigations, and the intrinsic ferroelectric NC with suppressed polarization has not been demonstrated except locally at vortex core. While NC-FeFET with subthreshold swing (SS) lower than 60 mV/dec limit has been reported, such device characteristics has not been directly connected to suppressed polarization at materials’ level, and alternative mechanisms other than NC have also been proposed. Here we demonstrate stable sub-60 mV/dec SS with hysteresis free IV in NC-FeFET based on SrTiO3/Pb(Zr0.1Ti0.9)O3/SrTiO3 heterostructure, and observe its suppressed polarization at both macroscopic and microscopic scales. The intrinsic ferroelectric NC thus is experimentally confirmed and directly connected to NC-FeFET performance, and the mica-based device is also highly flexible and robust under cyclic bending as well as extended heating.

Полевой транзистор с металлическим затвором

The design and the principle of operation of a field effect transistor based on a semiconductor nanowire with a metal gate is presented and described. The subthreshold slope of the device has been estimated and was shown that it may to exceed the thermionic limit (value e/k_B T).

Robust Subthermionic Topological Transistor Action via Antiferromagnetic Exchange

The topological quantum field-effect transition in buckled two-dimensional-Xenes can potentially enable subthermionic transistor operation coupled with a dissipationless on-state conduction. We investigate realistic device structures that exploit the quantum field-effect transition between the dissipationless topological phase and the band-insulator phase. We find that the previously considered dual-gate structure is disadvantageous, leading to a near doubling of the subthreshold swing. However, we identify a single-gate strategy capable of overcoming the thermionic limit at the cost of sacrificing the dissipationless on-state conduction. By introducing an out-of-plane antiferromagnetic exchange in the material via proximity coupling, we exploit transitions between the quantum spin-valley Hall and the spin quantum anomalous Hall phase, which restore the topological robustness of the on state while simultaneously surpassing the thermionic limit. Our work thus outlines a realistic pathway to topological transistors that can overcome Boltzmann's tyranny while preserving topological robustness.

M3C2(OH)2 (M = Zr and Hf): An Ideal Electrode Material for sub‐5 nm 2D Field‐Effect Transistors

AbstractRealizing Ohmic contact is essential but challenging in the development of high‐performance 2D‐material‐based electronics. Here, using first‐principles calculations, the interfacial properties between 2D metallic M3C2T2 (M = Ti, Zr, Hf; T = O, F, OH) and 2D semiconductors are comprehensively investigated, taking group ΙV monochalcogenides in blue‐phosphorene phase as example, and the performance of short‐channel field‐effect transistors (FETs) with M3C2(OH)2 electrode is studied. The band alignments and the interface dipole analysis demonstrate that the M3C2(OH)2 and Ti3C2O2 electrodes form van der Waals interaction with the group ΙV monochalcogenides, conductive to weakening the Fermi level pinning and forming desired Ohmic contacts. Moreover, owing to the large work function of the Ti3C2O2, it realizes p‐type Ohmic contacts with 2D semiconductors. In addition, due to the favorable Ohmic contacts, the on/off ratio of the 5 nm gate‐length Zr3C2(OH)2–GeTe FET is around 105. Moreover, for the 3 nm gate‐length Zr3C2(OH)2–SnTe FET after adopting optimizing strategies, the on/off ratio increases from 102 to 106, and the subthreshold slope decreases from 125 mV dec‐1 to 58 mV dec‐1 below the thermionic limit (60 mV dec‐1). The results provide a theoretical guidance for achieving the intrinsic n‐type and p‐type Ohmic contacts and high‐performance FETs in 2D nanoelectronics.

Simulation Study of Hetero-Junction Single Gate Extended Source TFET

The paper provides the information regarding the examination of Uni-Gate-Extended Source TFET w.r.t the doping concentration of source, drain and channel and device’s dimensions. The moto of extending the source into channel is to enhance the point to point tunneling. 2D simulations in TCAD tool are carried out to analyse and investigate the performance of proposed device. Because of the transposed SS down the thermionic limit of 60 mV/decade, TFETs can be considered as the most trustworthy devices that have lower power consumption and that’s why they are among the deserving devices for upcoming future CMOS logic applications. Although the TFET marks have been examined in fewer material systems, they are burdened by low ON-currents. We discussed the impact of sound on Tunnel FET devices and circuits. The dialogue is designed for the sound of a random noise effects. The paper also deals with configuration of gm and gd and their obtained significant values are rise up in the graph till 1x10-4 V-1 and 2x10-4V-1.

Dirac-source diode with sub-unity ideality factor

An increase in power consumption necessitates a low-power circuit technology to extend Moore’s law. Low-power transistors, such as tunnel field-effect transistors (TFETs), negative-capacitance field-effect transistors (NC-FETs), and Dirac-source field-effect transistors (DS-FETs), have been realised to break the thermionic limit of the subthreshold swing (SS). However, a low-power rectifier, able to overcome the thermionic limit of an ideality factor (η) of 1 at room temperature, has not been proposed yet. In this study, we have realised a DS diode based on graphene/MoS2/graphite van der Waals heterostructures, which exhibits a steep-slope characteristic curve, by exploiting the linear density of states (DOSs) of graphene. For the developed DS diode, we obtained η < 1 for more than four decades of drain current (ηave_4dec < 1) with a minimum value of 0.8, and a rectifying ratio exceeding 108. The realisation of a DS diode represents an additional step towards the development of low-power electronic circuits.

Mixed‐Dimensional van der Waals Engineering for Charge Transfer Enables Wafer‐Level Flexible Electronics

AbstractFlexible electronics draw intense interest because of their promising potential for emerging applications, which, however, encounter challenging obstacles of material self‐limiting fabrication, trade‐off mechanical flexibility, and associated moderate electrical performance. Here, wafer‐level flexible fully‐carbon‐integrated transistors via mixed‐dimensional van der Waals (vdW) engineering is realized. Remarkable performance includes subthreshold swing of 51.8 mV dec−1 breaking thermionic limit, outstanding field‐effect mobility as high as 313.8 cm2 V−1 s−1, and sub‐1 V operating voltage. The charge transfer modulation of graphene oxide on carbon nanotube in the vdW‐integrated transistors is designed to enhance channel conductance, which is simultaneously confirmed by theoretical calculations and electrical characterizations. Besides, the transistors maintain stable electrical performance after bending under an ultra‐small radius of 250 µm. Exponential‐sensitivity temperature sensors and binary‐logic inverters are further realized to demonstrate the feasibility of the devices as the building blocks of all‐vdW electronics. These results indicate that either the strategy of all‐vdW transistor realization or the charge transfer provides general approach to improve device performance and further advance flexible electronic technologies.

A steep-slope tellurium transistor with a native voltage amplifying threshold switch

What precludes lowering the supply voltage and overall power consumption of the transistor is the infamous Boltzmann tyranny, a fundamental thermionic limit preventing the subthreshold slope (SS) of the transistor from being lower than 60 mV dec−1 at room temperature (RT). Internal voltage amplification through the use of an additional threshold switch (TS) serially connected to the transistor channel has been shown to be highly effective to break the Boltzmann barrier. This approach, however, is typically heterogeneous by employing TS materials that are foreign to the transistor. Recently, semiconducting tellurium (Te) has gained considerable research interest for its use as an emerging low-dimensional p-type channel material with high hole mobility, air-stability, and the ability to be processed at near ambient temperature. In this work, we unveil a hidden advantage of Te for a steep-slope transistor in which Te serves as the channel material and the TS material at the same time. In a homogeneous and compact device architecture, RT-SS lower than 30 mV dec−1 can be achieved. This is enabled by a combination of unique electrical–electrochemical–thermal properties in Te. This work augments the functionality of Te and provides a low-power transistor solution.

Organic steep-slope nano-FETs: A rational design based on two-dimensional covalent-organic frameworks

We report a strategy to design organic steep-slope nanoscale field-effect transistors (nano-FETs) with subthreshold swing (SS) breaking the thermionic limit of 60 mV/dec at room temperature. The devices are based on a family of two-dimensional (2D) covalent-organic frameworks (COFs) with a square lattice and building blocks of metallophthalocyanine (MPc). Our first-principles calculations reveal that lattice mismatch-free metal/semiconductor monolayer heterojunctions, which serve as both electrodes and channel of the devices, can be obtained by modulating monolayer 2D MPc-COFs with suitable MPc. The cold-source mechanism and the interplay between electrodes and channel are of critical importance for realizing doping-free organic steep-slope nano-FETs, of which the SS can reach as small as 37.2 mV/dec at 300 K. Our findings offer a route to overcome the “Boltzmann tyranny” in low-power nanoelectronic devices by rational design of organic 2D materials, which are much more diverse and flexible in material design than their inorganic counterparts. • Organic nano-FETs with subthreshold swing breaking the thermionic limit of 60 mV/dec at room temperature were proposed. • The devices are based on two-dimensional covalent-organic frameworks of metallophthalocyanine. • The cold-source mechanism and the interplay between electrodes and channel are the underlying mechanism for the devices.

MoS2 transistors gated by ferroelectric HfZrO2 with MoS2/mica heterojunction interface

Two-dimensional (2D) molybdenum disulfide (MoS2) field-effect transistor (FET) gated by negative capacitance (NC) is a promising architecture to overcome the thermionic limit and thus reduce device consumption. Here, top-gated MoS2 NCFETs have been prepared by transferring a mica flake on MoS2 channel to form a van der Waals heterojunction interface, together with a ferroelectric HfZrO2 (HZO) deposited on mica. Stable NC effects are demonstrated for MoS2 NCFETs. The MoS2 NCFETs integrated with mica/HZO gate stack provide competitive electrical characteristics when they are applied with a gate voltage sweep-width in the range of 1−3 V and a sweep-rate from 0.01 to 0.2 V s−1, including steep-slope of sub 60 mV dec−1 in four orders of magnitude of drain current, on/off current ratio over 106, and small hysteresis-width less than 50 mV. Outstanding performance should be ascribed to damage-free properties of mica/MoS2 van der Waals interface and capacitance matching between the HZO ferroelectric and mica dielectric. The results confirm the promising nature of mica/HZO gate stack and potential applications for future electronics.

Tunneling Junction as Cold Source: Toward Steep-Slope Field-Effect Transistors Based on Monolayer MoS2

In ultrascaled field-effect transistors (FETs), the thermionic limit to subthreshold swing (SS) represents a serious issue impeding their low-power application. Here, we propose a novel tunneling cold source FET (TCS-FET) to realize steep-slope (with SS less than 60 mV/dec) low-power devices, in which a p-n junction serves as cold source as a result of self-filtering of the electronic thermionic tail. Our first-principles calculations on the electrical properties of the TCS-FET based on monolayer MoS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> predict that large ON/OFF current ratio ( I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> / I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> ) up to 1.6 ×10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">9</sup> and steep SS as small as 32 mV/dec can be obtained. Moreover, by considering atomic doping at the source, we demonstrate that defects engineering is effective in optimizing both I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> / I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> and SS of the devices. This study is important for guiding the design of nanoscale steep-slope FETs based on 2-D materials.

Gate-controlled MoTe2 homojunction for sub-thermionic subthreshold swing tunnel field-effect transistor

A tunnel field-effect transistor (TFET) activated by a quantum band-to-band tunneling mechanism has encouraged the acceleration of nanodevices owing to its capability to beat the thermionic emission limit of a subthreshold swing (SS) (60 mV dec−1) in conventional metal-oxide-semiconductor FETs. Despite numerous studies, fabricating a TFET based on two-dimensional materials remain several major concerns due to factors such as a low on–off current ratio, weak air stability, and large hysteresis. Herein, we developed a MoTe2 homojunction-based TFET with bottom metal contacts and a defect-free polymer substrate. The transfer characteristic shows a sub-thermionic minimum SS of 36.4 mV dec−1 and SS average over four decades of 46 mV dec−1 at 300 K, with negligible hysteresis. In particular, a smaller supply voltage of 0.6 V (vs. 0.7 V for Silicon technology) is realized in the TFET. Furthermore, our device exhibits an excellent on/off current ratio of ~108, strong air stability for a period of over several months and a sub-Boltzmann limit, body factor of m = 0.21. This study demonstrates a strategy for a van der Waals heterostructure assembly and describes the considerable progress in TFET research.

Strain engineered C31 field-effect-transistors: a new strategy to break 60 mV/decade by using electron injection from intrinsic isolated states

A novel steep-slope field-effect-transistor is proposed to break the thermionic limit by using the intrinsic isolated states in materials. The monolayer C31 is used as the injection source to self-filter out high-energy electrons and strain engineering is adopted to modulate the energy gap and IS width. It is found that, under 8% biaxial tensile strain, the calculated subthreshold swing is as low as ∼28.7 mV dec−1 with a high current ratio (I ON/I OFF) of ∼3.9 × 107, demonstrating that the proposed strategy could be a promising candidate for the future developments of low-power nanodevices.

3‐4: Invited Paper: All‐Inkjet‐Printed Low‐Voltage Organic Thin‐Film Transistors

Organic thin‐film transistors (OTFTs) have the advantage of potentially low‐cost manufacturing and mechanical robustness. However, the traditional OTFT requires high operating voltages, thereby constraining its applications in the real world. In this paper, we examine the main issues underlying the OTFT that lead to a high operating voltage. We review printed OTFTs and demonstrate ways to reduce the operating voltage by suppressing the interface trap density. Recent advances in all‐inkjet‐printed low‐voltage organic thin‐film transistors show it is possible for the subthreshold slope to approach the thermionic limit. Based on this technology, an all‐inkjet‐printed ultra‐low‐power high‐gain amplifier, applied to eye movement tracking by detecting human electrooculogram signals, is presented.

Design and investigation of negative capacitance–based core‐shell dopingless nanotube tunnel field‐effect transistor

Investigation and analysis of a ferroelectric material–based dopingless nanotube tunnel field-effect transistor are conducted using a lead zirconate titanate (PZT) gate stack to induce negative capacitance in the device. Landau–Khalatnikov equations are used in deriving the parameter values of the ferroelectric material to ensure accurate results. The nanotube structure of the tunnel field-effect transistor allows for better electrostatic control owing to its gate-all-around structure. Incorporation of negative capacitance further reduces the voltage supply requirement and power consumption of the structure while simultaneously improving switching. In addition, the device is studied for varying thicknesses of the dielectric PZT material. The threshold voltage of the device under study was calculated as 0.281 V, and the average subthreshold slope of the device was reduced to 18.271 mV/decade, far below the thermionic limit of 60 mV/decade.