Thermal Laser Stimulation Research Articles

Preliminary Study on Automatic Detection of Hard Defects in Integrated Circuits Based on Thermal Laser Stimulation

Locating the fault position is a crucial part of the failure mechanism analysis of integrated circuits. This paper proposes a hard defect locating system based on Thermal Laser Stimulation (TLS) technology. The equation for laser-induced changes in the electrical parameters of semiconductor devices is a good guide to the hardware and software design of the hard defect locating system. The scanning mode of fast total scanning combined with slow point-to-point scanning can quickly locate abnormal areas. A modified median absolute difference (MAD) method is applied to the extraction of anomalous data. The system software can automatically and collaboratively control the 3D mobile station, laser, and signal acquisition unit. It also can intuitively display the distribution of abnormal points on the infrared image. Using a failure MRAM chip and a good one to conduct a comparative test, the abnormal points distributed on the infrared image of the chip indicate that the failure area is in the digital module or eFuse module of the chip, and the Emission Microscopy (EMMI) experiment also verifies the accuracy of the test system.

Simulation based dynamic laser stimulation for failure analysis of analog and mixed-signal circuits

With the increasing complexity of circuits, it is difficult to carry out fault isolation in a short time. This is particularly true for mixed-signal circuits when using only standard fault isolation techniques (e.g. EMMI or TLS). It is often complicated to tell whether a spot is a consequence of a failure or points out the location of the defect itself. In this scenario, circuit simulators are a solution to resolve this ambiguity and ease this task. This work proposes a simulation method for circuits inspected using thermal laser stimulation techniques. Furthermore, simulations for the dynamic laser stimulation technique are proposed with encouraging results for failure analysis.

Preliminary Study on the Model of Thermal Laser Stimulation for Defect Localization in Integrated Circuits

Thermal Laser Stimulation (TLS) is an efficient technology for integrated circuit defect localization in Failure Analysis (FA) laboratories. It contains Optical Beam-Induced Resistance Change (OBIRCH), Thermally-Induced Voltage Alteration (TIVA), and Seebeck Effect Imaging (SEI). These techniques respectively use the principle of laser-induced resistance change and the Seebeck effect. In this paper, a comprehensive model of TLS technology is proposed. Firstly, the model presents an analytical expression of the temperature variation in Integrated Circuits (IC) after laser irradiation, which quantificationally shows the positive correlation with laser power and the negative correlation with scanning velocity. Secondly, the model describes the opposite influence of laser-induced resistance change and the Seebeck effect in the device. Finally, the relationship between the current variation measured in the experiment and other parameters, especially the voltage bias, is well explained by the model. The comprehensive model provides theoretical guidance for the efficient and accurate defect localization of TLS technology.

Evaluation of Low-Cost Thermal Laser Stimulation for Data Extraction and Key Readout

Recent attacks using thermal laser stimulation (TLS) have shown that it is possible to extract cryptographic keys from the battery-backed memory on state-of-the-art field-programmable gate arrays (FPGAs). However, the professional failure analysis microscopes usually employed for these attacks cost in the order of 500k to 1M dollars. In this work, we evaluate the use of a cheaper commercial laser fault injection station retrofitted with a suitable amplifier and light source to enable TLS. We demonstrate that TLS attacks are possible at a hardware cost of around 100k dollars. This constitutes a reduction of the resources required by the attacker by a factor of at least five. We showcase two actual attacks: data extraction from the SRAM memory of a low-power microcontroller and decryption key extraction from a 20-nm technology FPGA device. The strengths and weaknesses of our low-cost approach are then discussed in comparison with the conventional failure analysis equipment approach. In general, this work demonstrates that TLS backside attacks are available at a much lower cost than previously expected.

Failure analysis case studies of floating nets in mixed-signal IC

Two case studies concerning failure analysis on open via defects are presented in this paper. Both of them were performed on a mixed-signal product for automotive application and showed several analysis techniques used to find defective net. First example showed the use of well-known Emission Microscopy (EMMI) in combination with advanced electrical setup to highlight floating net. This case study showed the need to thoroughly interpret EMMI signatures in combination with extensive setup investigation in order to solve an analysis with a complex failure mode. Second example showed an innovative use of Dynamic Thermal Laser Stimulation to identify a floating gate.

Assessment of nociception and related quality-of-life measures in a porcine model of neurofibromatosis type 1.

Neurofibromatosis type 1 (NF1) is an autosomal dominant genetic disorder resulting from germline mutations in the NF1 gene, which encodes neurofibromin. Patients experience a variety of symptoms, but pain in the context of NF1 remains largely underrecognized. Here, we characterize nociceptive signaling and pain behaviors in a miniswine harboring a disruptive NF1 mutation (exon 42 deletion). We present the first characterization of pain-related behaviors in a pig model of NF1, identifying unchanged agitation scores, lower tactile thresholds (allodynia), and decreased response latencies to thermal laser stimulation (hyperalgesia) in NF1 (females only) pigs. Male NF1 pigs with tumors showed reduced sleep quality and increased resting, 2 health-related quality-of-life symptoms found to be comorbid in people with NF1 pain. We explore these phenotypes in relationship to suppression of the increased activity of the N-type voltage-gated calcium (CaV2.2) channel by pharmacological antagonism of phosphorylation of a regulatory protein-the collapsin response mediator protein 2 (CRMP2), a known interactor of neurofibromin, and by targeting the interface between the α subunit of CaV2.2 and the accessory β-subunits with small molecules. Our data support the use of NF1 pigs as a large animal model for studying NF1-associated pain and for understanding the pathophysiology of NF1. Our findings demonstrate the translational potential of 2 small molecules in reversing ion channel remodeling seen in NF1. Interfering with CaV2.2, a clinically validated target for pain management, might also be a promising therapeutic strategy for NF1-related pain management.

Key Extraction Using Thermal Laser Stimulation

Thermal laser stimulation (TLS) is a failure analysis technique, which can be deployed by an adversary to localize and read out stored secrets in the SRAM of a chip. To this date, a few proof-of-concept experiments based on TLS or similar approaches have been reported in the literature, which do not reflect a real attack scenario. Therefore, it is still questionable whether this attack technique is applicable to modern ICs equipped with side-channel countermeasures. The primary aim of this work is to assess the feasibility of launching a TLS attack against a device with robust security features. To this end, we select a modern FPGA, and more specifically, its key memory, the so-called battery-backed SRAM (BBRAM), as a target. We demonstrate that an attacker is able to extract the stored 256-bit AES key used for the decryption of the FPGA’s bitstream, by conducting just a single non-invasive measurement. Moreover, it becomes evident that conventional countermeasures are incapable of preventing our attack since the FPGA is turned off during key recovery. Based on our time measurements, the required effort to develop the attack is shown to be less than 7 hours. To avert this powerful attack, we propose a low-cost and CMOS compatible countermeasure circuit, which is capable of protecting the BBRAM from TLS attempts even when the FPGA is powered off. Using a proof-of-concept prototype of our countermeasure, we demonstrate its effectiveness against TLS key extraction attempts.

Lock-in thermal laser stimulation for non-destructive failure localization in 3-D devices

We report a new non-destructive method to localize interconnection failures in 3-D devices. The scanning optical microscopy (SOM) technique is based on lock-in thermal laser stimulation (LI-TLS) and uses thermal waves to non-destructively map the current path in a 3-D device. We validate the method with test structures and show how the magnitude and phase of a propagating thermal wave may provide valuable 3-dimensional information on the failure location. We apply the technique on a short failed chain structure in a four level chip stack with an intensity modulated laser as a thermal wave injector and the structure under test as a detector. We confirm our results by physical failure analysis through a selective cross sectioning process.

Static logic state analysis by TLS on powered logic circuits: Three case studies for suspected stuck-at failure modes

Thermal Laser Stimulation (TLS) for static logic state analysis is applied to failure analysis. Three case studies of analyses of the digital logic in an automotive Application Specific Integrated Circuit (ASIC) are discussed. By analyzing the logic states of the circuit we were able to identify the mechanism and localize the site of irregular behavior non-destructively, both for a stuck-at fault and two weak interconnects. The approach measures the power supply current while applying TLS to the device back side. This allows an extremely high analysis coverage, because every transistor is connected to the power supply, making this method a universal tool for every digital circuit failure analysis (FA) workflow, because the gained understanding of the fault allows to replace multiple steps of alternative FA techniques by only a single technique, reducing time and cost for successful FA.

Signal noise perturbation on automotive mixed-mode semiconductor device generated by graded substrate defect

The semiconductor technologies evolution allows greatly reducing noise impact on products and many structures have been created to reduce its effect. However, this paper presents the apparition of a noise issue during the production of a mixed-mode device dedicated to automotive applications. The research investigations concerned the fact that failure was not detected at test level but at customer level; therefore, it was determinant to understand the root cause of this failure mode to drive corrective actions in order to secure customer. The challenge was to analyse noise in Failure Analysis (FA) without fault spatial localization results. Indeed, Light Emission Microscopy (EMMI) and Thermal Laser Stimulation (ex: Soft Defect Localization – SDL) were unable to provide any defective area in the product. The lack of failing device identification led us to combine electrical and design analyses in order to define hypothesis on the failure origin. It was then possible to drive physical investigations through different approaches, using physical cross-section, Secondary Ion Mass Spectrometry (SIMS) and Scanning Capacitance Microscopy (SCM) techniques. Finally, the obtained complementary results will be discussed and an explanation of the failure mechanism will be presented as the root cause issue, allowing defining the defective step in production process.

Finite element analysis of thermal laser skin stimulation for a finer characterization of the nociceptive system

Thermal laser stimulation of the skin is an efficient exploratory tool to characterize the nociceptive system. In the present study, finite element simulations are done to calculate the intra-cutaneous spatio-temporal temperature profiles following the delivery of such laser stimuli. The proposed computer-aided modeling considers a number of important parameters that have been disregarded in previous approaches: (i) variability of water content across the skin in both hairy and glabrous skin, (ii) temperature dependency of optical and thermal skin parameters, (iii) laser wavelength and corresponding absorption coefficient, (iv) beam shape (Gaussian vs. flat top) and (v) power emission (closed vs. open loop). Numerical simulations allow determining at each instant of time the volume and area of skin tissue whose temperature exceeds a given nociceptor activation threshold. This knowledge allows a finer characterization of the subpopulations of primary afferents that encode and convey nociceptive signals to the central nervous system. As an example, the approach is used to obtain an estimate of intraepidermal nerve fiber density in both physiological and pathological conditions. Moreover, a better knowledge of the heat distribution also reduces the risk of injury to the skin. Finally, in order to make the finite element simulations accessible to investigators with no prior background in numerical analysis, a specific open-source user-interface has been developed with the ONELAB software.

Advanced Dynamic Laser-Stimulation Methods Using Lock-In and Mixed-Frequency Techniques

Abstract A wide range of electrical faults are revealed through thermal laser stimulation (TLS). In principle, an electrical parameter, typically current or voltage, is monitored for changes caused by the heating effects of the laser. Most test setups are designed to limit the activity of the device in order to minimize the signal-to-noise ratio, but in some cases, the fault’s electrical footprint can only be detected when the device is stimulated in a dynamic way. This article describes the setup and implementation of various dynamic TLS methods and presents example applications demonstrating the advantages and limitations of each approach.

A Packaging Solution for Optically Testing Wire-Bonded Chips

In this paper, we describe the design and the experimental characterization of a packaging technique for backside optical testing of chips requiring wirebonding. Optical testing methods, based either on the collection of spontaneous hot-carrier photoemission or on laser stimulation, require an optical access to the active area of the circuit through the backside of the chip, while still providing mechanical support to the thinned die (very fragile), heat sinking capability, power and electrical signals. The proposed package fulfils all these requirements and it can hence be used for picosecond imaging for circuit analysis/time resolved emission measurements, emission microscopy investigations, laser voltage probe, thermal laser stimulation, photoelectric laser stimulation, and other failure analysis methods that require optical access to the transistor level through the silicon backside. The advantages of the new package are its versatility (it can fit different chip sizes), easy handling, low cost, and the fact that it is designed for optical testing and not just for electrical testing. We successfully used the proposed package for optically test chips in advanced complementary metal-oxide-semiconductor technologies (65 nm): measurements at low voltage are possible thanks to the proposed package.

Fast and rigorous use of thermal time constant to characterize back end of the line test structure in advanced technology

Thermal time constant analysis (TTC) opens a wide range of applications: structure identification, 3D localization for very deep micron technologies. In this paper, we describe a new analysis methodology for TTC signatures induced by modulated thermal laser stimulation (TLS). Previous approaches did not allow a fast and rigorous method to acquire and treat transient TLS signals. To overcome these limitations we have done a theoretical study, based on the Fourier transform of an analytical model describing temporal dependency of the TLS signal, which is powerful for signature interpretation. This analysis flow is applied to 65 nm reliability test structure.

Dynamic study of the thermal laser stimulation response on advanced technology structures

Thermal laser stimulation on sub-Micronics interconnection structures is well known. The usual approach is to consider them as a resistor, whatever the structure is. We experimentally showed the weaknesses of this assumption which has to be reconsidered. In this paper we develop a new analytical model based on fine characterization of the dynamic behavior structure heated and cooled. In addition to a better understanding of thermal laser stimulation signature, this modelization opens a wide range of application: structure identification, 3-D localization, etc. It should be a key for failure analysis accuracy and efficiency on Back End Of the Line test structures.

Localization of sensitive areas of power AC switch under thermal laser stimulation

Thermal laser stimulation (TLS) is a widely used tool in a failure analysis laboratory to detect defects in integrated circuits. TLS can also be used for good device characterization. In this paper, we apply TLS – and especially optical beam induced resistance change (OBIRCH) method – to localization of electrically high stressed areas. We test this process with a new product from power AC switch family without failure. We localize several sensitive areas involved during and after switching, which are similar to the ones obtained by electrical simulations.

Localization and physical analysis of a complex SRAM failure in 90nm technology

In this paper the analysis process of a complex SRAM failure in 90nm technology is introduced in detail. Using a correlation method, it could be traced back to a failure with an increased supply current. With the help of MCT emission microscopy and thermal laser stimulation (TLS) the defects were localized at both edges of every failing SRAM block. Further inspection by passive voltage contrast (PVC) and atomic force prober (AFP) current imaging led to a localization down to contact level. In the TEM analysis high angle annular dark field scanning TEM (HAADF STEM) was used to obtain better material contrast. CoSi residues were found at the wall of spacers of the failing FETs. Further surface parallel TEM inspection confirmed the hypothesis of a new type of bridging defect, i.e. CoSi stringers along word lines in SRAM cells, which has not been observed before to our knowledge. The process adjustment in the fab to avoid this failure led to a significant yield improvement. The abstract should be 75-200 words long, summarizing the work and placing it in an appropriate context.

Seebeck Effect Detection on Biased Device without OBIRCH Distortion Using FET Readout

Laser Stimulated Seebeck Effect Imaging (SEI) is widely used in Microelectronics Failure Analysis, namely when performed through chip backside. The SEI signal shapes are often not easy to interpret though, mostly because of superposition of additional OBIRCH (Optical Beam Induced Resistivity Change). Here, a SEI detection technique independent of OBIRCH interference is presented. When a thermoelectric voltage is generated on an interconnect that drives FET inputs (gate conductor), the voltage influences the FET channel conductance almost currentless producing drain output shift that can be detected as Thermal Laser Stimulation (TLS) signal. As FET output current is clearly separate from the gate, it cannot interfere with the thermoelectric effects in the gate conductor. A full characterization of the structure for several circuit models is presented. Test structures for SEI may be improved when designed with FET readout. Also on ICs SEI can be done with nominal supply voltage as long as the Seebeck junction is located in a gate conductor circuit.

Impact of semiconductors material on IR Laser Stimulation signal

In failure analysis laboratory, infrared laser stimulation techniques are more and more used for performing accurate defect localization on IC surface. Signatures obtained on metallic elements are well known, but weak data are available on signatures of semiconductors elements. Our investigations consist of studying impact of semiconductors materials on IR Laser Stimulation signal during a failure analysis. Frontside and backside Thermal Laser Stimulation (TLS) experiments were performed on n+/p+ diffusion and polycrystalline resistors from 0.18 μm technology, both silicided (CoSi 2) and unsilicided. Experimental results are presented and discussed for different W/L ratios. The impact of different semiconductors materials on TLS measurements is discussed and verified by experiment.

Failure analysis of micro-heating elements suspended on thin membranes

We report on the degradation of platinum micro-heating elements operating at high temperatures. Devices with platinum heaters suspended on micro-machined dielectric membranes were self-heated at high temperature until failure. Optical and SEM observations combined with mechanical deformation measurements and Thermal Laser Stimulation techniques were used to analyze the failure mechanisms of the micro-heating elements. Platinum atoms migration and breaking of the membrane were two failure modes observed. At high temperature, the migration of the platinum atoms was linked to the mechanical stress in the dielectric membrane. The Thermal Laser Stimulation technique revealed the formation of vertical as well as lateral thermocouples at mechanically deformed areas. One explanation proposed is that those thermocouples are the result of Si diffusion from the Si 3N 4 membrane into the platinum heater as well as electro-stress migration of platinum atoms.