Thermal Hotspots Research Articles

A Proficient Thermal Based Prediction Unit in Multi Core System

Multi core system has become a popular Execution platform for many Real time systems. The system is continue to shrink down due to thermal hotspots and temperature gradients, which Are significantly impact system parameters like Reliability, performance, cost and leakage power To improve these parameters in Real time systems/ multi core system a Temperature prediction management (TPM) technique is required for mission/safety critical application running on a multi core chip to avoid possible thermal hazards while meeting the application timing constraints. In this paper, we propose an efficient framework for Temperature prediction management (TPM) with time constraint model (Tracker & WDT) in many core systems where the balanced thermal profile can be achieved by proactive task migration among neighboring cores. And based on temperature prediction unit task migration will be performed among neighboring processing elements. Compared with existing proactive task migration technique ,our approach effectively minimize the thermal hotspots, less migration overhead with negligible performance overhead and it increase the processing speed of multi core systems.

A Wavelet-Based Spatio-Temporal Heat Dissipation Model for Reordering of Program Phases to Produce Temperature Extremes in a Chip

Localized heating leads to generation of thermal hotspots that affect the performance and reliability of an integrated circuit (IC). Functional workloads determine the locations and temperatures of hotspots on a die. In this paper, we present a systematic approach for developing a synthetic workload to maximize the temperature of a target hotspot. Our approach is based on the observation that hotspot temperature is determined not only by the current activity in that region, but also by the past activities in the surrounding regions. Accordingly, we develop a wavelet-based canonical spatio-temporal heat dissipation model for program traces, and use a novel integer linear programming formulation to rearrange program phases to generate target worst case hotspot temperature. Program phase behavior is rooted in the static structure of programs. In this case, the initial set of program phases is extracted from the SPEC 2000 benchmark. We apply this formulation to target another well-known problem of maximizing the temperature between a pair of coordinates in an IC. Experimental results show that by taking the spatio-temporal effect into account, we can raise the temperature of a hotspot higher than what is otherwise possible. Hotspot temperature maximization is important in design verification and testing.

Heat dissipation at a graphene–substrate interface

The development of nanoelectronics faces severe challenges from Joule heating, leading to high power density and spatial localization of heat, which nucleates thermal hot spots, limits the maximum current density and potentially causes catastrophic materials failure. Weak interfacial coupling with the substrate is a major route for effective heat mitigation in low-dimensional materials such as graphene and carbon nanotubes. Here we investigate the molecular-scale physics of this process by performing molecular dynamics simulations, and find that significant heating in graphene supported by a silicon carbide substrate cannot be avoided when the areal power density exceeds PG = 0.5 GW m−2. A steady state will be established within 200 ps with a significant temperature difference built up across the interface, and the interfacial thermal conductivity κc increases at higher power densities from 10 to 50 MW m−2 K−1. These observations are explained by a two-resistor model, where strong phonon scattering at the interface may perturb the ballistic heat transport and lead to a diffusive mechanism. Nanoengineering the interfacial thermal coupling by intercalating guest atoms shows potential for designing thermally transparent but electronically insulating interfaces, which paves the way for simultaneously optimizing thermal management and charge carrier mobility in nanoelectronics.

A Multi-Agent Framework for Thermal Aware Task Migration in Many-Core Systems

In deep submicrometer era, thermal hot spots, and large temperature gradients significantly impact system reliability, performance, cost, and leakage power. As the system complexity increases, it is more and more difficult to perform thermal management in a centralized manner because of state explosion and the overhead of monitoring the entire chip. In this paper, we propose a framework for distributed thermal management in many-core systems where balanced thermal profile can be achieved by proactive task migration among neighboring cores. The framework has a low cost agent residing in each core that observes the local workload and temperature and communicates with its nearest neighbor for task migration and exchange. By choosing only those migration requests that will result in balanced workload without generating thermal emergency, the proposed framework maintains workload balance across the system and avoids unnecessary migration. Experimental results show that, our distributed management policy achieves almost the same performance as a global management policy when the tasks are initially randomly distributed. Compared with existing proactive task migration technique, our approach generates less hotspot, less migration overhead with negligible performance overhead.

Quantifying Architectural Impact of Liquid Cooling for 3D Multi-Core Processors

For future multi-core processors, 3D integration is regarded as one of the most promising techniques since it improves performance and reduces power consumption by decreasing global wire length. However, 3D integration causes serious thermal problems since the closer proximity of heat generating dies makes existing thermal hotspots more severe. Conventional air cooling schemes are not enough for 3D multi-core processors due to the limit of the heat dissipation capability. Without more efficient cooling methods such as liquid cooling, the performance of 3D multi-core processors should be degraded by dynamic thermal management. In this paper, we examine the architectural impact of cooling methods on the 3D multi-core processor to find potential benefits of liquid cooling. We first investigate the thermal behavior and compare the performance of two different cooling schemes. We also evaluate the leakage power consumption and lifetime reliability depending on the temperature in the 3D multi-core processor.

Real-time implementation of remotely sensed hyperspectral image unmixing on GPUs

Spectral unmixing is one of the most popular techniques to analyze remotely sensed hyperspectral images. It generally comprises three stages: (1) reduction of the dimensionality of the original image to a proper subspace; (2) automatic identification of pure spectral signatures (called endmembers); and (3) estimation of the fractional abundance of each endmember in each pixel of the scene. The spectral unmixing process allows sub-pixel analysis of hyperspectral images, but can be computationally expensive due to the high dimensionality of the data. In this paper, we develop the first real-time implementation of a full spectral unmixing chain in commodity graphics processing units (GPUs). These hardware accelerators offer a source of computational power that is very appealing in hyperspectral remote sensing applications, mainly due to their low cost and adaptivity to on-board processing scenarios. The implementation has been developed using the compute device unified architecture (CUDA) and tested on an NVidia™ GTX 580 GPU, achieving real-time unmixing performance in two different case studies: (1) characterization of thermal hot spots in hyperspectral images collected by NASA's Airborne Visible Infra-red Imaging Spectrometer (AVIRIS) during the terrorist attack to the World Trade Center complex in New York City, and (2) sub-pixel mapping of minerals in AVIRIS hyperspectral data collected over the Cuprite mining district in Nevada.

Design of Test Structures for the Characterization of Thermal–Mechanical Stress in 3D-Stacked IC

In this paper, we present test structures and measurement techniques that enable the extraction of the significance of the thermal–mechanical stress in 3D-stacked integrated circuit technology. Heaters and integrated diodes have been used to determine the impact of hotspots in 3-D systems. The results obtained showed that in 3-D case, the peak temperature of a hotspot is three times higher compared to a traditional 2-D system. For the characterization of through silicon vias (TSVs)-induced stress and its impact on analog metal-oxide semiconductor (MOS) devices, a 10-bit current steering digital-to-analog converter (DAC) test structure is utilized. The DAC has been optimized to detect ion changes down to 0.5% due to TSV proximity, TSV orientation, thermal hotspots, and wafer thinning or stacking process. The results obtained from stand-alone short-channel MOS devices and the DAC structure clearly indicate the impact of TSV proximity and TSV orientation on the carrier mobility of nearby transistors.

The Need for Power Debugging in the Multi-Core Environment

Debugging an application for power has a wide array of benefits ranging from minimizing the thermal hotspots to reducing the likelihood of CPU malfunction. In this work, we justify the need for power debugging, and show that performance debugging of a parallel application does not automatically guarantee power balance across multiple cores. We perform experiments and show our results using two case study benchmarks, Volrend from Splash-2 and Bodytrack from Parsec-1.0.

Characterizing Vulnerability of Network Interfaces in Embedded Chip Multiprocessors

In Networks-on-Chip (NoC), with ever-increasing design complexity and technology scaling, soft errors have become a key design challenge. In this work, we extend the concept of architectural vulnerability factor (AVF) from the microprocessor domain and propose a network vulnerability factor (NVF) to characterize the susceptibility of Network Interfaces (NIs) to soft errors. For the first time, a detailed characterization of vulnerability is performed on a state-of-the-art AXI-based NI architecture using full system simulation. Our studies reveal that different NI buffers behave quite differently in the presence of transient faults and each buffer can have different inherent tolerance to faults. Our analysis also considers the impact of thermal hotspot mitigation techniques on the NVF estimation.

Low-cost sensing with ring oscillator arrays for healthier reconfigurable systems

Electronic systems on a chip increasingly suffer from component variation, voltage noise, thermal hotspots, and other subtle physical phenomena. Systems with reconfigurability have unique opportunities for adapting to such effects. Required, however, are low-cost, fine-grained methods for sensing physical parameters. This article presents powerful, novel approaches to online sensing, including methods for designing compact reconfigurable sensors, low-cost threshold detection, and several enhanced measurement procedures. Together, the approaches help enable systems to autonomously uncover a wealth of physical information. A highly efficient counter and improved ring oscillator are introduced, enabling an entire sensor node in just 8 Virtex-5 LUTs. We describe how variations can be measured in delay, temperature, switching-induced IR drop, and leakage-induced IR drop. We demonstrate the proposed approach with an experimental system based on a Virtex-5, instrumented with over 100 sensors at an overhead of only 1.3%. Results from thermally controlled experiments provide some surprising insights and illustrate the utility of the approach. Online sensing can help open the door to physically adaptive computing, including fine-grained power, reliability, and health management schemes for systems on a chip.

Power profiling-guided floorplanner for 3D multi-processor systems-on-chip

Three-dimensional (3D) integration has become one of the most promising techniques for the development of future multi-core processors, since it improves performance and reduces power consumption by decreasing global wire length. However, 3D integration causes serious thermal problems because the closer proximity of heat generating dies makes existing thermal hotspots more severe. Thermal-aware floorplanners can play an important role to improve the thermal profile, but they have failed in considering the dynamic power profiles of the applications. This study proposes a novel thermal-aware floorplanner guided by the power profiling of a set of benchmarks that are representative of the application scope. The results show how our approach outperforms the thermal metrics as compared with the worst-case scenario usually considered in ‘traditional’ thermal-aware floorplanners.

Validating theoretical simulations of thermal emission hot spot effects on maize canopies

This is a development of some of our previous work on the analysis of thermal emission hot spot effects. In that work, which was a simulation study, a curve-fitting model was proposed to derive the hot spot amplitude and half width. Based on the curve-fitting model, a new algorithm that predicts the component temperature differences from the hot spot amplitude is presented. In this study, the objectives are to evaluate the accuracy of the curve-fitting model and the new prediction algorithm using both airborne measurements based on the wide-angle infrared dual-mode line/area array scanner (WiDAS) system and ground measurements. Based on a prior knowledge of crop structure parameters (e.g. the leaf area index (LAI), leaf angle distribution (LAD) and leaf dimensions), validation results indicate that the curve-fitting model and the prediction algorithm can accurately retrieve the hot spot amplitude and half width (R 2 > 0.90 and root mean square error (RMSE) < 0.15 K), and predict leaf and soil temperature differences from directional signals of both airborne and ground data (bias < 1 K). The error of prior knowledge can significantly affect the prediction accuracy of leaf temperature difference. Also discussed are the limitations of the model and future research and application.

Remotely sensed ammonia emission from fumarolic vents associated with a hydrothermally active fault in the Salton Sea Geothermal Field, California

[1] Airborne hyperspectral imaging surveys were conducted over a geothermally active region straddling the southeastern shore of the Salton Sea in Southern California. The imagery was acquired across the 7.6–13.5 μm longwave-infrared region with a ground sample distance of approximately 1 m. Prominent thermal hot spots associated with fumaroles along a known fault line were observed to coincide with emission of free ammonia, presumed to originate from geothermally induced pyrolytic decomposition of nitrogenous compounds that permeate the lake water, sediment, and adjacent agricultural terrain. It is shown that the inferred fluxes of ammonia constitute a significant fraction (10–25%) of the total atmospheric ammonia burden assessed for the Salton Sea environs and represent a previously unreported source for that locale.

3D Electro-thermal modelling of bonding and metallization ageing effects for reliability improvement of power MOSFETs

This paper presents a methodology, based on 3D electro-thermal simulation, to investigate failures of vertical power MOSFET due to metallization ageing of source terminal. Modelling steps to obtain a 3D finite element modelling of MOSFET are presented with the smart approximations and limitations of MOSFET electrical behaviour. The effects of bonding wire gauge and contact area with top metallization are studied to optimize the power device design. The power device thermal runaway phenomenon and hot spot formation has been simulated and discussed.

An investigation of methods for injecting emissions from boreal wildfires using WRF-Chem during ARCTAS

Abstract. The Weather Research and Forecasting Model (WRF) is considered a "next generation" mesoscale meteorology model. The inclusion of a chemistry module (WRF-Chem) allows transport simulations of chemical and aerosol species such as those observed during NASA's Arctic Research of the Composition of the Troposphere from Aircraft and Satellites (ARCTAS) in 2008. The ARCTAS summer deployment phase during June and July coincided with large boreal wildfires in Saskatchewan and Eastern Russia. One of the most important aspects of simulating wildfire plume transport is the height at which emissions are injected. WRF-Chem contains an integrated one-dimensional plume rise model to determine the appropriate injection layer. The plume rise model accounts for thermal buoyancy associated with fires and local atmospheric stability. This paper describes a case study of a 10 day period during the Spring phase of ARCTAS. It compares results from the plume model against those of two more traditional injection methods: Injecting within the planetary boundary layer, and in a layer 3–5 km above ground level. Fire locations are satellite derived from the GOES Wildfire Automated Biomass Burning Algorithm (WF_ABBA) and the MODIS thermal hotspot detection. Two methods for preprocessing these fire data are compared: The prep_chem_sources method included with WRF-Chem, and the Naval Research Laboratory's Fire Locating and Monitoring of Burning Emissions (FLAMBE). Results from the simulations are compared with satellite-derived products from the AIRS, MISR and CALIOP sensors. When FLAMBE provides input to the 1-D plume rise model, the resulting injection heights exhibit the best agreement with satellite-observed injection heights. The FLAMBE-derived heights are more realistic than those utilizing prep_chem_sources. Conversely, when the planetary boundary layer or the 3–5 km a.g.l. layer were filled with emissions, the resulting injection heights exhibit less agreement with observed plume heights. Results indicate that differences in injection heights produce different transport pathways. These differences are especially pronounced in area of strong vertical wind shear and when the integration period is long.

Fighting fire with fire

Local thermal hot-spots in microprocessors lead to worst-case provisioning of global cooling resources, especially in large-scale systems where cooling power can be 50~100% of IT power. Further, the efficiency of cooling solutions degrade non-linearly with supply temperature. Recent advances in active cooling techniques have shown on-chip thermoelectric coolers (TECs) to be very efficient at selectively eliminating small hot-spots. Applying current to a superlattice TEC-film that is deposited between silicon and the heat spreader results in a Peltier effect, which spreads the heat and lowers the temperature of the hot-spot significantly and improves chip reliability . In this paper, we propose that hot-spot mitigation using thermoelectric coolers can be used as a power management mechanism to allow global coolers to be provisioned for a better worst case temperature leading to substantial savings in cooling power. In order to quantify the potential power savings from using TECs in data center servers, we present a detailed power model that integrates on-chip dynamic and leakage power sour-ces, heat diffusion through the entire chip, TEC and global cooler efficiencies, and all their mutual interactions. Our multi-scale analysis shows that, for a typical data center, TECs allow global coolers to operate at higher temperatures without degrading chip lifetime, and thus save ~27% cooling power on average while providing the same processor reliability as a data center running at 288K.

Thermal and Power Characterization of Real Computing Devices

Power and temperature are key design concerns in modern computing systems. Power minimization is essential for battery-operated devices and for large-scale data center facilities. The spatial and temporal allocation of within-die power consumption lead to thermal gradients and hot spots during operation. Temperature impacts key circuit metrics such as reliability, speed, and leakage power, and it is a major constraint towards improving the performance of high-end computing devices. Due to the enormous complexities and sheer number of modeling parameters of state-of-the-art designs, pre-silicon power and thermal models cannot be trusted blindly. It is necessary to complement pre-silicon analysis with post-silicon thermal and power characterization on the fabricated devices, and then to use the characterization results to improve the design during re-spins before ramp and production. In this paper, we describe new techniques for thermal and power characterization of real computing devices. We show how the measurements from infrared imaging, embedded thermal sensors, and current meters can be integrated to accurately characterize the temperatures and power of computing devices during operation. We describe the key algorithmic and experimental techniques required to overcome the challenges encountered when working with real devices. We present characterization results of a dual-core processor and a programmable logic device.

Thermal Hot Spot and Corrosion Damage in Conical Pressure Components

Abstract Structural integrity of an in-service component containing damage such as corrosion and thermal hot spot has to be evaluated regularly so as to certify the acceptance and safety of continued service of the component. In this paper, limit load solutions of a damaged conical shell, particularly local wall thinning and thermal hot spot, is investigated. The derived solutions are based on identifying the regions in the damaged component that directly participate in the plastic action (kinematically active). The concepts of reference volume and decay length are employed to identify the kinematically active regions in the damaged conical shell. The different solutions proposed in this paper are compared with the elastic-plastic finite element analysis. The results indicate that proposed solutions can be used with acceptable accuracy to make integrity assessment decisions.

Fast anomaly detection in hyperspectral images with RX method on heterogeneous clusters

Remotely sensed hyperspectral sensors provide image data containing rich information in both the spatial and the spectral domain, and this information can be used to address detection tasks in many applications. One of the most widely used and successful algorithms for anomaly detection in hyperspectral images is the RX algorithm. Despite its wide acceptance and high computational complexity when applied to real hyperspectral scenes, few approaches have been developed for parallel implementation of this algorithm. In this paper, we evaluate the suitability of using a hybrid parallel implementation with a high-dimensional hyperspectral scene. A general strategy to automatically map parallel hybrid anomaly detection algorithms for hyperspectral image analysis has been developed. Parallel RX has been tested on an heterogeneous cluster using this routine. The considered approach is quantitatively evaluated using hyperspectral data collected by the NASA’s Airborne Visible Infra-Red Imaging Spectrometer system over the World Trade Center in New York, 5 days after the terrorist attacks. The numerical effectiveness of the algorithms is evaluated by means of their capacity to automatically detect the thermal hot spot of fires (anomalies). The speedups achieved show that a cluster of multi-core nodes can highly accelerate the RX algorithm.

A Multi-Processing Systems-on-Chip Native Simulation Framework for Power and Thermal-Aware Design

The continuous advance in technology enables the design of more complex embedded systems making use of increasingly powerful Multi-Processing Systems-on-Chip. These new systems can be used in new applications that require increasing performance with lower cost and power consumption and higher reliability. Finding the right compromise among these contradictory constraints makes initial architectural design decisions crucial as they may compromise the quality of the final implementation. In Multi-Processing Systems-on-Chip design, the analysis of chip temperature is becoming increasingly important due to its impact on system reliability, power consumption and cost. In this paper, we propose a complete framework based on native simulation for early estimation of power consumption and thermal flow in Multi-Processing Systems-on-Chip. Native simulation enables fast modeling and simulation of the embedded software running on a specific platform in close interaction with all the platform components. The activity of each component is monitored by using high-level models, which enable the estimation of the power consumed. The power figures feed a high-level Multi-Processing Systems-on-Chip thermal model which supplies chip temperature estimations. At the same time, advanced techniques to manage power and temperature have been modeled. Thus, the proposed framework enables the detection of power and thermal hot spots in the first stages of the design flow, allowing the exploration of different alternatives to address these problems. The framework has been validated by comparing the results provided with an Instruction Set Simulator. The results show around 2% error in the estimations, while simulation time is speeded up three orders of magnitude. Different examples have been developed to demonstrate the capabilities of the proposed methodology in a variety of cases.