This paper presents extremely‐low leakage technologies in low‐temperature polysilicon (LTPS) TFTs. Experimental and physics‐based analysis of leakage currents, emphasizing the effects of process technologies and device design, are described. Small‐geometry TFTs, controlled by optimal LTPS process, dramatically reduce off‐state leakage current (Ioff) by suppressing gate‐induced drain leakage (GIDL) and thermal generation currents, thus potentially offering lower frame rate operations by reducing IC clock power. Numerical device simulations, supplemented by physics‐based analysis, are performed to corroborate the remarkable low‐Ioff experimental results as well as more‐than‐twice enhanced on‐state current (Ion) in optimized LTPS devices.
Read full abstract