In this study, we explore the capacitance C(V) characteristics of metal/polysilicon/silicon oxide/monosilicon (MSPOS) structures. The obtained C(V) curves allow us to analyze the behavior of the capacitance at high frequency as well as the effect of thermal annealing on these characteristics. These reveal particular characteristics of MOS and MOSP structures. The study shows that, under different bias voltages, the obtained curves differ depending on whether the bias is positive or negative. When applying positive voltages, we observe a certain configuration of the curves, while with negative voltages, another configuration appears, always indicating a combination of the C(V) characteristics specific to MOS and MOSP structures. For a substrate doped at a concentration ND = 2.1018 cm-3, we observed a significant variation of the capacitance under the effect of thermal annealing. This thermal treatment, by modifying the crystalline structure of polysilicon, allows the modification of the MOS capacitance. It influences in particular the growth of polysilicon grains as well as the grain boundaries. The results of this study highlight the effect of thermal annealing on polysilicon-based MOS structures. These observations highlight the effect of thermal annealing on the properties of MSPOS structures, by providing a detailed view of how bias voltages and thermal treatment interact to modulate the capacitance characteristics.
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