TFT Devices Research Articles

P‐28: Study on One Infrequent Influencing Factor of TFT‐LCD Life

AbstractThrough a lot of analysis and test on a rare failure (ongoing black mura), we found that the distance of TFT U shaped channel to the gate line edge have great influence on the stability of TFT device. When the distance is less than a critical value, the characterization of TFTs would degrade after a long‐time of stress or aging, lead to decrease of Ion and increase of Vth, resulting in poor life time of TFT‐LCD for the abnormal black phenomenon. By BTPS(Bias, Temperature, Photo, Stress) [1‐2] and aging test, we compare the stability of TFTs with different distance value, establish calculation model and design spec. Effective improvement have achieved by process adjusting and design changes.

Sputtered oxides used for passivation layers of amorphous InGaZnO thin film transistors

Four sputtered oxide films (SiO2, Al2O3, Y2O3 and TiO2) along with their passivating amorphous InGaZnO thin film transistors (a-IGZO TFTs) were comparatively studied in this paper. The device passivated by an Al2O3 thin film showed both satisfactory performance (μFE=5.3cm2/Vs, Ion/Ioff>107) and stability, as was probably related to smooth surface of Al2O3 thin films. Although the performance of the a-IGZO TFTs with a TiO2 passivation layer was also good enough (μFE=3.5cm2/Vs, Ion/Ioff>107), apparent Vth shift occurred in positive bias-stress tests due to the abnormal interface state between IGZO and TiO2 thin films. Sputtered Y2O3 was proved no potential for passivation layers of a-IGZO TFTs in this study. Despite unsatisfactory performance of the corresponding a-IGZO TFT devices, sputtered SiO2 passivation layer might still be preferred for its high deposition rate and excellent transparency which benefit the mass production of flat panel displays, especially active-matrix liquid crystal displays.

Magnetron-Sputtered SnO Thin Films for p-Type and Ambipolar TFT Applications

SnOx films were fabricated by reactive rf magnetron sputtering under various oxygen partial pressures (PO = 1.6%–50%) and then annealed in an air ambient. Four operating window regions of the SnOx films are demonstrated such as metallic Sn dominated films with n-type conduction, polycrystalline SnO dominated films with p-type conduction, SnO-SnO2 composite films with high resistivity, and amorphous SnO2 dominated films with n-type characteristics. TFT devices using the SnO dominated films as channels are investigated. The TFTs with the channels of a hole concentration over 1018 cm−3 show depletion p-type characteristics. The hole concentration can be tunable by changing PO, the channel thickness, and the annealing durations. An ambipolar operating mode is obtained by modulating the hole concentration.

电极材料对IGZO薄膜晶体管性能的影响

Indium gallium zinc oxide thin film transistors(IGZO-TFTs) with bottom-gate top structure were fabricated on n-type silicon substrates using radio frequency(RF) magnetron sputtering method.Three kinds of metal material such as Au,Cu,and Al were used to fabricate electrode,respectively,and the effects of different electrode materials on IGZO TFT performance were investigated. The output characteristic and transfer characteristic of the TFT devices were tested. The best performance was obtained when Au was used to fabricate electrode,its saturation output current was 17. 9 μA,and on-off current ratio was up to 1. 4 ×106. In addition,the contact characteristics between three kinds of electrodes and IGZO thin film were analyzed based on their work function. Au electrode had the smallest contact resistance of these three metal according to the TLM(transmission line model) theory.

Structural properties and electrical characteristics of Ho2O3 and HoTixOy gate dielectrics for a-InGaZnO thin-film transistors

Transfer and output characteristics of high-κ Ho2O3 and HoTixOy a-IGZO TFT devices.

Integrated circuits using fully solution-processed organic TFT devices with printed silver electrodes

We have demonstrated fully solution-processed inverter, NAND and NOR circuits using pseudo-CMOS logic and p-type organic TFT devices with printed electrodes that were fabricated using ink-jet printed silver nanoparticle inks at low temperatures. In order to optimize the gate electrode profiles, we thoroughly assessed the surface wettability of the silver nanoparticle inks. The pseudo-CMOS inverter circuit exhibited exceptional switching characteristics with a high signal gain of 34 at a supply voltage of 20V. The NAND and NOR circuits also exhibited excellent logic characteristics, whereby the switching voltage was approximately VDD/2 with a high noise margin and short delay time of 12.5ms.

Modulation of carrier mobility of diketopyrrolopyrrole and quaterthiophene containing copolymer with self-assembled monolayers on gate dielectrics of thin film transistors

We fabricated organic thin-film transistors (OTFTs) using diketopyrrolopyrrole (DPP) and quaterthiophene (QT) containing a conjugated polymer, poly[2,5-bis(2-octyldodecyl)pyrrolo[3,4-c]pyrrole-1,4(2H,5H)-dione-alt-2,2′:5′,2″:5″,2‴-quaterthiophene] (P(DPP-alt-QT)), as an active layer, with chemically modified SiO2 gate dielectrics. The effect of the surface treatment of SiO2 with alkyltrichlorosilanes on the electric characteristics of P(DPP-alt-QT) was investigated. The self-assembled monolayers (SAMs) were elaborated with n-octyltrichlorosilane (OTS) and n-octadecyltrichlorosilane (ODTS) on the SiO2 surface.After the treatment with SAM, the contact angles and surface free energy of the dielectric layers were measured to study the variation in the surface properties. Using a high-performance P(DPP-alt-QT) polymer, we fabricated thin-film transistor devices with the following dielectric layers: bare SiO2/Si, OTS-SiO2/Si, and ODTS-SiO2/Si. In the electrical measurements, typical I–V characteristics of TFTs were observed. The values of best field-effect mobility, μ, were 1.13 and 3.46cm2V−1s−1 for P(DPP-alt-QT)-based TFTs containing OTS- and ODTS-treated SiO2 dielectric layers, respectively. The ODTS-treated TFT device with the lowest dielectric surface free energy exhibited the highest mobility among the three devices constructed using three different dielectric layers.

Electrical Performance Enhancement of Al–Zn-Sn–O Thin Film Transistor by Supercritical Fluid Treatment

In this letter, a low-temperature supercritical fluid (SCF) treatment was employed to enhance the electrical and optical properties of amorphous Al-Zn-Sn-O thin film transistors (a-AZTO TFTs) for flat-panel displays. The carrier mobility and threshold voltage of a-AZTO TFT were improved significantly after SCF process because of the reduction of trap density in the a-AZTO active layer. In addition, the SCF-treated a-AZTO TFT exhibited superior electrical reliability and less degradation after negative gate bias illumination stress. X-ray photoelectron spectroscopy analysis confirmed that the proposed SCF treatment could effectively oxidize a-AZTO film and change the oxidation states of Sn, resulting in the improvement of a-AZTO TFT device characteristics.

Investigation on plasma treatment for transparent Al–Zn–Sn–O thin film transistor application

This work reported the physical characteristics and electrical performance of amorphous Al–Zn–Sn–O thin film transistor (a-AZTO TFT) device under the temperature effects of thermal annealing process and various gas plasma post-treatments. The thermal annealing at 450°C could strengthen the oxygen bonding of a-AZTO film, thereby improving the film quality and TFT device performance. In addition, the oxygen deficient can be reduced effectively by the O2 and N2O plasma treatments, respectively, leading to enhanced electrical reliability. Also, the optical energy gap of a-AZTO films with O2 or N2O plasma treatment was measured about 3.5eV, which indicated that all of the a-AZTO films were insensitive to visible light. On the other hand, the electron mobility of a-AZTO TFT was observed to be promoted after NH3 plasma post-treatment. The improvement could be attributed to a slight doping effect of H+ ions. These results showed the potential of post-treatments for flat panel displays applications of transparent a-AZTO TFT technology.

P.3: 3‐D Stacked Complementary TFT Devices using n‐type α‐IGZO and p‐type F8T2 TFTs — Operation Confirmation of NOT and NAND Logic Circuits –

AbstractWe have developed 3‐D stacked complementary TFT devices using n‐type α‐IGZO and p‐type F8T2 TFTs on PET substrates. We confirmed proper I‐V characteristics of both the α‐IGZO and F8T2 TFTs and correct input‐output characteristics of both NOT and NAND logic circuits. The operation confirmation of the NAND logic circuit suggests that any advanced logic circuit can be composed using these complementary TFT devices.

Structural and electrical characteristics of high-κ ErTixOy gate dielectrics on InGaZnO thin-film transistors

In this paper, we investigated the structural properties and electrical characteristics of high-κ ErTixOy gate dielectrics on indium-gallium-zinc oxide thin-film transistors (IGZO TFTs). We used X-ray diffraction, X-ray photoelectron spectroscopy, and atomic force microscopy to investigate the structural and morphological features of these dielectric films after they had been subjected to annealing at various temperatures. The high-κ ErTixOy IGZO TFT device annealed at 400°C exhibited better electrical characteristics in terms of a large field-effect mobility (8.24cm2/V-s), low threshold voltage (0.36V), small subthreshold swing (130mV/dec), and high Ion/off ratio(3.73×106). These results are attributed to the reduction of the trap states and oxygen vacancies between the ErTixOy film and IGZO active layer interface during high-temperature annealing in oxygen ambient. The reliability of voltage stress also can be improved by the oxygen annealing at 400°C.

Two-step Electrical Degradation Behavior in α-InGaZnO Thin-film Transistor Under Gate-bias Stress

Investigated transfer characteristics on threshold voltage instability behavior in amorphous indium-gallium-zinc oxide thin-film transistor (α-IGZO TFT). A two-step electrical degradation behavior of α-IGZO TFT was found under gate-bias stress. A usual small positive shift followed by a special negative shift of threshold voltage is characterized in the α-IGZO TFT device. We suggest that the positive shift of the threshold voltage is due to the charge trapping in the gate dielectric and/or at the channel/dielectric interface, while the negative shift of threshold voltage is assigned to electric field-induced extra electron carriers from H2O molecules in the back channel protective layer. We conclude that the H2O molecules and the quality of passivation layer affect the degradation behavior of α-IGZO TFT devices.

Patterning Method for Silver Nanoparticle Electrodes in Fully Solution-Processed Organic Thin-Film Transistors Using Selectively Treated Hydrophilic and Hydrophobic Surfaces

Fully solution-processed organic thin-film transistor (OTFT) devices have been fabricated with simple patterning process at a relatively low process temperature of 100 °C. In the patterning process, a hydrophobic amorphous fluoropolymer material, which was used as the gate dielectric layer and the underlying base layer, was treated with an oxygen plasma to selectively change its surface wetting properties from hydrophobic to hydrophilic. Silver source and drain electrodes were successfully formed in the treated areas with highly uniform line widths and without residues between the electrodes. Nonuniformities in the thickness of the silver electrodes originating from the “coffee-ring” effect were suppressed by optimizing the blend of solvents used with the silver nanoparticles, such that the printed electrodes are appropriate for bottom-gate OTFT devices. A fully solution-processed OTFT device using a polymer semiconductor material (PB16TTT) exhibited good electrical performance with no hysteresis in its transfer characteristics and with good linearity in its output characteristics. A relatively high carrier mobility of 0.14 cm2 V-1 s-1 and an on/off ratio of 1×105 were obtained with the fabricated TFT device.

Characterization of the p-type Sn1−x Mn x O2 oxide semiconductor nanoparticles by Sol-Gel method

This paper reports the properties of p-type oxide semiconductor Sn1−x Mn x O2 (MTO) nanoparticles with a low doping concentration of Mn (0 ≤ x ≤ 0.05) prepared with a sol-gel method. X-ray diffraction (XRD) results show that single-phase rutile MTO was obtained for x up to 0.03. The samples have particle average size of about 100 nm, which was confirmed with scanning electron microscopy (SEM) and high-resolution transmission electron microscopy (HRTEM). The compositional changes and electrical properties of the MTO nanoparticles were characterized by using x-ray photoelectron spectroscopy (XPS) and Hall effect measurements. Mn3+ cations are incorporated into the rutile SnO2 lattice. P-type conduction which is arisen from the substitution of Mn3+ to Sn4+ lattice was demonstrate by Hall data. These compositions have hole carrier concentrations in the range 2.26∼8.53 × 1016 cm−3 and exhibit Hall mobilities in the range 0.8∼4.1 cm2/Vs. The mobility of MTO decreases as the Mn content increases due to the doping effect. A transparent, ptype TFT device can be fabricated with this composition.

High performance IGZO/TiO2 thin film transistors using Y2O3 buffer layers on polycarbonate substrate

In this work, we fabricate IGZO TFT devices on flexible substrate at room temperature. The IGZO/TiO2 TFT has small subthreshold swing of 0.16 V/dec, but suffers large gate leakage and negative threshold voltage. However, the TiO2 TFT with Y2O3 buffer layers shows improved characteristics including a low threshold voltage of 0.55 V, a small sub-threshold swing of 0.175 V/decade and high field-effect mobility of 43 cm2/Vs. Such good performance can be attributed to the enhanced capacitance density and lowered gate leakage owing to the integration of large band gap Y2O3 and low-temperature higher-κ TiO2.

Dependence of annealing on stability of transparent amorphous InGaZnO thin film transistor

Bottom-gate transparent IGZO–TFT had been successfully fabricated at relatively low temperature (200°C). The devices annealing for 4h at 200°C exhibit good electrical properties with saturation mobility of 8.2cm2V−1s−1, subthreshold swing of 1.0V/dec and on/off current ratio of 5×106. The results revealed that the stability of TFT devices can be improved remarkably by post-annealing treatment. After applying positive gate bias stress of 20V for 5000s, the device annealing for 1h shows a larger positive Vth shift of 4.7V. However, the device annealing for 4h exhibits a much smaller Vth shift of 0.04V and more stable.

Self-stratified semiconductor/dielectric polymer blends: vertical phase separation for facile fabrication of organic transistors

Semiconducting/insulating polymer blends are promising materials for use in organic thin film transistor (OTFT) applications. Here, vertically phase-separated poly(3-hexylthiophene) (P3HT)-top and poly(methyl methacrylate) (PMMA)-bottom blend films were developed for the facile fabrication of OTFTs with excellent electrical properties. The microstructures of the blend films could be adjusted simply by altering the film processing conditions, which impacted the electrical properties of the OTFTs based on the blend films. A decrease in the P3HT content of the blend film significantly reduced the interface roughness between the semiconductor (P3HT) and dielectric (PMMA) layers, which reduced charge trapping or scattering, thereby increasing the field-effect mobility. A higher solution concentration tended to increase the drying time during film deposition, which allowed the P3HT molecules to self-organize over a long period of time. This led to an increase in the ordering of the phase-separated P3HT film, which significantly improved the device performance. TFTs based on a P3HT/PMMA (1/39 w/w) film prepared from a 4 wt% blend solution showed the best field-effect performance with a saturated field-effect mobility of 0.022 cm2 V−1 s−1 and an Ion/Ioff current ratio of 2 × 105. The vertically stratified P3HT/PMMA films were also suitable for the fabrication of all-polymer TFT devices on flexible substrates.

4,4′-Di(pyren-1-yl)-1,1′-biphenyl as an efficient material for organic light-emitting diodes and thin-film transistors

We report an efficient and thermally stable material (4,4′-di(pyren-1-yl)-1,1′-biphenyl, DBP) for use as a deep-blue-emitting layer in organic light-emitting diodes (OLEDs) as well as an active channel layer in organic thin-film transistors (OTFTs). An OLED device doped with 3% DBP exhibited pure blue fluorescence emission at 460 nm with a current efficiency of 3.9 cd A−1 at Commission Internationale de l'Eclairage (CIE) coordinates of (0.15, 0.13). Furthermore, the DBP-based thin film grown on the octadecyltrichlorosilane (OTS)-treated SiO2/Si substrate at 19 °C exhibited p-type hole-transport behavior in a TFT device configuration, with a field-effect mobility (μFET) of 0.21 cm2 V−1 s−1.

Reliability Analysis of Symmetric Vertical-Channel Nickel-Salicided Poly-Si Thin-Film Transistors

In this paper, a reliability analysis of symmetric Vertical-channel Ni-SAlicided poly-Si thin-film transistors (VSA-TFTs) is performed for the first time. First, we compare the drain-induced barrier-lowering effect (DIBL) of VSA-TFTs. The VSA-TFTs with thinner gate oxide thickness, an offset structure, and a longer floating n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> region have better immunity to DIBL. Second, VSA-TFTs with a longer floating n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> region also have better immunity under hot-carrier (HC) stress and self-heating (SH) stress. However, VSA-TFTs with a shorter floating n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> region also have better immunity to positive gate bias (PGB) stress. Consequently, in order to optimize reliability characteristics, including SH stress, HC stress, and PGB stress, it is necessary to modulate the length of the floating n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> region. Third, the PGB stress, rather than SH stress or HC stress, becomes a major issue for VSA-TFTs under the stress bias below 4 V. In other words, PGB stress will dominate the degradation behaviors when the stress bias is not high enough to achieve SH stress and HC stress. Finally, the worst degradation condition of VSA-TFTs under HC stress, similar to that of most TFT devices, occurs when the stress of V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> is less than half of V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> .

Inspection of the TFT Devices Using the Low-Energy Electron Beam Emitted from the Microcolumn

The inspection of the TFT device for the LCD panel has been usually carried out by the large-scale electron column where the kinetic energy of the electron beam is higher than 10 kV, which has many disadvantages for the inspection. In this work, we replaced the bulky electron column with a tiny microcolumn and carried out the inspection of the TFT device. The result shows that the low-energy e-beam inspection can clearly observe the physical defects of the devices and also identify the abnormal electrical behavior caused by the defects in the device.