Estimation Of Testability Research Articles

Off-axis conics as base surfaces for freeform optics enable null testability.

When conducting interferometric tests of freeform optical surfaces, additional optical components, such as computer-generated holograms or deformable mirrors, are often necessary to achieve a null or quasi-null. These additional optical components increase both the cost and the difficulty of interferometric tests of freeform optical surfaces. In this paper, designs using off-axis segments of conics as base surfaces for freeforms are explored. These off-axis conics are more complex base surfaces than typically-used base spheres but remain null-testable. By leveraging off-axis conics in conjunction with additional orthogonal polynomial departures, designs were found with up to an order-of-magnitude of improvement in testability estimates relative to designs that use base spheres. Two design studies, a three-mirror telescope and a wide field-of-view four-mirror telescope, demonstrate the impact of using off-axis conics as the base surface.

Testability Measurement Model for Object Oriented Design (Tmmood)

Measuring testability early in the development life cycle especially at design phase is a criterion of crucial importance to software designers, developers, quality controllers and practitioners. However, most of the mechanism available for testability measurement may be used in the later phases of development life cycle. Early estimation of testability, absolutely at design phase helps designers to improve their designs before the coding starts. Practitioners regularly advocate that testability should be planned early in design phase. Testability measurement early in design phase is greatly emphasized in this study; hence, considered significant for the delivery of quality software. As a result, it extensively reduces rework during and after implementation, as well as facilitate for design effective test plans, better project and resource planning in a practical manner, with a focus on the design phase. An effort has been put forth in this paper to recognize the key factors contributing in testability measurement at design phase. Additionally, testability measurement model is developed to quantify software testability at design phase. Furthermore, the relationship of Testability with these factors has been tested and justified with the help of statistical measures. The developed model has been validated using experimental tryout. Finally, it incorporates the empirical validation of the testability measurement model as the author’s most important contribution.

Metric Based Testability Estimation Model for Object Oriented Design: Quality Perspective

The quality factor of class diagram is critical because it has significant influence on overall quality of the product, delivered finally. Testability has been recognized as a key factor to software quality. Estimating testability at design stage is a criterion of crucial significance for software designers to make the design more testable. Taking view of this fact, this paper identifies testability factors namely effectiveness and reusability and establishes the correlation among testability, effectiveness and reusability and justifies the correlation with the help of statistical measures. Moreover study developed metric based testability estimation model and developed model has been validated using experimental test. Subsequently, research integrates the empirical validation of the developed model for high level acceptance. Finally a hypothesis test performs by the two standards to test the significance of correlation.

Design of a Probabilistic Based Software Tool for Evaluating Controllability, Observability and Testability Models of Digital Systems

This paper presents a probabilistic based software tool for estimation of digital systems' testability. The tool allows fast computation to estimate testability in linear time complexity regarding the number of components and interconnects of the digital system. The designed tool is based on utilization of controllability and observability measurement for the estimation of overall system's testability. The algorithmic procedures are tested, verified and demonstrated through a large number of simulated digital systems. As examples some of the simulated results are embedded in this paper.

Scan BIST with biased scan test signals

The conventional test-per-scan built-in self-test (BIST) scheme needs a number of shift cycles followed by one capture cycle. Fault effects received by the scan flipflops are shifted out while shifting in the next test vector like scan testing. Unlike deterministic testing, it is unnecessary to apply a complete test vector to the scan chains. A new scan-based BIST scheme is proposed by properly controlling the test signals of the scan chains. Different biased random values are assigned to the test signals of scan flip-flops in separate scan chains. Capture cycles can be inserted at any clock cycle if necessary. A new testability estimation procedure according to the proposed testing scheme is presented. A greedy procedure is proposed to select a weight for each scan chain. Experimental results show that the proposed method can improve test effectiveness of scan-based BIST greatly, and most circuits can obtain complete fault coverage or very close to complete fault coverage.

Using Weighted Scan Enable Signals to Improve Test Effectiveness of Scan-Based BIST

The conventional test-per-scan built-in self-test (BIST) scheme needs a number of shift cycles followed by one capture cycle. Fault effects received by the scan flip-flops are shifted out while shifting in the next test vector, like scan testing. Unlike deterministic testing, it is unnecessary to apply a complete test vector to the scan chains. A new scan-based BIST scheme is proposed by properly controlling the scan enable signals of the scan chains. Different weighted values are assigned to the scan enable signals of scan flip-flops in separate scan chains. Capture cycles can be inserted at any clock cycle if necessary. A new testability estimation procedure according to the proposed testing scheme is presented. A greedy procedure is proposed to select a weight for each scan chain. Experimental results show that the proposed method can improve test effectiveness of scan-based BIST greatly and most circuits can obtain complete fault coverage or very close to complete fault coverage.

A functional-level testability measure for register-level circuits and its estimation

Estimation of circuit testability is an important issue when evaluating the circuit design. A testability measure indicates how easy or difficult it would be to generate tests for the circuit. STAFAN (Statistical Fault Analysis) is a well known gate-level testability analysis program which predicts the fault coverage of a digital circuit under the stuck-at fault model, without actually performing fault simulation. STAFAN offers speed advantage over other testability analysis programs such as SCOAP; further, it explicitly predicts the fault coverage for a given test set, unlike other testability measures which are harder to interpret. We show how a STAFAN-like testability analysis program can be constructed for circuits built out of register-level modules such as adders, multipliers, multiplexers, and busses. Our tool, which we call FSTAFAN, is useful in a testability-driven high-level synthesis environment. We have implemented FSTAFAN on a Sun/SPARC workstation and describe its performance on some register-level circuits.

Test Generation and Fault Simulation for Cell Fault Model using Stuck-at Fault Model based Test Tools

Cell Fault Model (CFM) is a well-adopted functional fault model used for cell-based circuits. Despite of the wide adoption of CFM, no test tool is available for the estimation of CFM testability. The vast majority of test tools are based on the single stuck-at fault model. In this paper we introduce a method to calculate the CFM testability of a cell-based circuit using any single stuck-at fault based test tool. Cells are substituted by equivalent cells and Test Generation and Fault Simulation for CFM are emulated by Test Generation and Fault Simulation for a set of single stuck-at faults of the equivalent cells. The equivalent cell is constructed from the original cell with a simple procedure, with no need of knowledge of gate-level implementation, or its function. With the proposed methodology, the maturity and effectiveness of stuck-at fault based tools is used in testing of digital circuits, with respect to Cell Fault Model, without developing new tools.

Testing core-based systems: a symbolic methodology

Because they must rely on vendor-provided test patterns, designers of core-based systems are forced to use expensive scan-based test techniques. The authors' alternative solution exploits the expressiveness of binary decision diagrams to provide test generation for the system and testability estimation and improvement of its components.

Metric framework for object-oriented real-time systems specification languages

In this paper, a framework for maintaining control of and analyzing object-oriented system specifications of real-time systems by using a set of metrics covering technical, cognitive, and process-oriented views is presented. The indicators defined can be u nsed for monitoring the evolution of system quality and for effort prediction. The use of metrics for the estimation of reusability, verifiability, and testability is analyzed. The metric framework is integrated in a CASE tool named TOOMS, which is based on TROL, a dual object-oriented language with both descriptive and operational capabilities. TOOMS allows one to describe the system at different levels of structural abstractions and at different levels of specification detail, such as many other languages and models for real-time systems (e.g., OSDL, ObjectTime, ObjectChart). According to this, the metrics proposed are capable of producing estimations at each level of system specification, thus allowing incremental specification/metrication. The metric framework must be regarded as a support for controlling the process of software development in order to guarantee the final quality.

A beta model for estimating the testability and coverage distributions of a VLSI circuit

A relation between fault coverage and testability is employed to predict population coverage. The testability profile is modeled as a mixture of a discrete impulse function and a continuous beta distribution. The parameters of the modeled distribution are estimated from fault coverage data obtained on a sample of faults. The beta distribution is chosen due to its flexible nature. The computed values of the beta parameters are dependent on the distribution of input vectors. Experimental results on three of the large ISCAS-89 circuits reflect the accuracy of the estimated fault coverage. Applications of the presented work include test generation by fault sampling, testability estimation, and test length predictions.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

COMELOT: a computer-aided measure for logic testability

This paper describes the theory and application of a testability assessment program, called CAMELOT, which has been developed for British Telecom. The program is intended for use as an interactive design aid, the testability predictions produced allowing the designer to make the best use of the range of testability improvement techniques available. CAMELOT uses a model of the test generation process to calculate controllability and observability values for each circuit node. These values measure the ease with which the node concerned can be set to a desired logic level and the ease with which its state can be observed respectively. The calculations take into account the possibility that a stored state device may have either an initialisation requirement or transient states. By combining the sets of values calculated, testability estimates can be produced for each circuit node and for the circuit as a whole. The paper describes the concepts of CAMELOT, relates it to other testability measures that have been described in the open literature and gives examples of its use.