Abstract
This paper presents a probabilistic based software tool for estimation of digital systems' testability. The tool allows fast computation to estimate testability in linear time complexity regarding the number of components and interconnects of the digital system. The designed tool is based on utilization of controllability and observability measurement for the estimation of overall system's testability. The algorithmic procedures are tested, verified and demonstrated through a large number of simulated digital systems. As examples some of the simulated results are embedded in this paper.
Highlights
Digital devices have become a hot topic of interest and research[1,2,3,4,5,6,7]
Some of the basic foundation of these methods depends on the knowledge of the analytical modelling of the controllability and the observability of the Digital System Under Test (DSUT)
The results obtained for basic digital systems like 3x8 decoder, 4x2 multiplexer and 4-bit comparator have been shown in Figures 8, 9 and 10 respectively
Summary
Digital devices have become a hot topic of interest and research[1,2,3,4,5,6,7]. Major techniques like Fault Diagnosis, Design for Test (DFT), Built-In Self-Test (BIST) and Scan methods are being heavily researched[8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28]. Some of the basic foundation of these methods depends on the knowledge of the analytical modelling of the controllability and the observability of the Digital System Under Test (DSUT). The study of the probabilistic model of the DSUT eases the problem in identifying the weak links in the digital system. It becomes important to understand these concepts and have a tool to help in obtaining their values for any given digital system. Probabilistic modeling is based on the probabilistic nature of each logic gates in the digital system. The probability of logic 1 at the two inputs is taken as 0.5, that is; P(i1) = P(i2) = 0.5. The probability of logic 1 at the output of an AND gate; P2(1) is the product of P(i1) and P(i2). The probability of logic 1 at the output of an AND gate; P2(1) is the product of P(i1) and P(i2). (2)
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