Test Set Size Research Articles

Improved free R factors for cross-validation of macromolecular structure - importance for real-space refinement.

Improvements in free R cross-validation are based on changed scaling procedures and the use, in map calculation, of estimates of the validation amplitudes which are independent of the actual observed values. The deleterious effects of the omitted test data are mitigated by reduction of the test-set size, which is made possible by constraining test and working sets to share the same scaling coefficients, thereby reducing the degrees of freedom and the dependence of free R on data selection. Further improvements come with use of a modified free R factor, R freeTA. Instead of omitting the validation reflections from map calculation, their amplitudes are replaced by the average of resolution peers that is (nearly) independent of the actual cross-validation amplitudes. The improvements are relevant to model building, phase refinement by density modification and especially to real-space refinement. Although for real data at about 3 A resolution, free R factors of about 0.25 are affected little, the precision of the structure is improved by about 0.1 A. Tests with simulated data show that with good agreement between observed and calculated amplitudes (as in very high resolution studies or simulated refinement tests), free R factors can be improved by factors greater than two.

Scalable Test Generators for High-Speed Datapath Circuits

This paper explores the design of efficient test sets and test-pattern generators for on-line BIST. The target applications are high-performance, scalable datapath circuits for which fast and complete fault coverage is required. Because of the presence of carry-lookahead, most existing BIST methods are unsuitable for these applications. High-level models are used to identify potential test sets for a small version of the circuit to be tested. Then a regular test set is extracted and a test generator TG is designed to meet the following goals: scalability, small test set size, full fault coverage, and very low hardware overhead. TG takes the form of a twisted ring counter with a small decoder array. We apply our technique to various datapath circuits including a carry-lookahead adder, an arithmetic-logic unit, and a multiplier-adder.

The AETG system: an approach to testing based on combinatorial design

This paper describes a new approach to testing that uses combinatorial designs to generate tests that cover the pairwise, triple, or n-way combinations of a system's test parameters. These are the parameters that determine the system's test scenarios. Examples are system configuration parameters, user inputs and other external events. We implemented this new method in the AETG system. The AETG system uses new combinatorial algorithms to generate test sets that cover all valid n-way parameter combinations. The size of an AETG test set grows logarithmically in the number of test parameters. This allows testers to define test models with dozens of parameters. The AETG system is used in a variety of applications for unit, system, and interoperability testing. It has generated both high-level test plans and detailed test cases. In several applications, it greatly reduced the cost of test plan development.

Pronunciation by Analogy: Impact of Implementational Choices on Performance

Pronunciation by analogy (PbA) is an emerging, data-driven technique with potential application in text-to-speech (TTS) systems, as well as being an influential psychological model of reading aloud. The underlying idea is that a pronunciation for an unknown word (i.e., one not in the dictionary, or lexicon, of the human or machine “reader”) is assembled by matching substrings of the input to substrings of known, lexical words, hypothesizing a partial pronunciation for each matched substring from the lexical knowledge of the “reader,” and concatenating the partial pronunciations. This paper assesses the capability of PbA to derive pronunciations for unknown words of English. As a psychological model, PbA is “under-specified,” that is, the implementor of a simulation of the process faces detailed choices which can only be resolved by trial and error. One goal for this paper is to explore the impact of certain basic implementational choices on the performance of PbA systems. The variables studied are the specific lexical database used as the basis of the analogy process, the way of ranking/scoring candidate pronunciations, and the effect of manual versus automatic alignment of letters and phonemes. When tested with short (monosyllabic) pseudowords previously used in experimental psychology studies, the lowest error rate achieved is 14.3% (for a test set of size 70). We conclude that current PbA systems are at best poor models of pseudoword pronunciation by humans. To assess their suitability for use in a TTS application, in which multisyllabic words will be encountered, the implementations have also been tested with lexical words temporarily removed from the dictionary. The best performance obtained was 93.5% phonemes correct (corresponding to 67.9% words correct) for a 16,280-word dictionary. This is vastly superior to the 25.7% words correct obtained using a set of popular letter-to-sound rules, indicating considerable scope for analogy methods to be exploited in future TTS systems.

Polynomial size test sets for commutative languages

It is proved that any commutative language over an alphabet of n symbols possesses a test set of size O (n 2 ). If the Parikh-map of the language is a linear set, then the minimum size of the test set is O (n log n). A finite commutative language over an alphabet of n symbols such that the smallest test set for the language is of size Ω (n 2 ) is shown to exist.

Distributed Test Pattern Generation for Stuck-At Faults in Sequential Circuits

Automatic test pattern generation (ATPG) remains one of the most complex CAD tasks. Therefore, numerous methods were proposed to speed up ATPG by using parallelism. In this paper, we focus on parallelizing ATPG for stuck-at faults in sequential circuits by combining fault and search space parallelism. Fault parallelism is applied to so-called easy-to-detect faults. The main task of this approach is to find a best-suited partitioning of the fault list, based on dependencies between faults. For hard-to-detect faults left by fault parallelism, search space partitioning is applied, integrating depth-first and breadth-first search. Since a small test set size is mandatory for a cheap test and fault parallelism increases the number of test patterns, test set compaction is done in a post-processing phase. Results show that our approach is not only capable of achieving potentially superlinear speedups, but also improves test set quality. The parallel environment we use consists of a network of 100 workstations connected via ethernet.

Fault-based ATPG for linear analog circuits with minimal size multifrequency test sets

An automatic test pattern generation (ATPG) procedure for linear analog circuits is presented in this work. A fault-based multifrequency test approach is considered. The procedure selects a minimal set of test measures and generates the minimal set of frequency tests which guarantee maximum fault coverage and, if required, maximal fault diagnosis, of circuit AC hard/soft faults. The procedure is most suitable for linear time-invariant circuits which present significant frequency-dependent fault effects. For test generation, the approach is applicable once parametric tests have determined DC behaviour. The advantage of this procedure with respect to previous works is that it guarantees a minimal size test set. For fault diagnosis, a fault dictionary containing a signature of the effects of each fault in the frequency domain is used. Fault location and fault identification can be achieved without the need of analog test points, and just in-circuit checkers with an observable go/no-go digital output are required for diagnosis. The procedure is exemplified for the case of an analog biquadratic filter. Three different self-test approaches for this circuit are considered. For each self-test strategy, a set of several test measures is possible. The procedure selects, in each case, the minimal set of test measures and the minimal set of frequency tests which guarantee maximum fault coverage and maximal diagnosis. With this, the self-test approaches are compared in terms of the fault coverage and the fault diagnosability achieved.

Test Error Fluctuations in Finite Linear Perceptrons

We examine the fluctuations in the test error induced by random, finite, training and test sets for the linear perceptron of input dimension n with a spherically constrained weight vector. This variance enables us to address such issues as the partitioning of a data set into a test and training set. We find that the optimal assignment of the test set size scales with n2/3.

On the testability of iterative logic arrays

The problem of detecting single cellular faults in arbitrarily large one-dimensional, unilateral, combinational iterative logic array (= ILAs) is considered. Fault patterns (= FPs) of the ILA's basic cell are introduced to characterize any cellular fault. Testability properties like (full, partial) testability, redundancy, test complexity of FPs are studied. Based on this analysis we prove that only two test complexity classes exist: the minimum size of a complete test set of an ILA is either constant—in this case the ILA is called C-testable — or linear in the length of the ILA. Furthermore, depending on the type of the FP that is considered new efficient algorithms for the determination of the test complexity and the construction of complete test sets are presented. In particular, we reduce the exponential worst case complexity of the construction given in (Friedman, 1973) to a polynomial worst case bound (measured in the size of the function table for the basic cell).

Finite-size effects and optimal test set size in linear perceptrons

Fluctuations in the test error are important in the learning theory of finite-dimensional systems as they represent how well the test error matches the average test error. By explicitly finding the variance of the test error due to randomness present in both the data set and algorithm for a linear perceptron of dimension n, we are able to address such questions as the optimal test set size. Where exact results were not tractable, a good approximation is given to the variance. We find that the optimal test set size possesses a phase transition between linear and 2/3 power-law scaling in the system size n.

Polynomial Size Test Sets For Context-Free Languages

We prove that each context-free language possesses a test set of size O(m6), where m is the number of productions in a grammar-producing the language. A context-free grammar generating the test set can be found in polynomial time by a sequential algorithm. It improves the doubly exponential upper bound from [2] and single exponential one from J. Karhumäki, W. Rytter, and S. Jarominek (Theoret. Comput. Sci.116 (1993), 305-316). On the other hand, we show that the lower bound for the problem is Ω(m3) and that the lower bound for the size of a test set for a language defined over n-letter alphabet is Ω(n3).

Delay fault coverage, test set size, and performance trade-offs

The main disadvantage of the path delay fault model is that to achieve 100% testability every path must be tested. Since the number of paths is usually exponential in circuit size, this implies very large test sets for most circuits. Not surprisingly, all known analysis and synthesis techniques for 100% path delay fault testability are computationally infeasible on large circuits. We prove that 100% delay fault testability is not necessary to guarantee the speed of a combinational circuit. There exist path delay faults which can never impact the circuit delay (computed using any correct timing analysis method) unless some other path delay faults also affect it. These are termed robust dependent delay faults and need not be considered in delay fault testing. Necessary and sufficient conditions under which a set of path delay faults is robust dependent are proved; this yields more accurate and increased delay fault coverage estimates than previously used. Next, assuming only the existence of robust delay fault tests for a very small set of paths, we show how the circuit speed (clock period) can be selected such that 100% robust delay fault coverage is achieved. This leads to a quantitative tradeoff between the testing effort (measured by the size of the test set) for a circuit and the verifiability of its performance. Finally, under a bounded delay model, we show that the test set size can be reduced while maintaining the delay fault coverage for the specified circuit speed. Examples and experimental results are given to show the effect of these three techniques on the amount of delay fault testing necessary to guarantee correct operation.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Built-in self test for C-testable ILA's

Testing of one-dimensional (1-D) unilateral iterative logic arrays (ILA's) of combinational cells with constant test vectors is studied and the concept of one repetition length (ORL) within the tests used for testing C-testable arrays is described. The impact of ORL on the test set size and the design of the test generator are discussed. ORL can dramatically reduce the on-chip test generator size with a negligible increase in the test set size. ORL, coupled with a single distinguishing sequence (DS) for ILA's with cell vertical outputs has proved to be attractive in terms of both reduced test set size and reduced test generator size. ORL testability can be used for C-testable arrays with single faulty cell and multiple faulty cells. The technique for using a single linear finite state machine (LFSM) for generating the necessary deterministic test patterns followed optionally by pseudorandom patterns from the same automaton is discussed. Use of an LFSM as a built-in test generator for only deterministic tests for 1-D ILA's is covered. With ORL, a compact LFSM based built-in self test (BIST) generator can deliver the test vectors to all the cells in the array. The exact probability distribution equation has been developed for additional bits needed to map a nonlinear machine (FSM) definition into a LFSM definition. The distribution clearly shows that the expected number of additional bits is very small, often zero.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Aliasing computation using fault simulation with fault dropping

It is generally thought that accurate analysis of aliasing requires non-fault dropping fault simulation. We show that fault dropping is possible when computing the exact aliasing of modeled faults for common output response compression circuits. The fault dropping process is most effective when the test set size is small. Extensions to large test sets are also considered. We present a fault simulation procedure that takes maximum advantage of fault dropping and present experimental results to support its effectiveness.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits

This paper presents new cost-effective heuristics for the generation of minimal test sets. Both dynamic techniques, which are introduced into the test generation process, and a static technique, which is applied to already generated test sets, are used. The dynamic compaction techniques maximize the number of faults that a new test vector detects out of the yet-undetected faults as well as out of the already-detected ones. Thus, they reduce the number of tests and allow tests generated earlier in the test generation process to be dropped. The static compaction technique replaces N test vectors by M<N test vectors, without loss of fault coverage. During test generation, we also find a lower bound on test set size. Experimental results demonstrate the effectiveness of the proposed techniques.

Dynamic probe scheduling optimization for MCM substrate test

We propose an improved integrated test generation/optimization algorithm for Multichip Module (MCM) substrate verification using two-probe testers. The goal of this work is to reduce the substrate testing time while providing complete coverage for open, short, and high net resistance faults. We approach this objective via two directions, namely test set size reduction and efficient probe scheduling. The test set size reduction is achieved by eliminating redundant tests associated with conventional approaches. The probe scheduling problem is formulated as a dynamical multi-dimensional Traveling Salesman Problem for probe sequence optimization. A simulated annealing based algorithm is devised to simultaneously take these two factors into consideration during the integrated test generation/optimization process. Since there exist numerous test sets providing complete fault coverage for a given design, our algorithm dynamically selects preferred ones by invoking an efficient validation routine during the test generation/optimization. Experiments conducted on industrial substrates using a two-probe tester showed that the test sets generated by our algorithm are able to reduce the testing time by over 38% compared to those generated by an in-house patented package.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Automatically generating test data from a Boolean specification

This paper presents a family of strategies for automatically generating test data for any implementation intended to satisfy a given specification that is a Boolean formula. The fault detection effectiveness of these strategies is investigated both analytically and empirically, and the costs, assessed in terms of test set size, are compared.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A totally self-checking checker for a parallel unordered coding scheme

Bose has developed a parallel unordered coding scheme using only r checkbits for 2/sup r/ information bits. This code can detect all unidirectional errors and requires simple parallel encoding/decoding. The information symbols can be separated from the check symbols. However, the information symbols containing all zeros and all ones need to be transformed to two other information symbols. This allows one to reduce the number of checkbits over Berger code by 1. Since information symbols containing a power-of-two number of bits are quite common, this coding scheme should become quite popular. The authors describe a modular, economical, and easily testable totally self-checking (TSC) checker design for the above code. The TSC concept is well known for providing concurrent error detection of transient as well as permanent faults. The design is self-testing with at most only 2r+16 codeword tests. This means that if k is the number of information bits, the size of the codeword test set is only O(log/sub 2/ k). This is the first known TSC checker design for this code. >

The complexity of sparse polynomial interpolation over finite fields

We consider the problem of interpolating and zero testing sparse multivariate polynomials over finite fields from their values given by a black box. We give an estimate of the size of a test set constructed by Clausen, Dress, Grabmeier, and Karpinski [2] and improve the previously known lower bounds on the size of a minimal test set. Further, we present for arbitrary finite fields a new interpolation algorithm that uses only evaluations over the ground field, thereby answering an open question of Dur and Grabmeier [3].

Optimal Testing and Design of Adders

On-the-fly calculations of area and performance are a typical part of the computer-aided iterative design process in VLSI, which aims at a satisfactory tradeoff of various conflicting objectives, among which are test-generation time and test-set size. However, determining test sets on-the-fly as one circuit is transformed into another is extremely difficult. Our goal is to add a test dimension to the design optimization process that complements methods concerned with area and performance optimization. We define a set of logic transformations that result in easily computed changes to test sets. Test-set preserving (TSP) transformations preserve a combinational circuit’s test sets, while test-set altering (TSA) transformations introduce a minimum number of tests needed to maintain completeness. We illustrate our approach with a family of adders that share area-efficient tree structures and differ in the amount of carry-lookahead used to accelerate carry computation. Members include the ripple-carry adder, which has no lookahead, and the standard carry-lookahead adder, which exploits lookahead across all inputs. It is straightforward to derive area and performance measures for this class of adders. Given an n-bit adder with lookahead degree k, we determine a sequence of circuit transformations that produce the adder of degree k2 and test sets of minimum size. Optimal test sets of size k(logkn + 1) + 2 result for arbitrary n and k, which improve significantly upon previously reported tests.