Test Point Selection Research Articles

Test generation for specification test of analog circuits using efficient test response observation methods

In this paper, a new automated test generation methodology for specification testing of analog circuits using test point selection and efficient analog test response waveform capture methods for enhancing the test accuracy is proposed. The proposed approach co-optimizes the construction of a multi-tone sinusoidal test stimulus and the selection of the best set of test response observation points. For embedded analog circuits, it uses a subsampling-based digitization method compatible with IEEE 1149.1 to accurately digitize the analog test response waveforms. The proposed specification approach uses ‘alternate test’ framework, in which the specifications of the analog circuit-under-test are computed (predicted) using statistical regression models that are constructed based on process variations and corresponding variations of test responses captured from different test observation points. The test generation process and the test point selection process aim to maximize the accuracy of specification prediction. Experimental results validating the proposed specification test approach are presented.

Entropy-Based Optimum Test Points Selection for Analog Fault Dictionary Techniques

An efficient method to select an optimum set of test points for dictionary techniques in analog fault diagnosis is proposed. This is done by searching for the minimum of the entropy index based on the available test points. First, the two-dimensional integer-coded dictionary is constructed whose entries are measurements associated with faults and test points. The problem of optimum test points selection is, thus, transformed to the selection of the columns that isolate the rows of the dictionary. Then, the likelihood for a column to be chosen based on the size of its ambiguity set is evaluated using the minimum entropy index of test points. Finally, the test point with the minimum entropy index is selected to construct the optimum set of test points. The proposed entropy-based method to select a local minimum set of test points is polynomial bounded in computational cost. The comparison between the proposed method and other reported test points selection methods is carried out by statistical experiments. The results indicate that the proposed method more efficiently and more accurately finds the locally optimum set of test points and is practical for large scale analog systems.

Hierarchical fault diagnosis of analog integrated circuits

This paper introduces a hierarchical-fault-diagnosis algorithm as an aid to testing analog and mixed signal circuits. The diagnosis approach is based on that introduced by Wey and others and makes use of the self-test algorithm, and the component-connection model. The main extension to these techniques is the use of a hierarchical approach whereby blocks of circuitry are grouped together leading to a reduction in matrix size, so making even large scale circuits diagnosable. Other improvements from this approach include a novel test-point selection procedure and the fact that hard faults can also be diagnosed, provided they lie completely within a hierarchical block. The overall algorithm is described and the results from example circuits show good functionality of the diagnosis algorithm. Fault masking and sensitivity to the simulation/measurement resolution of test point values are examined and are highlighted as future activities to further improve the approach.

Test point selection for analog fault diagnosis of unpowered circuit boards

Modern densely loaded circuit boards have posed problems for fault diagnosis with in-circuit testers because only limited physical access to the boards is allowed. In this paper, we present an efficient graph-based test-point selection algorithm for analog fault diagnosis of unpowered circuit boards. In addition to finding the sets of test points that allow one to differentiate between the elements under diagnosis, the algorithm can serve as a design for testability (DfT) guide for circuit board design. Experimental results on some industrial designs show that, in general, access to 50% of the nodes is sufficient to diagnose all the elements.

An Assessment of the Accuracy of Triangulated Irregular Networks (TINs) and Lattices in ARC/INFO

This paper evaluates the accuracy of triangulated irregular networks (TINs) and lattices in ARC/INFO. The results of an empirical comparison of the two models over two selected topographic sites are presented. Both vector and raster data were used to build the models. Three pairs of models were constructed based on 1,600, 4,000, and 9,000 sample points for the study area of the State Botanical Garden of Athens, Georgia, and 400, 800, and 1,600 sample points for the study area of Lake Lucerne of Wisconsin. The two models were assessed based on the same number of input sample points. Overall, TINs performed better than lattices. The quality of lattices decreased more dramatically than that of TINs when the number of sample points used for the construction of the models decreased. With an increase in the number of sample points used, the difference in performance between the two models decreased. The results of the evaluation directly depend on the comparison criteria and modeling algorithms. The evaluation is slightly sensitive to test indices used and the distribution of test points. The spatial pattern of residuals on spot heights was quite different from that on randomly selected test points. Users should choose models carefully based on the purpose of their application, the accuracy required, and the computer resources that are available.

Efficient test-point selection for scan-based BIST

We propose a test point selection algorithm for scan-based built-in self-test (BIST). Under a pseudorandom BIST scheme, the objectives are (1) achieving a high random pattern fault coverage, (2) reducing the computational complexity, and (3) minimizing the performance as well as the area overheads due to the insertion of test points. The proposed algorithm uses a hybrid approach to accurately estimate the profit of the global random testability of a test point candidate. The timing information is fully integrated into the algorithm to access the performance impact of a test point. In addition, a symbolic procedure is proposed to compute testability measures more efficiently for circuits with feedbacks so that the test point selection algorithm can be applied to partial-scan circuits. The experimental results show the proposed algorithm achieves higher fault coverages than previous approaches,with a significant reduction of computational complexity. By taking timing information into consideration, the performance degradation can he minimized with possibly more test points.

Digital IC device testing by transient signal analysis(TSA)

The Letter presents a new approach to testing digital circuits that uses the variations in the transient signals generated within digital circuits as a defect detection method. The IDD transients on the supply rails and voltage transients at selected test points are sampled over a test interval. Simulation experiments show that variations in the transient waveforms between defective and nondefective circuits exist and that these variations are sensitive to many types of defects even when they appear on off-sensitised paths. These variations can be analysed using pattern recognition techniques, and neural processing is proposed as the means of identifying the transient waveforms of defective devices .

Structural and behavioral synthesis for testability techniques

In this paper, a behavioral synthesis for testability system is presented. In this system, a testability modifier is connected to an existing behavioral level synthesis program, which accepts a circuit's behavioral description in C or VHDL as input. The outline of the system is as follows: (1) a testability analyzer is first applied to identify the hard-to-test areas in the circuit from the behavioral description; (2) a selection process is then applied to select test points or partial scan flip-flops. Selection is based on behavioral information rather than low-level structural description. This allows test point insertion or partial scan usage on circuits described as an interconnection of high level modules; (3) test statement insertion (TSI), an alternative to test point insertion and partial scan, is used to modify the circuit based on the selected test points. The major advantage of using TSI is a low pin count and test application time as compared to test point insertion and partial scan. In addition, TSI can be applied at the early design phase. This approach was implemented in a computer program, and applied to several sample circuits generated by a synthesis tool. The results are also presented.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Test-point selection and testability measures via QR factorization of linear models

An efficient algorithm is presented for selecting test points for use in applications such as calibration and fault diagnosis of electronic networks. The algorithm, based on QR factorization of the circuit sensitivity matrix, minimizes the prediction or estimation errors which result from random measurement error. A definition of testability based on the concept of minimum estimation error is also introduced. Practical examples are given.

Multifrequency measurement of testability with application to large linear analog systems

With increasing electronic circuit complexity, assessing the testability features becomes a necessity during the design, implementation, and operational or maintenance phases of an analog system. A quantitative measure of testability, based on several multifrequency stimuli, is adopted which is able to handle multiple faults and may provide information also on the degree of complexity encountered in a specific test. An efficient and practical algorithm is proposed which is associated with the result of Sen and Saeks and has a well-defined interpretation even with a large number of circuit parameters liable to failure. The described technique is a basis for optimizing the number and allocation of the selected test points; furthermore, it may serve as an aid in functional partitioning of the same system to facilitate testing and/or reduce computational complexity. An application to a classical active filter is also given.

Test point selection methods for the self-testing based analogue fault diagnosis system

Two methods for selecting test points of an analogue circuit are presented. The purpose of making such a selection is to increase the testability of the self-testing algorithm which is used to allocate the defective components of a given analogue circuit. Some closed relations between network equations and network topology have been investigated so that the computational effort can be reduced to minimum. This comes up with the first test point selection method. The second method for selecting a proper set of test points for fault diagnosis is a table look-up approach by which no complex matrix computation is required. Instead, only a few searches, which are based on a simple rule, on a binary matrix are needed. The cost of applying this table look-up method is that the testability of the target circuit due to the selected test points may not be the highest. Both methods are applicable to linear and nonlinear circuits.

Erratum: Test point selection methods for self-testing based analogue fault diagnosis system

Erratum: Test point selection methods for self-testing based analogue fault diagnosis system

A comparison of hierarchically paged and scrolling displays for fault finding

The selection of test points when fault finding with a hierarchically paged display is more efficient than when using a scrolling display. However, this difference is not found with more able subjects. An unexpected finding is that both displays seem to facilitate more consistent performance than that obtained when the operator's view of the system is unrestricted. The effect of restricting system information by a ‘window’, as both types of display do, is discussed in terms of strategies operators may adopt in consequence, in particular strategies to cope with memory load.

Optimal Test Point Selection for Sequential Manufacturing Processes

Consider a manufacturing process, such as the production of complex semiconductor devices, which consists of the sequential application of n possibly unreliable operations, t <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</inf> , t <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> , · · ·, <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</inf> . Let c <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">i</inf> be the cost incurred in performing operation t <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">i</inf> , and let p <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">i</inf> be the probability that t <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">i</inf> will be performed successfully. Clearly one would prefer to reject immediately any item as soon as a faulty operation has been performed upon it in order to avoid the unnecessary cost of further processing that item. For this purpose, we shall assume that, immediately following each operation t <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">i</inf> , it is possible to apply a perfectly reliable test T <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">i</inf> , for determining whether or not the item should be rejected at that point, where the cost incurred by applying T <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">i</inf> depends only upon the point i of test application and the last previous point at which such a test was applied. Since the application of tests entails additional costs, careful analysis is required to determine which tests are sufficiently useful to justify that additional cost. Using a dynamic programming approach, we derive a useful and efficient algorithm which utilizes the test and operation costs, along with the operation failure probabilities, to determine a set of testing points which will result in the minimal expected manufacturing cost. We then show how it is possible to further improve upon our algorithm for the particular case in which all test costs depend only upon the point of test application.

Quantitative Test Techniques for Advanced Automatic Checkout

High-speed, digital, internally-programmed, automatic checkout equipment is a powerful test tool whose impact has not yet been felt in testing large complex systems. It has, in certain ways, much higher test capabilities than either a sequentially programmed machine or a human operator. For these capabilities to be harnessed, new test techniques are required to ensure that failures or weaknesses are detected and separated from normal drifts. These techniques involve the design-of-the-prime system to secure through instrumentation, wiring, test points, and other built-in provisions, precisely the kind and quantity of test data needed. The test techniques involve improvement of several present-day test practices. The selection of test points, for example, is based upon both broad and detailed quantitative factors related to probability-of-mission-success, and reliability, rather than upon intuition, but with ample opportunity for the exercise of the designer's judgment. In general, more data are required, but the pay-off is in greatly increased reliability and availability, together with lower net costs. The immediate objectives of failure detection, prediction, prevention, and isolation are defined and a test program is described whose purpose is to maximize the failure information content of the test data rather than to reconfirm abstract design parameters. One technique described is called ``inferential testing'' or ``introspective testing'' which, complemented by end-to-end testing, is especially powerful in testing closed-loop systems. Another approach and technique described is that of wringing all possible test data from a fixed set of test points by ``network testing.