Test Data Compression Technique Research Articles

Two-stage low power test data compression for digital VLSI circuits

In this paper, we present a hybrid X-filling and two-stage test data compression (TS-TDC) techniques for digital VLSI circuits to reduce the test power and test data volume respectively. The proposed hybrid X-filling combines adjacent filling and modified 4m filling technique to reduce the switching activities of the scan cells. It divides the unspecified bits present in the test cubes by multiples of 4 to increase the correlation between the consecutive test patterns which in turn provides better run length for test data reduction. The filled test cubes are encoded with two stage test data compression in order to reduce test data volume. In the first stage, the completely specified test sets are encoded using Alternative Statistical Run Length (ASRL) coding to enhance the test data compression. The compressed ASRL test set is encoded further using Run Length based Huffman Coding (RLHC) since ASRL codewords contain the maximum run length of oneâ;;s. Experimental results show that the proposed hybrid filling provides the scan-in average and peak-power transition reduction of 88% and 29% respectively against original test sets. The two-stage test data compression scheme achieves a maximum of 86% and an average of 76% compression ratio for ISCAS’89 benchmark circuits.

Test data compression using hierarchical block merging technique

Manufacturing of semiconductor devices at the sub-micron level has led to the introduction of huge number of faults. To ensure the quality of integrated circuits (ICs), enormous amount of test data is needed which, in turn, increases the overall test cost of the ICs. This study presents a hierarchical block-merging-based technique (HBMT) for test data compression, which appropriately encodes the test pattern blocks of fixed sizes at inter- and intra-block levels using lesser number of bits. The proposed technique works in four steps: segmentation of the entire length of test data into equal length blocks; categorisation of test blocks as compatible blocks and unique blocks; merging of compatible blocks to form representative pattern block, which is further merged at sub-block level; and compression of the non-compatible (unique) blocks using different encoding cases. Experimental results performed on various international symposium for circuits and systems (ISCAS)' 89 benchmark circuits demonstrate the effectiveness of the proposed test data compression technique. It is found that application of HBMT can improve the compression efficiency by an average of 73% along with a reduction in the test application time. This study also presents the decoder architecture.

Temperature and data size trade-off in dictionary based test data compression

This paper proposes a new thermal-aware test data compression technique using dictionary-based coding. Large test data volume and rise in chip temperature during a test, are the two major challenges for the test engineers. Efficient filling of the don't care bits of the test patterns minimises the transition count in the scan chains, which in turn reduces the temperature of the chip to a large extent. On the other hand, high test data compression can be achieved by filling the don't-cares in a manner to get more similar sub-vectors within the test vectors. Although, both the problems rely on don't-care bit filling, most of the existing works have considered them separately. Moreover, it has been observed that, in general, thermal-aware don't-care filling leads to poor test compression, while a compression-aware don't-care filling produces high temperature. However, a high test compression with low-temperature is the most desirable expectation. In our work, we have combined the temperature reduction and the test data compression into a single problem and solved it. We have presented an integrated approach that can perform a trade-off between temperature and test compression. Experimental results on ISCAS'89, ITC'99 and IWLS'05 benchmarks show the flexibility of the proposed method to achieve a balance between temperature and test compression. The work has further been extended to reduce temperature without sacrificing compression.

Low Power Scan Chain Reordering Method with Limited Routing Congestion for Code-based Test Data Compression

Various test data compression techniques have been developed to reduce the test costs of system–on–a–chips. In this paper, a scan chain reordering algorithm for code–based test data compression techniques is proposed. Scan cells within an acceptable relocation distance are ranked to reduce the number of conflicts in all test patterns and rearranged by a positioning algorithm to minimize the routing overhead. The proposed method is demonstrated on ISCAS ’89 benchmark circuits with their physical layout by using a 180 nm CMOS process library. Significant improvements are observed in compression ratio and test power consumption with minor routing overhead.

Test Data Compression Using Variable Prefix Run Length (VPRL) Code

One of the major challenges in testing a system-on-a-chip (SoC) is dealing with the large test data volume and large scan power consumption. To reduce the volume of test data, several test data compression techniques have been proposed. This paper presents a new test data compression scheme, which reduces test data volume for a system-on-a-chip (SoC). The proposed approach is based on the use of MT (Minimum Transition)-fill technique and Variable Prefix Run Length (VPRL) codes for test data compression. These VPRL codes can efficiently compress the data streams, that are composed of both runs of 0s and 1s. Experimental results for ISCAS’89 benchmark circuits supports and proves the proposed approach, better to the other existing techniques, by reducing test data volume.

High-Quality Statistical Test Compression With Narrow ATE Interface

In this paper, we present a novel compression method and a low-cost decompression architecture that combine the advantages of both symbol-based and linear-based techniques and offer a very attractive unified solution that removes the barriers of existing test data compression techniques. Besides the traditional goals of high compression and short test application time, the proposed method also offers low shift switching activity and high unmodeled defect coverage at the same time. In addition, it favors multi-site testing as requires a very low pin-count interface to the automatic test equipment. Finally, contrary to existing techniques, it provides an integrated solution for testing multi-core system on chips (SoCs) as it is suitable for cores of both known and unknown structures that usually coexist in SoCs.

Test Data Compression Using Selective Sparse Storage

For today's very large scale integrated circuits, test data volume is recognized as a major contributor to the cost of manufacturing testing. Test data compression addresses this problem by reducing the test data volume without affecting the overall system performance. This paper proposes a new test data compression technique using selective sparse storage. Test sets are partitioned into four kinds of blocks of uniform length, all-0 blocks, all-1 blocks, sparse blocks and characterless blocks. Blocks are encoded appropriately based on the occurrence of them. They are encoded into 0, 10, 110 + number of the sparse bits + locations of all the sparse bits, and 111 + the block itself, respectively. Two algorithms are proposed for how to select the sparse blocks from test sets. A theoretical analysis for our selective sparse storage shows the new compression technique outperforms the conventional test data compression approaches. Experimental results illustrate the flexibility and efficiency of the new method, which is consistent with the theoretical analysis.

A Twin Symbol Encoding Technique Based on Run-Length for Efficient Test Data Compression

Recent test data compression techniques raise concerns regarding power dissipation and compression efficiency. This letter proposes a new test data compression scheme, twin symbol encoding, that supports block division skills that can reduce hardware overhead. Our experimental results show that the proposed technique achieves both a high compression ratio and low-power dissipation. Therefore, the proposed scheme is an attractive solution for efficient test data compression.

Test Data Compression Using Efficient Bitmask and Dictionary Selection Methods

Higher circuit densities in system-on-chip (SOC) designs have led to drastic increase in test data volume. Larger test data size demands not only higher memory requirements, but also an increase in testing time. Test data compression addresses this problem by reducing the test data volume without affecting the overall system performance. This paper proposes a novel test data compression technique using bitmasks which provides a substantial improvement in the compression efficiency without introducing any additional decompression penalty. The major contributions of this paper are as follows: 1) it develops an efficient bitmask selection technique for test data in order to create maximum matching patterns; 2) it develops an efficient dictionary selection method which takes into account the bitmask based compression; and 3) it proposes a test compression technique using efficient dictionary and bitmask selection to significantly reduce the testing time and memory requirements. We have applied our method on various test data sets and compared our results with other existing test compression techniques. Our algorithm outperforms existing dictionary-based approaches by up to 30%, giving a best possible test compression of 92%.

Test data compression technique based on partial data block reuse in SoC

Test data compression technique based on partial data block reuse in SoC

SoC Test Data Compression Technique Based on RLE-G

Test data compression has been an effective way to reduce test data volume and test time, as well as to solve automatic test equipment (ATE) memory and bandwidth limitation. We analyze the limitations of current test data compression algorithm and draw on the previous experience to deduce an optimal compression coding model suitable for SoC test data. In addition, in this paper we make full use of the relevance of the test vectors and the advantages of statistical coding to present an efficient test data compression method RLE-G based on the coding model, and give the RLE-G the optimal compression efficiency of the boundary conditions and realization steps. The experimental results for ISCAS 89 benchmark circuits demonstrate RLE-G have the excellent advantages of high compression ratio.

Run-Length-Based Test Data Compression Techniques: How Far from Entropy and Power Bounds?—A Survey

The run length based coding schemes have been very effective for the test data compression in case of current generation SoCs with a large number of IP cores. The first part of paper presents a survey of the run length based codes. The data compression of any partially specified test data depends upon how the unspecified bits are filled with 1s and 0s. In the second part of the paper, the five different approaches for “don't care” bit filling based on nature of runs are proposed to predict the maximum compression based on entropy. Here the various run length based schemes are compared with maximum data compression limit based on entropy bounds. The actual compressions claimed by the authors are also compared. For various ISCAS circuits, it has been shown that when the X filling is done considering runs of zeros followed by one as well as runs of ones followed by zero (i.e., Extended FDR), it provides the maximum data compression. In third part, it has been shown that the average test power and peak power is minimum when the don't care bits are filled to make the long runs of 0s as well as 1s.

Split variable-length input Huffman code with application to test data compression for embedded cores in SOCs

In this article, a run length encoding-based test data compression technique has been addressed. The scheme performs Huffman coding on different parts of the test data file separately. It has been observed that up to a 6% improvement in compression ratio and a 29% improvement in test application time can be achieved sacrificing only about 6.5% of the decoder area. We have compared our results with the other contemporary works reported in the literature. It has been observed that for most of the cases, our scheme produces a better compression ratio and that the area requirements are much less.

Efficient test compression technique based on block merging

Test data compression is an effective methodology for reducing test data volume and testing time. The author presents a new test data compression technique based on block merging. The technique capitalises on the fact that many consecutive blocks of the test data can be merged together. Compression is achieved by storing the merged block and the number of blocks merged. It also takes advantage of cases where the merged block can be filled by all 0s or all 1s. Test data decompression is performed on chip using a simple circuitry that repeats the merged block the required number of times. The decompression circuitry has the advantage of being test-data-independent. Experimental results on benchmark circuits demonstrate the effectiveness of the proposed technique compared with other coding-based compression techniques.

Test data compression for system-on-a-chip using extended frequency-directed run-length code

One of the major challenges in testing a system-on-a-chip is dealing with the large volume of test data. To reduce the volume of test data, several test data compression techniques have been proposed. Frequency-directed run-length (FDR) code is a variable-to-variable run length code based on encoding runs of 0s. It is demonstrated that higher test data compression can be achieved based on encoding both runs of 0s and 1s. An extension to the FDR code is proposed and by experimental results its effectiveness in achieving a higher compression ratio is demonstrated.

A Selective Scan Slice Encoding Technique for Test Data Volume and Test Power Reduction

Scan architectures, though widely used in modern designs for testing purpose, are expensive in test data volume and power consumption. To solve these problems, we propose in this paper to modify an existing test data compression technique (Wang Z, Chakrabarty K in Test data compression for IP embedded cores using selective encoding of scan slices. IEEE International Test Conference, paper 24.3, 2005) so that it can simultaneously address test data volume and power consumption reduction for scan testing of embedded Intellectual Property (IP) cores. Compared to the initial solution that fill don't-care bits with the aim of reducing only test data volume, here the assignment is performed to minimize also the power consumption. The proposed power-aware test data compression technique is applied to the ISCAS'89 and ITC'99 benchmark circuits and on a number of industrial circuits. Results show that up to 14× reduction in test data volume and 98% test power reduction can be obtained simultaneously.

Relationship Between Entropy and Test Data Compression

The entropy of a set of data is a measure of the amount of information contained in it. Entropy calculations for fully specified data have been used to get a theoretical bound on how much that data can be compressed. This paper extends the concept of entropy for incompletely specified test data (i.e., that has unspecified or don't care bits) and explores the use of entropy to show how bounds on the maximum amount of compression for a particular symbol partitioning can be calculated. The impact of different ways of partitioning the test data into symbols on entropy is studied. For a class of partitions that use fixed-length symbols, a greedy algorithm for specifying the don't cares to reduce entropy is described. It is shown to be equivalent to the minimum entropy set cover problem and thus is within an additive constant error with respect to the minimum entropy possible among all ways of specifying the don't cares. A polynomial time algorithm that can be used to approximate the calculation of entropy is described. Different test data compression techniques proposed in the literature are analyzed with respect to the entropy bounds. The limitations and advantages of certain types of test data encoding strategies are studied using entropy theory

Test Data Compression Using a Hybrid Run-Length Code Method

This letter proposes a run-length code based test data compression technique capable of efficient compression. The proposed test compression method is based on a hybrid run-length encoding, which greatly reduces test data storage on the tester. The code words are carefully selected so as to increase the compression ratio for the test data. Also, a heuristic mapping algorithm and a scan latch reordering method for don't care values in the test cubes increase the compression ratio. Results indicate that the proposed code and heuristic mapping schemes are very efficient in reducing test data. Reduced test data results in less test storage and test time.

Nine-coded compression technique for testing embedded cores in SoCs

This paper presents a new test-data compression technique that uses exactly nine codewords. Our technique aims at precomputed data of intellectual property cores in system-on-chips and does not require any structural information of cores. The technique is flexible in utilizing both fixed- and variable-length blocks. In spite of its simplicity, it provides significant reduction in test-data volume and test-application time. The decompression logic is very small and can be implemented fully independent of the precomputed test-data set. Our technique is flexible and can be efficiently adopted for single- or multiple-scan chain designs. Experimental results for ISCAS'89 benchmarks illustrate the flexibility and efficiency of the proposed technique.

Reducing Test-Data Volume Using<tex>$P$</tex>-Testable Scan Chains in Circuits With Multiple Scan Chains

For a scan design with multiple scan chains, we say that a scan chain is P-testable if it is possible to achieve complete fault coverage for the circuit (i.e., detect all the detectable target faults) when the scan chain is driven from a source that produces values having a property P. For example, a scan chain is random-testable if it is possible to achieve complete fault coverage for the circuit when the scan chain is driven from a source of pseudorandom values for the complete test application process. In a similar way, we define periodic-testable and combination-testable scan chains. All the sources we consider for P-testable scan chains are simple to implement on-chip. By identifying P-testable scan chains and driving them from the appropriate on-chip sources, we reduce the number of scan chains that need to be driven from an external tester. In this way, we reduce the number of scan inputs that a tester needs to control and the amount of test data that the external tester needs to store and apply to the circuit. Existing test data compression techniques can be used to further reduce the test data volume.