Abstract
Various test data compression techniques have been developed to reduce the test costs of system–on–a–chips. In this paper, a scan chain reordering algorithm for code–based test data compression techniques is proposed. Scan cells within an acceptable relocation distance are ranked to reduce the number of conflicts in all test patterns and rearranged by a positioning algorithm to minimize the routing overhead. The proposed method is demonstrated on ISCAS ’89 benchmark circuits with their physical layout by using a 180 nm CMOS process library. Significant improvements are observed in compression ratio and test power consumption with minor routing overhead.
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